6  * Copyright (C) 1999-2006 Helge Deller <deller@gmx.de> (07-13-1999)
10  * Cache and TLB management
55 void flush_data_cache_local(void *);  /* flushes local data-cache only */
56 void flush_instruction_cache_local(void); /* flushes local code-cache only */
60 /* On some machines (i.e., ones with the Merced bus), there can be
62  * by software. We need a spinlock around all TLB flushes to ensure
125 	    test_bit(PG_dcache_dirty, &folio->flags)) {  in __update_cache()
126 		while (nr--)  in __update_cache()
128 		clear_bit(PG_dcache_dirty, &folio->flags);  in __update_cache()
130 		while (nr--)  in __update_cache()
139 	seq_printf(m, "I-cache\t\t: %ld KB\n",   in show_cache_info()
142 		snprintf(buf, 32, "%lu-way associative", cache_info.dc_loop);  in show_cache_info()
143 	seq_printf(m, "D-cache\t\t: %ld KB (%s%s, %s, alias=%d)\n",  in show_cache_info()
146 		(cache_info.dc_conf.cc_sh ? ", shared I/D":""),  in show_cache_info()
153 		cache_info.dt_conf.tc_sh ? " - shared with ITLB":""  in show_cache_info()
157 	/* BTLB - Block TLB */  in show_cache_info()
163 		"BTLB fix-entr.\t: %d instruction, %d data (%d combined)\n"  in show_cache_info()
164 		"BTLB var-entr.\t: %d instruction, %d data (%d combined)\n",  in show_cache_info()
244 	printk("D-TLB conf: sh %d page %d cst %d aid %d sr %d\n",  in parisc_cache_init()
251 	printk("I-TLB conf: sh %d page %d cst %d aid %d sr %d\n",  in parisc_cache_init()
262 			printk(KERN_WARNING "Unexpected TLB configuration. "  in parisc_cache_init()
263 			"Will flush I/D separately (could be optimized).\n");  in parisc_cache_init()
269 	 *	(1 << (cc_block-1)) * (cc_line << (4 + cnf.cc_shift))  in parisc_cache_init()
271 	 * http://lists.parisc-linux.org/pipermail/parisc-linux/2004-June/023625.html  in parisc_cache_init()
272 	 * http://lists.parisc-linux.org/pipermail/parisc-linux/2004-June/023671.html  in parisc_cache_init()
279 	/* stride needs to be non-zero, otherwise cache flushes will not work */  in parisc_cache_init()
287 		panic("SMP kernel required to avoid non-equivalent aliasing");  in parisc_cache_init()
338 	 * The TLB is the engine of coherence on parisc.  The CPU is  in __flush_cache_page()
339 	 * entitled to speculate any page with a TLB mapping, so here  in __flush_cache_page()
341 	 * only alias mapping. This guarantees that the page is no-longer  in __flush_cache_page()
350 	if (vma->vm_flags & VM_EXEC)  in __flush_cache_page()
360 	/* Purge TLB entry to remove translation on all CPUs */  in flush_kernel_dcache_page_addr()
365 	/* Use tmpalias flush to prevent data cache move-in */  in flush_kernel_dcache_page_addr()
376 	/* Purge TLB entry to remove translation on all CPUs */  in flush_kernel_icache_page_addr()
381 	/* Use tmpalias flush to prevent instruction cache move-in */  in flush_kernel_icache_page_addr()
401 		if (--nr == 0)  in flush_icache_pages()
413 	pgd_t *pgd = mm->pgd;  in get_ptep()
480 	unsigned long i, nr, flags;  in flush_dcache_folio()  local
484 		set_bit(PG_dcache_dirty, &folio->flags);  in flush_dcache_folio()
490 	for (i = 0; i < nr; i++)  in flush_dcache_folio()
491 		flush_kernel_dcache_page_addr(kaddr + i * PAGE_SIZE);  in flush_dcache_folio()
496 	pgoff = folio->index;  in flush_dcache_folio()
506 	vma_interval_tree_foreach(vma, &mapping->i_mmap, pgoff, pgoff + nr - 1) {  in flush_dcache_folio()
507 		unsigned long offset = pgoff - vma->vm_pgoff;  in flush_dcache_folio()
510 		addr = vma->vm_start;  in flush_dcache_folio()
512 		if (offset > -nr) {  in flush_dcache_folio()
513 			pfn -= offset;  in flush_dcache_folio()
518 		if (addr + nr * PAGE_SIZE > vma->vm_end)  in flush_dcache_folio()
519 			nr = (vma->vm_end - addr) / PAGE_SIZE;  in flush_dcache_folio()
521 		if (old_addr == 0 || (old_addr & (SHM_COLOUR - 1))  in flush_dcache_folio()
522 					!= (addr & (SHM_COLOUR - 1))) {  in flush_dcache_folio()
523 			for (i = 0; i < nr; i++)  in flush_dcache_folio()
525 					addr + i * PAGE_SIZE,  in flush_dcache_folio()
526 					(pfn + i) * PAGE_SIZE);  in flush_dcache_folio()
531 			if (!(vma->vm_flags & VM_SHARED))  in flush_dcache_folio()
535 					old_addr, addr, vma->vm_file);  in flush_dcache_folio()
552 #define FLUSH_TLB_THRESHOLD (16*1024) /* 16 KiB minimum TLB threshold */
558 	unsigned long size;  in parisc_setup_cache_timing()  local
563 	alltime = mfctl(16) - alltime;  in parisc_setup_cache_timing()
565 	size = (unsigned long)(_end - _text);  in parisc_setup_cache_timing()
567 	flush_kernel_dcache_range((unsigned long)_text, size);  in parisc_setup_cache_timing()
568 	rangetime = mfctl(16) - rangetime;  in parisc_setup_cache_timing()
571 		alltime, size, rangetime);  in parisc_setup_cache_timing()
573 	threshold = L1_CACHE_ALIGN((unsigned long)((uint64_t)size * alltime / rangetime));  in parisc_setup_cache_timing()
586 	/* calculate TLB flush threshold */  in parisc_setup_cache_timing()
588 	/* On SMP machines, skip the TLB measure of kernel text which  in parisc_setup_cache_timing()
597 	size = (unsigned long)_end - (unsigned long)_text;  in parisc_setup_cache_timing()
600 	rangetime = mfctl(16) - rangetime;  in parisc_setup_cache_timing()
604 	alltime = mfctl(16) - alltime;  in parisc_setup_cache_timing()
606 	printk(KERN_INFO "Whole TLB flush %lu cycles, Range flush %lu bytes %lu cycles\n",  in parisc_setup_cache_timing()
607 		alltime, size, rangetime);  in parisc_setup_cache_timing()
609 	threshold = PAGE_ALIGN((num_online_cpus() * size * alltime) / rangetime);  in parisc_setup_cache_timing()
610 	printk(KERN_INFO "Calculated TLB flush threshold %lu KiB\n",  in parisc_setup_cache_timing()
615 	printk(KERN_INFO "TLB flush threshold set to %lu KiB\n",  in parisc_setup_cache_timing()
630 	ptep = get_ptep(vma->vm_mm, vmaddr);  in flush_cache_page_if_present()
639 	struct mm_struct *mm = vma->vm_mm;  in flush_cache_page_if_present()
686 	    end - start >= parisc_tlb_flush_threshold) {  in __flush_tlb_range()
691 	/* Purge TLB entries for small ranges using the pdtlb and  in __flush_tlb_range()
722 		usize += vma->vm_end - vma->vm_start;  in mm_total_size()
751 		flush_cache_pages(vma, vma->vm_start, vma->vm_end);  in flush_cache_mm()
757 	    || end - start >= parisc_cache_flush_threshold) {  in flush_cache_range()
761 		if (vma->vm_flags & VM_EXEC)  in flush_cache_range()
802  * as well as the TLB when clearing a PTE that's valid.
807 	struct mm_struct *mm = (vma)->vm_mm;  in ptep_clear_flush()
821  * from the vm_struct struct. I wasn't able to successfully handle the
830 	/* Prevent cache move-in */  in flush_cache_vmap()
833 	if (end - start >= parisc_cache_flush_threshold) {  in flush_cache_vmap()
850 	if (vm->flags & VM_IOREMAP) {  in flush_cache_vmap()
851 		physaddr = vm->phys_addr;  in flush_cache_vmap()
874 	/* Prevent cache move-in */  in flush_cache_vunmap()
891 void flush_kernel_vmap_range(void *vaddr, int size)  in flush_kernel_vmap_range()  argument
894 	unsigned long end = start + size;  in flush_kernel_vmap_range()
911 void invalidate_kernel_vmap_range(void *vaddr, int size)  in invalidate_kernel_vmap_range()  argument
914 	unsigned long end = start + size;  in invalidate_kernel_vmap_range()
944 		return -EFAULT;  in SYSCALL_DEFINE3()
960 			: "r" (end), "r" (dcache_stride), "i" (SR_USER));  in SYSCALL_DEFINE3()
975 			: "r" (end), "r" (icache_stride), "i" (SR_USER));  in SYSCALL_DEFINE3()