Home
last modified time | relevance | path

Searched +full:composite +full:- +full:mux +full:- +full:clock (Results 1 – 25 of 63) sorted by relevance

123

/linux/arch/arm/boot/dts/ti/omap/
H A Domap24xx-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Device Tree Source for OMAP24xx clock data
9 #clock-cells = <0>;
10 compatible = "ti,composite-mux-clock";
12 ti,bit-shift = <2>;
17 #clock-cells = <0>;
18 compatible = "ti,composite-clock";
23 #clock-cells = <0>;
24 compatible = "ti,composite-mux-clock";
26 ti,bit-shift = <6>;
[all …]
H A Domap3xxx-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Device Tree Source for OMAP3 clock data
9 #clock-cells = <0>;
10 compatible = "fixed-clock";
11 clock-frequency = <16800000>;
15 #clock-cells = <0>;
16 compatible = "ti,mux-clock";
22 #clock-cells = <0>;
23 compatible = "ti,divider-clock";
25 ti,bit-shift = <6>;
[all …]
H A Domap2430-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Device Tree Source for OMAP2430 clock data
10 #clock-cells = <0>;
11 compatible = "ti,composite-mux-clock";
17 #clock-cells = <0>;
18 compatible = "ti,composite-clock";
23 #clock-cells = <0>;
24 compatible = "ti,composite-mux-clock";
26 ti,bit-shift = <2>;
31 #clock-cells = <0>;
[all …]
H A Domap44xx-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Device Tree Source for OMAP4 clock data
9 #clock-cells = <0>;
10 compatible = "fixed-clock";
11 clock-output-names = "extalt_clkin_ck";
12 clock-frequency = <59000000>;
16 #clock-cells = <0>;
17 compatible = "fixed-clock";
18 clock-output-names = "pad_clks_src_ck";
19 clock-frequency = <12000000>;
[all …]
H A Domap54xx-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Device Tree Source for OMAP5 clock data
9 #clock-cells = <0>;
10 compatible = "fixed-clock";
11 clock-output-names = "pad_clks_src_ck";
12 clock-frequency = <12000000>;
16 #clock-cells = <0>;
17 compatible = "ti,gate-clock";
18 clock-output-names = "pad_clks_ck";
20 ti,bit-shift = <8>;
[all …]
H A Domap2420-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Device Tree Source for OMAP2420 clock data
10 #clock-cells = <0>;
11 compatible = "ti,composite-no-wait-gate-clock";
13 ti,bit-shift = <15>;
18 #clock-cells = <0>;
19 compatible = "ti,composite-mux-clock";
21 ti,bit-shift = <8>;
26 #clock-cells = <0>;
27 compatible = "ti,composite-clock";
[all …]
H A Domap36xx-omap3430es2plus-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Device Tree Source for OMAP34xx/OMAP36xx clock data
8 clock@a00 {
11 #clock-cells = <2>;
12 #address-cells = <1>;
13 #size-cells = <0>;
15 ssi_ssr_gate_fck_3430es2: clock-ssi-ssr-gate-fck-3430es2@0 {
17 #clock-cells = <0>;
18 compatible = "ti,composite-no-wait-gate-clock";
19 clock-output-names = "ssi_ssr_gate_fck_3430es2";
[all …]
/linux/Documentation/devicetree/bindings/clock/ti/
H A Dti,mux-clock.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/clock/ti/ti,mux-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Texas Instruments mux clock
10 - Tero Kristo <kristo@kernel.org>
13 This clock assumes a register-mapped multiplexer with multiple inpt clock
14 signals or parents, one of which can be selected as output. This clock does
24 register value selected parent clock
29 Some clock controller IPs do not allow a value of zero to be programmed
[all …]
H A Dcomposite.txt1 Binding for TI composite clock.
3 This binding uses the common clock binding[1]. It assumes a
4 register-mapped composite clock with multiple different sub-types;
6 a multiplexer clock with multiple input clock signals or parents, one
9 an adjustable clock rate divider, this behaves exactly as [3]
12 clock, this behaves exactly as [4]
15 merged to this clock. The component clocks shall be of one of the
16 "ti,*composite*-clock" types.
18 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
19 [2] Documentation/devicetree/bindings/clock/ti/ti,mux-clock.yaml
[all …]
/linux/drivers/clk/stm32/
H A Dclk-stm32-core.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) STMicroelectronics 2022 - All Rights Reserved
17 #include "clk-stm32-core.h"
18 #include "reset-stm32.h"
26 const struct stm32_rcc_match_data *data = match->data; in stm32_rcc_clock_init()
27 struct clk_hw_onecell_data *clk_data = data->hw_clks; in stm32_rcc_clock_init()
31 max_binding = data->maxbinding; in stm32_rcc_clock_init()
35 return -ENOMEM; in stm32_rcc_clock_init()
37 clk_data->num = max_binding; in stm32_rcc_clock_init()
39 hws = clk_data->hws; in stm32_rcc_clock_init()
[all …]
H A Dclk-stm32mp1.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) STMicroelectronics 2018 - All Rights Reserved
9 #include <linux/clk-provider.h>
17 #include <linux/reset-controller.h>
21 #include <dt-bindings/clock/stm32mp1-clks.h>
23 #include "reset-stm32.h"
171 "ck_hse", "pll4_r", "clk-hse-div2"
308 struct clk_mux mux; member
379 struct mux_cfg *mux; member
384 /* STM32 Composite clock */
[all …]
/linux/drivers/clk/rockchip/
H A Dclk-rv1126.c1 // SPDX-License-Identifier: GPL-2.0
4 * Author: Finley Xiao <finley.xiao@rock-chips.com>
7 #include <linux/clk-provider.h>
13 #include <dt-bindings/clock/rockchip,rv1126-cru.h>
216 MUX(CLK_RTC32K, "clk_rtc32k", mux_rtc32k_p, CLK_SET_RATE_PARENT,
220 MUX(SCLK_UART1_MUX, "sclk_uart1_mux", mux_uart1_p, CLK_SET_RATE_PARENT,
224 MUX(SCLK_UART0_MUX, "sclk_uart0_mux", mux_uart0_p, CLK_SET_RATE_PARENT,
228 MUX(SCLK_UART2_MUX, "sclk_uart2_mux", mux_uart2_p, CLK_SET_RATE_PARENT,
232 MUX(SCLK_UART3_MUX, "sclk_uart3_mux", mux_uart3_p, CLK_SET_RATE_PARENT,
236 MUX(SCLK_UART4_MUX, "sclk_uart4_mux", mux_uart4_p, CLK_SET_RATE_PARENT,
[all …]
H A Dclk-rk3308.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Author: Finley Xiao <finley.xiao@rock-chips.com>
7 #include <linux/clk-provider.h>
12 #include <dt-bindings/clock/rk3308-cru.h>
199 MUX(0, "clk_uart0_mux", mux_uart0_p, CLK_SET_RATE_PARENT,
203 MUX(0, "clk_uart1_mux", mux_uart1_p, CLK_SET_RATE_PARENT,
207 MUX(0, "clk_uart2_mux", mux_uart2_p, CLK_SET_RATE_PARENT,
211 MUX(0, "clk_uart3_mux", mux_uart3_p, CLK_SET_RATE_PARENT,
215 MUX(0, "clk_uart4_mux", mux_uart4_p, CLK_SET_RATE_PARENT,
219 MUX(0, "dclk_vop_mux", mux_dclk_vop_p, CLK_SET_RATE_PARENT,
[all …]
H A Dclk-px30.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Author: Elaine Zhang<zhangqing@rock-chips.com>
7 #include <linux/clk-provider.h>
12 #include <dt-bindings/clock/px30-cru.h>
209 MUX(0, "clk_pdm_mux", mux_pdm_p, CLK_SET_RATE_PARENT,
213 MUX(0, "clk_i2s0_tx_mux", mux_i2s0_tx_p, CLK_SET_RATE_PARENT,
217 MUX(0, "clk_i2s0_rx_mux", mux_i2s0_rx_p, CLK_SET_RATE_PARENT,
221 MUX(0, "clk_i2s1_mux", mux_i2s1_p, CLK_SET_RATE_PARENT,
225 MUX(0, "clk_i2s2_mux", mux_i2s2_p, CLK_SET_RATE_PARENT,
229 MUX(0, "clk_uart1_mux", mux_uart1_p, CLK_SET_RATE_PARENT,
[all …]
H A Dclk-rk3328.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Author: Elaine <zhangqing@rock-chips.com>
7 #include <linux/clk-provider.h>
12 #include <dt-bindings/clock/rk3328-cru.h>
237 MUX(0, "i2s0_pre", mux_i2s0_p, CLK_SET_RATE_PARENT,
241 MUX(0, "i2s1_pre", mux_i2s1_p, CLK_SET_RATE_PARENT,
245 MUX(0, "i2s2_pre", mux_i2s2_p, CLK_SET_RATE_PARENT,
249 MUX(SCLK_SPDIF, "sclk_spdif", mux_spdif_p, CLK_SET_RATE_PARENT,
253 MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT,
257 MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT,
[all …]
H A Dclk-rk3228.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Author: Xing Zheng <zhengxing@rock-chips.com>
5 * Jeffy Chen <jeffy.chen@rock-chips.com>
8 #include <linux/clk-provider.h>
13 #include <dt-bindings/clock/rk3228-cru.h>
184 MUX(0, "i2s0_pre", mux_i2s0_p, CLK_SET_RATE_PARENT,
188 MUX(0, "i2s1_pre", mux_i2s1_pre_p, CLK_SET_RATE_PARENT,
192 MUX(0, "i2s2_pre", mux_i2s2_p, CLK_SET_RATE_PARENT,
196 MUX(SCLK_SPDIF, "sclk_spdif", mux_sclk_spdif_p, CLK_SET_RATE_PARENT,
200 MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT,
[all …]
H A Dclk-rk3036.c1 // SPDX-License-Identifier: GPL-2.0-or-later
7 * Author: Xing Zheng <zhengxing@rock-chips.com>
10 #include <linux/clk-provider.h>
15 #include <dt-bindings/clock/rk3036-cru.h>
150 MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT,
154 MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT,
158 MUX(SCLK_UART2, "sclk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT,
162 MUX(0, "i2s_pre", mux_i2s_pre_p, CLK_SET_RATE_PARENT,
166 MUX(SCLK_SPDIF, "sclk_spdif", mux_spdif_p, 0,
171 * Clock-Architecture Diagram 1
[all …]
H A Dclk-rk3128.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Author: Elaine <zhangqing@rock-chips.com>
7 #include <linux/clk-provider.h>
12 #include <dt-bindings/clock/rk3128-cru.h>
174 MUX(0, "i2s0_pre", mux_i2s0_p, CLK_SET_RATE_PARENT,
178 MUX(0, "i2s1_pre", mux_i2s1_pre_p, CLK_SET_RATE_PARENT,
182 MUX(SCLK_SPDIF, "sclk_spdif", mux_sclk_spdif_p, CLK_SET_RATE_PARENT,
186 MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT,
190 MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT,
194 MUX(SCLK_UART2, "sclk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT,
[all …]
H A Dclk-rv1108.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Author: Shawn Lin <shawn.lin@rock-chips.com>
5 * Andy Yan <andy.yan@rock-chips.com>
8 #include <linux/clk-provider.h>
13 #include <dt-bindings/clock/rv1108-cru.h>
168 MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT,
172 MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT,
176 MUX(SCLK_UART2, "sclk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT,
180 MUX(0, "i2s0_pre", mux_i2s0_pre_p, CLK_SET_RATE_PARENT,
184 MUX(0, "i2s1_pre", mux_i2s1_p, CLK_SET_RATE_PARENT,
[all …]
H A Dclk-rk3368.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 #include <linux/clk-provider.h>
11 #include <dt-bindings/clock/rk3368-cru.h>
247 MUX(0, "i2s_8ch_pre", mux_i2s_8ch_pre_p, CLK_SET_RATE_PARENT,
251 MUX(0, "spdif_8ch_pre", mux_spdif_8ch_p, CLK_SET_RATE_PARENT,
255 MUX(0, "i2s_2ch_pre", mux_i2s_2ch_p, CLK_SET_RATE_PARENT,
259 MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT,
263 MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT,
267 MUX(SCLK_UART3, "sclk_uart3", mux_uart3_p, CLK_SET_RATE_PARENT,
271 MUX(SCLK_UART4, "sclk_uart4", mux_uart4_p, CLK_SET_RATE_PARENT,
[all …]
H A Dclk-rk3288.c1 // SPDX-License-Identifier: GPL-2.0-or-later
7 #include <linux/clk-provider.h>
12 #include <dt-bindings/clock/rk3288-cru.h>
251 MUX(0, "i2s_pre", mux_i2s_pre_p, CLK_SET_RATE_PARENT,
255 MUX(0, "spdif_mux", mux_spdif_p, CLK_SET_RATE_PARENT,
259 MUX(0, "spdif_8ch_mux", mux_spdif_8ch_p, CLK_SET_RATE_PARENT,
263 MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT,
267 MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT,
271 MUX(SCLK_UART2, "sclk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT,
275 MUX(SCLK_UART3, "sclk_uart3", mux_uart3_p, CLK_SET_RATE_PARENT,
[all …]
H A Dclk-rk3588.c1 // SPDX-License-Identifier: GPL-2.0
4 * Author: Elaine Zhang <zhangqing@rock-chips.com>
7 #include <linux/clk-provider.h>
12 #include <dt-bindings/clock/rockchip,rk3588-cru.h>
20 * Downstream enables the linked clock via runtime PM whenever the gate is
21 * enabled. This implementation uses separate clock nodes for each of the
22 * linked gate clocks, which leaks parts of the clock tree into DT.
25 * ignores the information. Once the clock framework is ready to handle it, the
194 HIWORD_UPDATE(_divdsu - 1, RK3588_CLK_DSU_DF_DIV_MASK, \
201 .val = HIWORD_UPDATE(_aclkm - 1, RK3588_ACLKM_DSU_DIV_MASK, \
[all …]
H A Dclk-rk3399.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Author: Xing Zheng <zhengxing@rock-chips.com>
7 #include <linux/clk-provider.h>
15 #include <dt-bindings/clock/rk3399-cru.h>
246 MUX(0, "clk_spdif_mux", mux_spdif_p, CLK_SET_RATE_PARENT,
250 MUX(0, "clk_i2s0_mux", mux_i2s0_p, CLK_SET_RATE_PARENT,
254 MUX(0, "clk_i2s1_mux", mux_i2s1_p, CLK_SET_RATE_PARENT,
258 MUX(0, "clk_i2s2_mux", mux_i2s2_p, CLK_SET_RATE_PARENT,
262 MUX(SCLK_UART0, "clk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT,
266 MUX(SCLK_UART1, "clk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT,
[all …]
/linux/drivers/clk/mediatek/
H A Dclk-mtk.c1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <linux/clk-provider.h>
19 #include "clk-mtk.h"
20 #include "clk-gate.h"
21 #include "clk-mux.h"
44 clk_data->num = clk_num; in mtk_init_clk_data()
47 clk_data->hws[i] = ERR_PTR(-ENOENT); in mtk_init_clk_data()
93 return -ENOMEM; in mtk_clk_register_fixed_clks()
98 if (!IS_ERR_OR_NULL(clk_data->hws[rc->id])) { in mtk_clk_register_fixed_clks()
99 pr_warn("Trying to register duplicate clock ID: %d\n", rc->id); in mtk_clk_register_fixed_clks()
[all …]
/linux/drivers/clk/
H A Dclk-stm32h7.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk-provider.h>
18 #include <dt-bindings/clock/stm32h7-clks.h>
20 /* Reset Clock Control Registers */
55 /* System clock parent */
66 "hsi_ck", "csi_ck", "hse_ck", "no clock" };
78 /* Kernel clock parent */
136 /* RTC clock parent */
139 /* Micro-controller output clock parent */
146 /* LCD clock */
[all …]

123