Lines Matching +full:composite +full:- +full:mux +full:- +full:clock
1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Author: Xing Zheng <zhengxing@rock-chips.com>
5 * Jeffy Chen <jeffy.chen@rock-chips.com>
8 #include <linux/clk-provider.h>
13 #include <dt-bindings/clock/rk3228-cru.h>
184 MUX(0, "i2s0_pre", mux_i2s0_p, CLK_SET_RATE_PARENT,
188 MUX(0, "i2s1_pre", mux_i2s1_pre_p, CLK_SET_RATE_PARENT,
192 MUX(0, "i2s2_pre", mux_i2s2_p, CLK_SET_RATE_PARENT,
196 MUX(SCLK_SPDIF, "sclk_spdif", mux_sclk_spdif_p, CLK_SET_RATE_PARENT,
200 MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT,
204 MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT,
208 MUX(SCLK_UART2, "sclk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT,
213 * Clock-Architecture Diagram 1
226 COMPOSITE(0, "ddrphy4x", mux_ddrphy_p, CLK_IGNORE_UNUSED,
249 MUX(SCLK_HDMI_PHY, "hdmiphy", mux_hdmiphy_p, CLK_SET_RATE_PARENT,
251 MUX(0, "usb480m_phy", mux_usb480m_phy_p, CLK_SET_RATE_PARENT,
253 MUX(0, "usb480m", mux_usb480m_p, CLK_SET_RATE_PARENT,
281 COMPOSITE(ACLK_VPU_PRE, "aclk_vpu_pre", mux_pll_src_4plls_p, 0,
287 COMPOSITE(ACLK_RKVDEC_PRE, "aclk_rkvdec_pre", mux_pll_src_4plls_p, 0,
293 COMPOSITE(SCLK_VDEC_CABAC, "sclk_vdec_cabac", mux_pll_src_4plls_p, 0,
297 COMPOSITE(SCLK_VDEC_CORE, "sclk_vdec_core", mux_pll_src_4plls_p, 0,
302 COMPOSITE(ACLK_IEP_PRE, "aclk_iep_pre", mux_pll_src_4plls_p, 0,
308 COMPOSITE(ACLK_HDCP_PRE, "aclk_hdcp_pre", mux_pll_src_4plls_p, 0,
312 MUX(0, "sclk_rga_src", mux_pll_src_4plls_p, 0,
317 COMPOSITE(SCLK_RGA, "sclk_rga", mux_sclk_rga_p, 0,
321 COMPOSITE(ACLK_VOP_PRE, "aclk_vop_pre", mux_pll_src_4plls_p, 0,
325 COMPOSITE(SCLK_HDCP, "sclk_hdcp", mux_pll_src_3plls_p, 0,
332 COMPOSITE(SCLK_HDMI_CEC, "sclk_hdmi_cec", mux_sclk_hdmi_cec_p, 0,
367 COMPOSITE(SCLK_CRYPTO, "sclk_crypto", mux_pll_src_2plls_p, 0,
371 COMPOSITE(SCLK_TSP, "sclk_tsp", mux_pll_src_2plls_p, 0,
378 COMPOSITE(SCLK_WIFI, "sclk_wifi", mux_pll_src_cpll_gpll_usb480m_p, 0,
382 COMPOSITE(SCLK_SDMMC, "sclk_sdmmc", mux_mmc_src_p, 0,
399 * Clock-Architecture Diagram 2
406 MUX(0, "sclk_vop_src", mux_sclk_vop_src_p, 0,
412 MUX(DCLK_VOP, "dclk_vop", mux_dclk_vop_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
417 COMPOSITE(0, "i2s0_src", mux_pll_src_2plls_p, 0,
427 COMPOSITE(0, "i2s1_src", mux_pll_src_2plls_p, 0,
440 COMPOSITE(0, "i2s2_src", mux_pll_src_2plls_p, 0,
450 COMPOSITE(0, "sclk_spdif_src", mux_pll_src_2plls_p, 0,
470 COMPOSITE(0, "aclk_gpu_pre", mux_pll_src_4plls_p, 0,
474 COMPOSITE(SCLK_SPI0, "sclk_spi0", mux_pll_src_2plls_p, 0,
479 COMPOSITE(0, "uart0_src", mux_pll_src_cpll_gpll_usb480m_p, 0,
482 COMPOSITE(0, "uart1_src", mux_pll_src_cpll_gpll_usb480m_p, 0,
485 COMPOSITE(0, "uart2_src", mux_pll_src_cpll_gpll_usb480m_p,
501 COMPOSITE(SCLK_NANDC, "sclk_nandc", mux_pll_src_2plls_p, 0,
505 COMPOSITE(SCLK_MAC_SRC, "sclk_gmac_src", mux_pll_src_2plls_p, 0,
508 MUX(SCLK_MAC_EXTCLK, "sclk_mac_extclk", mux_sclk_mac_extclk_p, 0,
510 MUX(SCLK_MAC, "sclk_gmac_pre", mux_sclk_gmac_pre_p, 0,
520 COMPOSITE(SCLK_MAC_PHY, "sclk_macphy", mux_sclk_macphy_p, 0,
523 COMPOSITE(SCLK_MAC_OUT, "sclk_gmac_out", mux_pll_src_2plls_p, 0,
528 * Clock-Architecture Diagram 3
724 CLK_OF_DECLARE(rk3228_cru, "rockchip,rk3228-cru", rk3228_clk_init);