Lines Matching +full:composite +full:- +full:mux +full:- +full:clock
1 // SPDX-License-Identifier: GPL-2.0-or-later
7 * Author: Xing Zheng <zhengxing@rock-chips.com>
10 #include <linux/clk-provider.h>
15 #include <dt-bindings/clock/rk3036-cru.h>
150 MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT,
154 MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT,
158 MUX(SCLK_UART2, "sclk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT,
162 MUX(0, "i2s_pre", mux_i2s_pre_p, CLK_SET_RATE_PARENT,
166 MUX(SCLK_SPDIF, "sclk_spdif", mux_spdif_p, 0,
171 * Clock-Architecture Diagram 1
180 * Clock-Architecture Diagram 2
211 COMPOSITE(0, "aclk_peri_src", mux_pll_src_3plls_p, 0,
239 MUX(0, "uart_pll_clk", mux_pll_src_apll_dpll_gpll_usb480m_p, 0,
263 COMPOSITE(ACLK_VCODEC, "aclk_vcodec", mux_pll_src_3plls_p, 0,
269 COMPOSITE(0, "aclk_hvec", mux_pll_src_3plls_p, 0,
273 COMPOSITE(0, "aclk_disp1_pre", mux_pll_src_3plls_p, 0,
276 COMPOSITE(0, "hclk_disp_pre", mux_pll_src_3plls_p, 0,
279 COMPOSITE(SCLK_LCDC, "dclk_lcdc", mux_pll_src_3plls_p, 0,
295 COMPOSITE(SCLK_EMMC, "sclk_emmc", mux_mmc_src_p, 0,
308 COMPOSITE(0, "i2s_src", mux_pll_src_3plls_p, 0,
321 COMPOSITE(0, "spdif_src", mux_pll_src_3plls_p, 0,
332 COMPOSITE(SCLK_GPU, "sclk_gpu", mux_pll_src_3plls_p, 0,
336 COMPOSITE(SCLK_SPI, "sclk_spi", mux_pll_src_3plls_p, 0,
340 COMPOSITE(SCLK_NANDC, "sclk_nandc", mux_pll_src_3plls_p, 0,
344 COMPOSITE(SCLK_SFC, "sclk_sfc", mux_pll_src_dmyapll_dpll_gpll_xin24_p, 0,
350 MUX(SCLK_MACREF, "mac_clk_ref", mux_mac_p, CLK_SET_RATE_PARENT,
358 MUX(SCLK_HDMI, "dclk_hdmi", mux_dclk_p, 0,
362 * Clock-Architecture Diagram 3
467 pr_warn("%s: could not register clock usb480m: %ld\n", in rk3036_clk_init()
490 CLK_OF_DECLARE(rk3036_cru, "rockchip,rk3036-cru", rk3036_clk_init);