Lines Matching +full:composite +full:- +full:mux +full:- +full:clock
1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Author: Elaine <zhangqing@rock-chips.com>
7 #include <linux/clk-provider.h>
12 #include <dt-bindings/clock/rk3128-cru.h>
174 MUX(0, "i2s0_pre", mux_i2s0_p, CLK_SET_RATE_PARENT,
178 MUX(0, "i2s1_pre", mux_i2s1_pre_p, CLK_SET_RATE_PARENT,
182 MUX(SCLK_SPDIF, "sclk_spdif", mux_sclk_spdif_p, CLK_SET_RATE_PARENT,
186 MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT,
190 MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT,
194 MUX(SCLK_UART2, "sclk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT,
199 * Clock-Architecture Diagram 1
231 MUX(SCLK_USB480M, "usb480m", mux_usb480m_p, CLK_SET_RATE_PARENT,
235 COMPOSITE(0, "aclk_cpu_src", mux_aclk_cpu_src_p, 0,
251 COMPOSITE(ACLK_VEPU, "aclk_vepu", mux_pll_src_5plls_p, 0,
256 COMPOSITE(ACLK_VDPU, "aclk_vdpu", mux_pll_src_5plls_p, 0,
262 COMPOSITE(SCLK_HEVC_CORE, "sclk_hevc_core", mux_pll_src_5plls_p, 0,
267 COMPOSITE(ACLK_VIO0, "aclk_vio0", mux_pll_src_5plls_p, 0,
270 COMPOSITE(ACLK_VIO1, "aclk_vio1", mux_pll_src_5plls_p, 0,
273 COMPOSITE(HCLK_VIO, "hclk_vio", mux_pll_src_4plls_p, 0,
278 COMPOSITE(0, "clk_peri_src", mux_clk_peri_src_p, 0,
313 COMPOSITE(SCLK_SDMMC, "sclk_sdmmc", mux_mmc_src_p, 0,
317 COMPOSITE(SCLK_SDIO, "sclk_sdio", mux_mmc_src_p, 0,
321 COMPOSITE(SCLK_EMMC, "sclk_emmc", mux_mmc_src_p, 0,
329 * Clock-Architecture Diagram 2
331 COMPOSITE(DCLK_VOP, "dclk_vop", mux_sclk_vop_src_p, 0,
334 COMPOSITE(SCLK_VOP, "sclk_vop", mux_sclk_vop_src_p, 0,
337 COMPOSITE(DCLK_EBC, "dclk_ebc", mux_pll_src_3plls_p, 0,
346 MUX(SCLK_CIF_OUT_SRC, "sclk_cif_out_src", mux_clk_cif_out_src_p, 0,
351 COMPOSITE(0, "i2s0_src", mux_pll_src_3plls_p, 0,
361 COMPOSITE(0, "i2s1_src", mux_pll_src_3plls_p, 0,
374 COMPOSITE(0, "sclk_spdif_src", mux_pll_src_3plls_p, 0,
394 COMPOSITE(ACLK_GPU, "aclk_gpu", mux_pll_src_5plls_p, 0,
398 COMPOSITE(SCLK_SPI0, "sclk_spi0", mux_pll_src_3plls_p, 0,
403 COMPOSITE(0, "uart0_src", mux_pll_src_4plls_p, 0,
406 MUX(0, "uart12_src", mux_pll_src_4plls_p, 0,
427 COMPOSITE(SCLK_MAC_SRC, "sclk_gmac_src", mux_pll_src_3plls_p, 0,
430 MUX(SCLK_MAC, "sclk_gmac", mux_sclk_gmac_p, 0,
441 COMPOSITE(SCLK_TSP, "sclk_tsp", mux_pll_src_3plls_p, 0,
445 COMPOSITE(SCLK_NANDC, "sclk_nandc", mux_pll_src_3plls_p, 0,
454 * Clock-Architecture Diagram 3
552 COMPOSITE(SCLK_SFC, "sclk_sfc", mux_sclk_sfc_src_p, 0,
585 return ERR_PTR(-ENOMEM); in rk3128_common_clk_init()
592 return ERR_PTR(-ENOMEM); in rk3128_common_clk_init()
634 CLK_OF_DECLARE(rk3126_cru, "rockchip,rk3126-cru", rk3126_clk_init);
656 CLK_OF_DECLARE(rk3128_cru, "rockchip,rk3128-cru", rk3128_clk_init);