Home
last modified time | relevance | path

Searched +full:clk +full:- +full:phase +full:- (Results 1 – 25 of 168) sorted by relevance

1234567

/linux/drivers/clk/sunxi/
H A Dclk-mod0.c1 // SPDX-License-Identifier: GPL-2.0-or-later
8 #include <linux/clk.h>
9 #include <linux/clk-provider.h>
15 #include "clk-factors.h"
18 * sun4i_a10_get_mod0_factors() - calculates m, n factors for MOD0-style clocks
29 if (req->rate > req->parent_rate) in sun4i_a10_get_mod0_factors()
30 req->rate = req->parent_rate; in sun4i_a10_get_mod0_factors()
32 div = DIV_ROUND_UP(req->parent_rate, req->rate); in sun4i_a10_get_mod0_factors()
45 req->rate = (req->parent_rate >> calcp) / calcm; in sun4i_a10_get_mod0_factors()
46 req->m = calcm - 1; in sun4i_a10_get_mod0_factors()
[all …]
/linux/include/trace/events/
H A Dclk.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
6 #define TRACE_SYSTEM clk
15 DECLARE_EVENT_CLASS(clk,
22 __string( name, core->name )
32 DEFINE_EVENT(clk, clk_enable,
39 DEFINE_EVENT(clk, clk_enable_complet
[all...]
/linux/drivers/mmc/host/
H A Dmmci_stm32_sdmmc.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) STMicroelectronics 2018 - All Rights Reserved
8 #include <linux/dma-mapping.h>
71 int phase, bool sampler __maybe_unused);
84 struct sdmmc_idma *idma = host->dma_priv; in sdmmc_idma_validate_data()
85 struct device *dev = mmc_dev(host->mmc); in sdmmc_idma_validate_data()
93 idma->use_bounce_buffer = false; in sdmmc_idma_validate_data()
94 for_each_sg(data->sg, sg, data->sg_len - 1, i) { in sdmmc_idma_validate_data()
95 if (!IS_ALIGNED(sg->offset, sizeof(u32)) || in sdmmc_idma_validate_data()
96 !IS_ALIGNED(sg->length, in sdmmc_idma_validate_data()
[all …]
H A Ddw_mmc-rockchip.c1 // SPDX-License-Identifier: GPL-2.0-or-later
8 #include <linux/clk.h>
12 #include <linux/mmc/slot-gpio.h>
17 #include "dw_mmc-pltfm.h"
32 struct clk *drv_clk;
33 struct clk *sample_clk;
40 * Each fine delay is between 44ps-77ps. Assume each fine delay is 60ps to
45 unsigned long rate = clk_get_rate(host->ciu_clk) / RK3288_CLKGEN_DIV; in rockchip_mmc_get_internal_phase()
50 /* Constant signal, no measurable phase shift */ in rockchip_mmc_get_internal_phase()
77 struct dw_mci_rockchip_priv_data *priv = host->priv; in rockchip_mmc_get_phase()
[all …]
H A Dsdhci-of-aspeed.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 #include <linux/clk.h>
18 #include "sdhci-pltfm.h"
40 struct clk *clk; member
85 * -----|-------------|----------|------------
108 writel(cap_val, sdc->regs + mirror_reg_offset); in aspeed_sdc_set_slot_capability()
118 spin_lock(&sdc->lock); in aspeed_sdc_configure_8bit_mode()
119 info = readl(sdc->regs + ASPEED_SDC_INFO); in aspeed_sdc_configure_8bit_mode()
121 info |= sdhci->width_mask; in aspeed_sdc_configure_8bit_mode()
123 info &= ~sdhci->width_mask; in aspeed_sdc_configure_8bit_mode()
[all …]
/linux/drivers/clk/hisilicon/
H A Dclk-hisi-phase.c1 // SPDX-License-Identifier: GPL-2.0
5 * Simple HiSilicon phase clock implementation.
14 #include "clk.h"
30 static int hisi_phase_regval_to_degrees(struct clk_hisi_phase *phase, in hisi_phase_regval_to_degrees() argument
35 for (i = 0; i < phase->phase_num; i++) in hisi_phase_regval_to_degrees()
36 if (phase->phase_regvals[i] == regval) in hisi_phase_regval_to_degrees()
37 return phase->phase_degrees[i]; in hisi_phase_regval_to_degrees()
39 return -EINVAL; in hisi_phase_regval_to_degrees()
44 struct clk_hisi_phase *phase = to_clk_hisi_phase(hw); in hisi_clk_get_phase() local
47 regval = readl(phase->reg); in hisi_clk_get_phase()
[all …]
H A DMakefile1 # SPDX-License-Identifier: GPL-2.0
6 obj-y += clk.o clkgate-separated.o clkdivider-hi6220.o clk-hisi-phase.o
8 obj-$(CONFIG_ARCH_HI3xxx) += clk-hi3620.o
9 obj-$(CONFIG_ARCH_HIP04) += clk-hip04.o
10 obj-$(CONFIG_ARCH_HIX5HD2) += clk-hix5hd2.o
11 obj-$(CONFIG_COMMON_CLK_HI3516CV300) += crg-hi3516cv300.o
12 obj-$(CONFIG_COMMON_CLK_HI3519) += clk-hi3519.o
13 obj-$(CONFIG_COMMON_CLK_HI3559A) += clk-hi3559a.o
14 obj-$(CONFIG_COMMON_CLK_HI3660) += clk-hi3660.o
15 obj-$(CONFIG_COMMON_CLK_HI3670) += clk-hi3670.o
[all …]
/linux/drivers/watchdog/
H A Drealtek_otto_wdt.c1 // SPDX-License-Identifier: GPL-2.0-only
10 * - Base prescale of (2 << 25), providing tick duration T_0: 168ms @ 200MHz
11 * - PRESCALE: logarithmic prescaler adding a factor of {1, 2, 4, 8}
12 * - Phase 1: Times out after (PHASE1 + 1) × PRESCALE × T_0
13 * Generates an interrupt, WDT cannot be stopped after phase 1
14 * - Phase 2: starts after phase 1, times out after (PHASE2 + 1) × PRESCALE × T_0
20 #include <linux/clk.h>
54 * One higher than the max values contained in PHASE{1,2}, since a value of 0
79 v = ioread32(ctrl->base + OTTO_WDT_REG_CTRL); in otto_wdt_start()
81 iowrite32(v, ctrl->base + OTTO_WDT_REG_CTRL); in otto_wdt_start()
[all …]
/linux/drivers/clk/
H A Dclk.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2010-2011 Canonical Ltd <jeremy.kerr@canonical.com>
4 * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org>
6 * Standard functionality for the common clock API. See Documentation/driver-api/clk.rst
9 #include <linux/clk/clk-conf.h>
11 #include <linux/clk.h>
12 #include <linux/clk-provider.h>
28 #include "clk.h"
92 int phase; member
107 #include <trace/events/clk.h>
[all …]
/linux/drivers/counter/
H A Drz-mtu3-cnt.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk.h>
10 #include <linux/mfd/rz-mtu3.h>
31 #define RZ_MTU3_TMDR1_PH_CNT_MODE_1 (4) /* Phase counting mode 1 */
32 #define RZ_MTU3_TMDR1_PH_CNT_MODE_2 (5) /* Phase counting mode 2 */
33 #define RZ_MTU3_TMDR1_PH_CNT_MODE_3 (6) /* Phase counting mode 3 */
34 #define RZ_MTU3_TMDR1_PH_CNT_MODE_4 (7) /* Phase counting mode 4 */
35 #define RZ_MTU3_TMDR1_PH_CNT_MODE_5 (9) /* Phase counting mode 5 */
40 * 0: 16-bit, 1: 32-bit
45 * PHCKSEL: External Input Phase Clock Select
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dccg/dcn20/
H A Ddcn20_dccg.c36 (dccg_dcn->regs->reg)
40 dccg_dcn->dccg_shift->field_name, dccg_dcn->dccg_mask->field_name
43 dccg_dcn->base.ctx
45 dccg->ctx->logger
51 if (dccg->ref_dppclk && req_dppclk) { in dccg2_update_dpp_dto()
52 int ref_dppclk = dccg->ref_dppclk; in dccg2_update_dpp_dto()
53 int modulo, phase; in dccg2_update_dpp_dto() local
55 // phase / modulo = dpp pipe clk / dpp global clk in dccg2_update_dpp_dto()
57 phase = ((modulo * req_dppclk) + ref_dppclk - 1) / ref_dppclk; in dccg2_update_dpp_dto()
59 if (phase > 0xff) { in dccg2_update_dpp_dto()
[all …]
/linux/drivers/clk/sunxi-ng/
H A Dccu_phase.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
7 #include <linux/clk-provider.h>
15 struct ccu_phase *phase = hw_to_ccu_phase(hw); in ccu_phase_get_phase() local
22 reg = readl(phase->common.base + phase->common.reg); in ccu_phase_get_phase()
23 delay = (reg >> phase->shift); in ccu_phase_get_phase()
24 delay &= (1 << phase->width) - 1; in ccu_phase_get_phase()
32 return -EINVAL; in ccu_phase_get_phase()
37 return -EINVAL; in ccu_phase_get_phase()
42 return -EINVAL; in ccu_phase_get_phase()
[all …]
/linux/drivers/clk/tegra/
H A Dclk-device.c1 // SPDX-License-Identifier: GPL-2.0-only
3 #include <linux/clk.h>
4 #include <linux/clk-provider.h>
15 #include "clk.h"
33 struct device *dev = clk_dev->dev; in tegra_clock_set_pd_state()
38 if (opp == ERR_PTR(-ERANGE)) { in tegra_clock_set_pd_state()
44 * not error out clk initialization. A typical example is in tegra_clock_set_pd_state()
71 mutex_lock(&clk_dev->lock); in tegra_clock_change_notify()
74 if (cnd->new_rate > cnd->old_rate) in tegra_clock_change_notify()
75 err = tegra_clock_set_pd_state(clk_dev, cnd->new_rate); in tegra_clock_change_notify()
[all …]
/linux/Documentation/devicetree/bindings/watchdog/
H A Dstarfive,jh7100-wdt.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/watchdog/starfive,jh7100-wdt.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Xingyu Wu <xingyu.wu@starfivetech.com>
11 - Samin Guo <samin.guo@starfivetech.com>
15 has only one timeout phase and reboots. And JH7110 watchdog has two
16 timeout phases. At the first phase, the signal of watchdog interrupt
25 - enum:
26 - starfive,jh7100-wdt
[all …]
/linux/drivers/iio/dac/
H A Dadi-axi-dac.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * Copyright 2016-2024 Analog Devices Inc.
8 #include <linux/adi-axi-common.h>
12 #include <linux/clk.h>
28 #include <linux/iio/buffer-dmaengine.h>
32 #include "ad3552r-hs.h"
127 guard(mutex)(&st->lock); in axi_dac_enable()
128 ret = regmap_set_bits(st->regmap, AXI_DAC_RSTN_REG, in axi_dac_enable()
137 ret = regmap_read_poll_timeout(st->regmap, AXI_DAC_DRP_STATUS_REG, in axi_dac_enable()
144 return regmap_set_bits(st->regmap, AXI_DAC_RSTN_REG, in axi_dac_enable()
[all …]
/linux/Documentation/devicetree/bindings/iio/frequency/
H A Dadi,adf4350.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Michael Hennerich <michael.hennerich@analog.com>
15 - adi,adf4350
16 - adi,adf4351
21 spi-max-frequency:
28 clock-names:
31 '#clock-cells':
34 clock-output-names:
[all …]
/linux/drivers/clk/rockchip/
H A DMakefile1 # SPDX-License-Identifier: GPL-2.0
6 obj-$(CONFIG_COMMON_CLK_ROCKCHIP) += clk-rockchip.o
8 clk-rockchip-y += clk.o
9 clk-rockchip-y += clk-pll.o
10 clk-rockchip-y += clk-cpu.o
11 clk-rockchip-y += clk-gate-grf.o
12 clk-rockchip-y += clk-half-divider.o
13 clk-rockchip-y += clk-inverter.o
14 clk-rockchip-y += clk-mmc-phase.o
15 clk-rockchip-y += clk-muxgrf.o
[all …]
H A Dclk-inverter.c1 // SPDX-License-Identifier: GPL-2.0-or-later
7 #include <linux/clk-provider.h>
11 #include "clk.h"
30 val = readl(inv_clock->reg) >> inv_clock->shift; in rockchip_inv_get_phase()
43 pr_err("%s: unsupported phase %d for %s\n", in rockchip_inv_set_phase()
45 return -EINVAL; in rockchip_inv_set_phase()
48 if (inv_clock->flags & ROCKCHIP_INVERTER_HIWORD_MASK) { in rockchip_inv_set_phase()
49 writel(HIWORD_UPDATE(val, INVERTER_MASK, inv_clock->shift), in rockchip_inv_set_phase()
50 inv_clock->reg); in rockchip_inv_set_phase()
55 spin_lock_irqsave(inv_clock->lock, flags); in rockchip_inv_set_phase()
[all …]
/linux/drivers/clk/meson/
H A DMakefile1 # SPDX-License-Identifier: GPL-2.0-only
4 obj-$(CONFIG_COMMON_CLK_MESON_CLKC_UTILS) += meson-clkc-utils.o
5 obj-$(CONFIG_COMMON_CLK_MESON_AO_CLKC) += meson-aoclk.o
6 obj-$(CONFIG_COMMON_CLK_MESON_CPU_DYNDIV) += clk-cpu-dyndiv.o
7 obj-$(CONFIG_COMMON_CLK_MESON_DUALDIV) += clk-dualdiv.o
8 obj-$(CONFIG_COMMON_CLK_MESON_MPLL) += clk-mpll.o
9 obj-$(CONFIG_COMMON_CLK_MESON_PHASE) += clk-phase.o
10 obj-$(CONFIG_COMMON_CLK_MESON_PLL) += clk-pll.o
11 obj-$(CONFIG_COMMON_CLK_MESON_REGMAP) += clk-regmap.o
12 obj-$(CONFIG_COMMON_CLK_MESON_SCLK_DIV) += sclk-div.o
[all …]
/linux/arch/arm/boot/dts/aspeed/
H A Daspeed-ast2600-evb.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
4 /dts-v1/;
6 #include "aspeed-g6.dtsi"
7 #include <dt-bindings/gpio/aspeed-gpio.h>
11 compatible = "aspeed,ast2600-evb", "aspeed,ast2600";
26 reserved-memory {
27 #address-cells = <1>;
28 #size-cells = <1>;
34 compatible = "shared-dma-pool";
41 compatible = "shared-dma-pool";
[all …]
/linux/Documentation/devicetree/bindings/memory-controllers/
H A Dst,stm32-fmc2-ebi-props.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/st,stm32-fmc2-ebi-props.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Christophe Kerello <christophe.kerello@foss.st.com>
11 - Marek Vasut <marex@denx.de>
14 st,fmc2-ebi-cs-transaction-type:
33 st,fmc2-ebi-cs-cclk-enable:
40 st,fmc2-ebi-cs-mux-enable:
46 st,fmc2-ebi-cs-buswidth:
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dccg/dcn31/
H A Ddcn31_dccg.c35 (dccg_dcn->regs->reg)
39 dccg_dcn->dccg_shift->field_name, dccg_dcn->dccg_mask->field_name
42 dccg_dcn->base.ctx
44 dccg->ctx->logger
50 if (dccg->dpp_clock_gated[dpp_inst]) { in dccg31_update_dpp_dto()
58 if (dccg->ref_dppclk && req_dppclk) { in dccg31_update_dpp_dto()
59 int ref_dppclk = dccg->ref_dppclk; in dccg31_update_dpp_dto()
60 int modulo, phase; in dccg31_update_dpp_dto() local
62 // phase / modulo = dpp pipe clk / dpp global clk in dccg31_update_dpp_dto()
64 phase = ((modulo * req_dppclk) + ref_dppclk - 1) / ref_dppclk; in dccg31_update_dpp_dto()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dccg/dcn35/
H A Ddcn35_dccg.c1 /* SPDX-License-Identifier: MIT */
34 (dccg_dcn->regs->reg)
38 dccg_dcn->dccg_shift->field_name, dccg_dcn->dccg_mask->field_name
41 dccg_dcn->base.ctx
44 dccg->ctx->logger
56 SYMCLK_BE_PHYCLK = 0, // Select phy clk when sym_clk_enable = 1
141 if (!dccg->ctx->dc->debug.root_clock_optimization.bits.dsc && allow_rcg) in dccg35_set_dsc_clk_rcg()
174 if (!dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se && enable) in dccg35_set_symclk32_se_rcg()
213 if (!dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_le && enable) in dccg35_set_symclk32_le_rcg()
240 if (!dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk && enable) in dccg35_set_physymclk_rcg()
[all …]
/linux/drivers/clk/qcom/
H A Dclk-alpha-pll.h1 /* SPDX-License-Identifier: GPL-2.0 */
11 #include <linux/clk-provider.h>
12 #include "clk-regmap.h"
82 * struct clk_alpha_pll - phase locked loop (PLL)
108 * struct clk_alpha_pll_postdiv - phase locked loop (PLL) post-divider
111 * @width: width of post-divider
112 * @post_div_shift: shift to differentiate between odd & even post-divider
113 * @post_div_table: table with PLL odd and even post-divider settings
114 * @num_post_div: Number of PLL post-divider settings
/linux/drivers/gpu/drm/sun4i/
H A Dsun4i_tcon.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
6 * Boris Brezillon <boris.brezillon@free-electrons.com>
7 * Maxime Ripard <maxime.ripard@free-electrons.com>
27 #define SUN4I_TCON_GINT0_VBLANK_ENABLE(pipe) BIT(31 - (pipe))
30 #define SUN4I_TCON_GINT0_VBLANK_INT(pipe) BIT(15 - (pipe))
67 #define SUN4I_TCON0_BASIC0_X(width) ((((width) - 1) & 0xfff) << 16)
68 #define SUN4I_TCON0_BASIC0_Y(height) (((height) - 1) & 0xfff)
71 #define SUN4I_TCON0_BASIC1_H_TOTAL(total) ((((total) - 1) & 0x1fff) << 16)
72 #define SUN4I_TCON0_BASIC1_H_BACKPORCH(bp) (((bp) - 1) & 0xfff)
76 #define SUN4I_TCON0_BASIC2_V_BACKPORCH(bp) (((bp) - 1) & 0xfff)
[all …]

1234567