Lines Matching +full:clk +full:- +full:phase +full:-
1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk.h>
10 #include <linux/mfd/rz-mtu3.h>
31 #define RZ_MTU3_TMDR1_PH_CNT_MODE_1 (4) /* Phase counting mode 1 */
32 #define RZ_MTU3_TMDR1_PH_CNT_MODE_2 (5) /* Phase counting mode 2 */
33 #define RZ_MTU3_TMDR1_PH_CNT_MODE_3 (6) /* Phase counting mode 3 */
34 #define RZ_MTU3_TMDR1_PH_CNT_MODE_4 (7) /* Phase counting mode 4 */
35 #define RZ_MTU3_TMDR1_PH_CNT_MODE_5 (9) /* Phase counting mode 5 */
40 * 0: 16-bit, 1: 32-bit
45 * PHCKSEL: External Input Phase Clock Select
66 * struct rz_mtu3_cnt - MTU3 counter private data
68 * @clk: MTU3 module clock
72 * @mtu_16bit_max: Cache for 16-bit counters
73 * @mtu_32bit_max: Cache for 32-bit counters
76 struct clk *clk; member
102 return &priv->ch[ch_id]; in rz_mtu3_get_ch()
110 pm_runtime_get_sync(priv->ch->dev); in rz_mtu3_is_counter_invalid()
111 tmdr = rz_mtu3_shared_reg_read(priv->ch, RZ_MTU3_TMDR3); in rz_mtu3_is_counter_invalid()
112 pm_runtime_put(priv->ch->dev); in rz_mtu3_is_counter_invalid()
128 mutex_lock(&priv->lock); in rz_mtu3_lock_if_counter_is_valid()
130 if (ch->is_busy && !priv->count_is_enabled[id]) { in rz_mtu3_lock_if_counter_is_valid()
131 mutex_unlock(&priv->lock); in rz_mtu3_lock_if_counter_is_valid()
132 return -EINVAL; in rz_mtu3_lock_if_counter_is_valid()
136 mutex_unlock(&priv->lock); in rz_mtu3_lock_if_counter_is_valid()
137 return -EBUSY; in rz_mtu3_lock_if_counter_is_valid()
147 mutex_lock(&priv->lock); in rz_mtu3_lock_if_count_is_enabled()
149 if (ch->is_busy && !priv->count_is_enabled[id]) { in rz_mtu3_lock_if_count_is_enabled()
150 mutex_unlock(&priv->lock); in rz_mtu3_lock_if_count_is_enabled()
151 return -EINVAL; in rz_mtu3_lock_if_count_is_enabled()
160 struct rz_mtu3_channel *const ch = rz_mtu3_get_ch(counter, count->id); in rz_mtu3_count_read()
164 ret = rz_mtu3_lock_if_counter_is_valid(counter, ch, priv, count->id); in rz_mtu3_count_read()
168 pm_runtime_get_sync(ch->dev); in rz_mtu3_count_read()
169 if (count->id == RZ_MTU3_32_BIT_CH) in rz_mtu3_count_read()
173 pm_runtime_put(ch->dev); in rz_mtu3_count_read()
174 mutex_unlock(&priv->lock); in rz_mtu3_count_read()
182 struct rz_mtu3_channel *const ch = rz_mtu3_get_ch(counter, count->id); in rz_mtu3_count_write()
186 ret = rz_mtu3_lock_if_counter_is_valid(counter, ch, priv, count->id); in rz_mtu3_count_write()
190 pm_runtime_get_sync(ch->dev); in rz_mtu3_count_write()
191 if (count->id == RZ_MTU3_32_BIT_CH) in rz_mtu3_count_write()
195 pm_runtime_put(ch->dev); in rz_mtu3_count_write()
196 mutex_unlock(&priv->lock); in rz_mtu3_count_write()
207 pm_runtime_get_sync(ch->dev); in rz_mtu3_count_function_read_helper()
209 pm_runtime_put(ch->dev); in rz_mtu3_count_function_read_helper()
224 * - need to add RZ_MTU3_TMDR1_PH_CNT_MODE_3 in rz_mtu3_count_function_read_helper()
225 * - need to add RZ_MTU3_TMDR1_PH_CNT_MODE_5 in rz_mtu3_count_function_read_helper()
227 return -EINVAL; in rz_mtu3_count_function_read_helper()
235 struct rz_mtu3_channel *const ch = rz_mtu3_get_ch(counter, count->id); in rz_mtu3_count_function_read()
239 ret = rz_mtu3_lock_if_count_is_enabled(ch, priv, count->id); in rz_mtu3_count_function_read()
244 mutex_unlock(&priv->lock); in rz_mtu3_count_function_read()
253 struct rz_mtu3_channel *const ch = rz_mtu3_get_ch(counter, count->id); in rz_mtu3_count_function_write()
258 ret = rz_mtu3_lock_if_count_is_enabled(ch, priv, count->id); in rz_mtu3_count_function_write()
275 * - need to add RZ_MTU3_TMDR1_PH_CNT_MODE_3 in rz_mtu3_count_function_write()
276 * - need to add RZ_MTU3_TMDR1_PH_CNT_MODE_5 in rz_mtu3_count_function_write()
278 mutex_unlock(&priv->lock); in rz_mtu3_count_function_write()
279 return -EINVAL; in rz_mtu3_count_function_write()
282 pm_runtime_get_sync(ch->dev); in rz_mtu3_count_function_write()
284 pm_runtime_put(ch->dev); in rz_mtu3_count_function_write()
285 mutex_unlock(&priv->lock); in rz_mtu3_count_function_write()
294 struct rz_mtu3_channel *const ch = rz_mtu3_get_ch(counter, count->id); in rz_mtu3_count_direction_read()
299 ret = rz_mtu3_lock_if_count_is_enabled(ch, priv, count->id); in rz_mtu3_count_direction_read()
303 pm_runtime_get_sync(ch->dev); in rz_mtu3_count_direction_read()
305 pm_runtime_put(ch->dev); in rz_mtu3_count_direction_read()
309 mutex_unlock(&priv->lock); in rz_mtu3_count_direction_read()
318 struct rz_mtu3_channel *const ch = rz_mtu3_get_ch(counter, count->id); in rz_mtu3_count_ceiling_read()
320 const size_t ch_id = rz_mtu3_get_hw_ch(count->id); in rz_mtu3_count_ceiling_read()
323 ret = rz_mtu3_lock_if_counter_is_valid(counter, ch, priv, count->id); in rz_mtu3_count_ceiling_read()
327 switch (count->id) { in rz_mtu3_count_ceiling_read()
330 *ceiling = priv->mtu_16bit_max[ch_id]; in rz_mtu3_count_ceiling_read()
333 *ceiling = priv->mtu_32bit_max; in rz_mtu3_count_ceiling_read()
337 mutex_unlock(&priv->lock); in rz_mtu3_count_ceiling_read()
338 return -EINVAL; in rz_mtu3_count_ceiling_read()
341 mutex_unlock(&priv->lock); in rz_mtu3_count_ceiling_read()
349 struct rz_mtu3_channel *const ch = rz_mtu3_get_ch(counter, count->id); in rz_mtu3_count_ceiling_write()
351 const size_t ch_id = rz_mtu3_get_hw_ch(count->id); in rz_mtu3_count_ceiling_write()
354 ret = rz_mtu3_lock_if_counter_is_valid(counter, ch, priv, count->id); in rz_mtu3_count_ceiling_write()
358 switch (count->id) { in rz_mtu3_count_ceiling_write()
362 mutex_unlock(&priv->lock); in rz_mtu3_count_ceiling_write()
363 return -ERANGE; in rz_mtu3_count_ceiling_write()
365 priv->mtu_16bit_max[ch_id] = ceiling; in rz_mtu3_count_ceiling_write()
369 mutex_unlock(&priv->lock); in rz_mtu3_count_ceiling_write()
370 return -ERANGE; in rz_mtu3_count_ceiling_write()
372 priv->mtu_32bit_max = ceiling; in rz_mtu3_count_ceiling_write()
376 mutex_unlock(&priv->lock); in rz_mtu3_count_ceiling_write()
377 return -EINVAL; in rz_mtu3_count_ceiling_write()
380 pm_runtime_get_sync(ch->dev); in rz_mtu3_count_ceiling_write()
381 if (count->id == RZ_MTU3_32_BIT_CH) in rz_mtu3_count_ceiling_write()
387 pm_runtime_put(ch->dev); in rz_mtu3_count_ceiling_write()
388 mutex_unlock(&priv->lock); in rz_mtu3_count_ceiling_write()
398 /* Phase counting mode 1 is used as default in initialization. */ in rz_mtu3_32bit_cnt_setting()
412 /* Phase counting mode 1 is used as default in initialization. */ in rz_mtu3_16bit_cnt_setting()
430 return -EBUSY; in rz_mtu3_initialize_counter()
436 * 32-bit phase counting need MTU1 and MTU2 to create 32-bit in rz_mtu3_initialize_counter()
440 return -EBUSY; in rz_mtu3_initialize_counter()
444 return -EBUSY; in rz_mtu3_initialize_counter()
451 return -EINVAL; in rz_mtu3_initialize_counter()
475 struct rz_mtu3_channel *const ch = rz_mtu3_get_ch(counter, count->id); in rz_mtu3_count_enable_read()
481 ret = rz_mtu3_lock_if_count_is_enabled(ch, priv, count->id); in rz_mtu3_count_enable_read()
485 if (count->id == RZ_MTU3_32_BIT_CH) in rz_mtu3_count_enable_read()
490 mutex_unlock(&priv->lock); in rz_mtu3_count_enable_read()
498 struct rz_mtu3_channel *const ch = rz_mtu3_get_ch(counter, count->id); in rz_mtu3_count_enable_write()
503 mutex_lock(&priv->lock); in rz_mtu3_count_enable_write()
504 pm_runtime_get_sync(ch->dev); in rz_mtu3_count_enable_write()
505 ret = rz_mtu3_initialize_counter(counter, count->id); in rz_mtu3_count_enable_write()
507 priv->count_is_enabled[count->id] = true; in rz_mtu3_count_enable_write()
508 mutex_unlock(&priv->lock); in rz_mtu3_count_enable_write()
510 mutex_lock(&priv->lock); in rz_mtu3_count_enable_write()
511 rz_mtu3_terminate_counter(counter, count->id); in rz_mtu3_count_enable_write()
512 priv->count_is_enabled[count->id] = false; in rz_mtu3_count_enable_write()
513 pm_runtime_put(ch->dev); in rz_mtu3_count_enable_write()
514 mutex_unlock(&priv->lock); in rz_mtu3_count_enable_write()
522 mutex_lock(&priv->lock); in rz_mtu3_lock_if_ch0_is_enabled()
523 if (priv->ch->is_busy && !(priv->count_is_enabled[RZ_MTU3_16_BIT_MTU1_CH] || in rz_mtu3_lock_if_ch0_is_enabled()
524 priv->count_is_enabled[RZ_MTU3_32_BIT_CH])) { in rz_mtu3_lock_if_ch0_is_enabled()
525 mutex_unlock(&priv->lock); in rz_mtu3_lock_if_ch0_is_enabled()
526 return -EINVAL; in rz_mtu3_lock_if_ch0_is_enabled()
543 pm_runtime_get_sync(priv->ch->dev); in rz_mtu3_cascade_counts_enable_get()
544 tmdr = rz_mtu3_shared_reg_read(priv->ch, RZ_MTU3_TMDR3); in rz_mtu3_cascade_counts_enable_get()
545 pm_runtime_put(priv->ch->dev); in rz_mtu3_cascade_counts_enable_get()
547 mutex_unlock(&priv->lock); in rz_mtu3_cascade_counts_enable_get()
562 pm_runtime_get_sync(priv->ch->dev); in rz_mtu3_cascade_counts_enable_set()
563 rz_mtu3_shared_reg_update_bit(priv->ch, RZ_MTU3_TMDR3, in rz_mtu3_cascade_counts_enable_set()
565 pm_runtime_put(priv->ch->dev); in rz_mtu3_cascade_counts_enable_set()
566 mutex_unlock(&priv->lock); in rz_mtu3_cascade_counts_enable_set()
582 pm_runtime_get_sync(priv->ch->dev); in rz_mtu3_ext_input_phase_clock_select_get()
583 tmdr = rz_mtu3_shared_reg_read(priv->ch, RZ_MTU3_TMDR3); in rz_mtu3_ext_input_phase_clock_select_get()
584 pm_runtime_put(priv->ch->dev); in rz_mtu3_ext_input_phase_clock_select_get()
586 mutex_unlock(&priv->lock); in rz_mtu3_ext_input_phase_clock_select_get()
601 pm_runtime_get_sync(priv->ch->dev); in rz_mtu3_ext_input_phase_clock_select_set()
602 rz_mtu3_shared_reg_update_bit(priv->ch, RZ_MTU3_TMDR3, in rz_mtu3_ext_input_phase_clock_select_set()
605 pm_runtime_put(priv->ch->dev); in rz_mtu3_ext_input_phase_clock_select_set()
606 mutex_unlock(&priv->lock); in rz_mtu3_ext_input_phase_clock_select_set()
630 const bool is_signal_ab = (synapse->signal->id == SIGNAL_A_ID) || in rz_mtu3_action_read()
631 (synapse->signal->id == SIGNAL_B_ID); in rz_mtu3_action_read()
632 struct rz_mtu3_channel *const ch = rz_mtu3_get_ch(counter, count->id); in rz_mtu3_action_read()
639 ret = rz_mtu3_lock_if_count_is_enabled(ch, priv, count->id); in rz_mtu3_action_read()
645 mutex_unlock(&priv->lock); in rz_mtu3_action_read()
652 if (count->id != RZ_MTU3_16_BIT_MTU1_CH) { in rz_mtu3_action_read()
653 tmdr = rz_mtu3_shared_reg_read(priv->ch, RZ_MTU3_TMDR3); in rz_mtu3_action_read()
657 mutex_unlock(&priv->lock); in rz_mtu3_action_read()
669 if (synapse->signal->id == SIGNAL_A_ID || in rz_mtu3_action_read()
670 synapse->signal->id == SIGNAL_C_ID) in rz_mtu3_action_read()
678 if (synapse->signal->id == SIGNAL_B_ID || in rz_mtu3_action_read()
679 synapse->signal->id == SIGNAL_D_ID) in rz_mtu3_action_read()
688 mutex_unlock(&priv->lock); in rz_mtu3_action_read()
689 return -EINVAL; in rz_mtu3_action_read()
692 mutex_unlock(&priv->lock); in rz_mtu3_action_read()
787 "MTCLKA-MTCLKB",
788 "MTCLKC-MTCLKD",
806 struct clk *const clk = dev_get_drvdata(dev); in rz_mtu3_cnt_pm_runtime_suspend() local
808 clk_disable_unprepare(clk); in rz_mtu3_cnt_pm_runtime_suspend()
815 struct clk *const clk = dev_get_drvdata(dev); in rz_mtu3_cnt_pm_runtime_resume() local
817 clk_prepare_enable(clk); in rz_mtu3_cnt_pm_runtime_resume()
836 struct rz_mtu3 *ddata = dev_get_drvdata(pdev->dev.parent); in rz_mtu3_cnt_probe()
837 struct device *dev = &pdev->dev; in rz_mtu3_cnt_probe()
846 return -ENOMEM; in rz_mtu3_cnt_probe()
849 priv->clk = ddata->clk; in rz_mtu3_cnt_probe()
850 priv->mtu_32bit_max = U32_MAX; in rz_mtu3_cnt_probe()
851 priv->ch = &ddata->channels[RZ_MTU3_CHAN_1]; in rz_mtu3_cnt_probe()
852 ch = &priv->ch[0]; in rz_mtu3_cnt_probe()
854 ch->dev = dev; in rz_mtu3_cnt_probe()
855 priv->mtu_16bit_max[i] = U16_MAX; in rz_mtu3_cnt_probe()
859 mutex_init(&priv->lock); in rz_mtu3_cnt_probe()
860 platform_set_drvdata(pdev, priv->clk); in rz_mtu3_cnt_probe()
861 clk_prepare_enable(priv->clk); in rz_mtu3_cnt_probe()
862 pm_runtime_set_active(&pdev->dev); in rz_mtu3_cnt_probe()
863 pm_runtime_enable(&pdev->dev); in rz_mtu3_cnt_probe()
864 ret = devm_add_action_or_reset(&pdev->dev, rz_mtu3_cnt_pm_disable, dev); in rz_mtu3_cnt_probe()
868 counter->name = dev_name(dev); in rz_mtu3_cnt_probe()
869 counter->parent = dev; in rz_mtu3_cnt_probe()
870 counter->ops = &rz_mtu3_cnt_ops; in rz_mtu3_cnt_probe()
871 counter->counts = rz_mtu3_counts; in rz_mtu3_cnt_probe()
872 counter->num_counts = ARRAY_SIZE(rz_mtu3_counts); in rz_mtu3_cnt_probe()
873 counter->signals = rz_mtu3_signals; in rz_mtu3_cnt_probe()
874 counter->num_signals = ARRAY_SIZE(rz_mtu3_signals); in rz_mtu3_cnt_probe()
875 counter->ext = rz_mtu3_device_ext; in rz_mtu3_cnt_probe()
876 counter->num_ext = ARRAY_SIZE(rz_mtu3_device_ext); in rz_mtu3_cnt_probe()
888 clk_disable_unprepare(priv->clk); in rz_mtu3_cnt_probe()
896 .name = "rz-mtu3-counter",
903 MODULE_ALIAS("platform:rz-mtu3-counter");