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/linux/drivers/video/fbdev/omap2/omapfb/dss/
H A Dvenc.c1 // SPDX-License-Identifier: GPL-2.0-only
15 #include <linux/clk.h>
250 struct clk *tv_dac_clk;
274 venc_write_reg(VENC_LLEN, config->llen); in venc_write_config()
275 venc_write_reg(VENC_FLENS, config->flens); in venc_write_config()
276 venc_write_reg(VENC_CC_CARR_WSS_CARR, config->cc_carr_wss_carr); in venc_write_config()
277 venc_write_reg(VENC_C_PHASE, config->c_phase); in venc_write_config()
278 venc_write_reg(VENC_GAIN_U, config->gain_u); in venc_write_config()
279 venc_write_reg(VENC_GAIN_V, config->gain_v); in venc_write_config()
280 venc_write_reg(VENC_GAIN_Y, config->gain_y); in venc_write_config()
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H A Ddss.h1 /* SPDX-License-Identifier: GPL-2.0-only */
59 #define FLD_MASK(start, end) (((1 << ((start) - (end) + 1)) - 1) << (end))
105 * Type-A PLLs: clkout[]/mX[] refer to hsdiv outputs m4, m5, m6, m7.
106 * Type-B PLLs: clkout[0] refers to m2.
152 struct clk *clkin;
210 int dss_mgr_simple_check(struct omap_overlay_manager *mgr,
212 int dss_mgr_check_timings(struct omap_overlay_manager *mgr,
214 int dss_mgr_check(struct omap_overlay_manager *mgr,
229 int dss_manager_kobj_init(struct omap_overlay_manager *mgr,
231 void dss_manager_kobj_uninit(struct omap_overlay_manager *mgr);
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H A Ddpi.c1 // SPDX-License-Identifier: GPL-2.0-only
24 #include <linux/clk.h>
56 /* only used in non-DT mode */
156 if (ctx->pck_min >= 100000000) { in dpi_calc_dispc_cb()
164 ctx->dispc_cinfo.lck_div = lckd; in dpi_calc_dispc_cb()
165 ctx->dispc_cinfo.pck_div = pckd; in dpi_calc_dispc_cb()
166 ctx->dispc_cinfo.lck = lck; in dpi_calc_dispc_cb()
167 ctx->dispc_cinfo.pck = pck; in dpi_calc_dispc_cb()
183 if (m_dispc > 1 && m_dispc % 2 != 0 && ctx->pck_min >= 100000000) in dpi_calc_hsdiv_cb()
186 ctx->dsi_cinfo.mX[HSDIV_DISPC] = m_dispc; in dpi_calc_hsdiv_cb()
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H A Dhdmi4.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com/
21 #include <linux/clk.h>
27 #include <sound/omap-hdmi-audio.h>
42 r = pm_runtime_resume_and_get(&hdmi.pdev->dev); in hdmi_runtime_get()
55 r = pm_runtime_put_sync(&hdmi.pdev->dev); in hdmi_runtime_put()
56 WARN_ON(r < 0 && r != -ENOSYS); in hdmi_runtime_put()
97 reg = devm_regulator_get(&hdmi.pdev->dev, "vdda"); in hdmi_init_regulator()
100 if (PTR_ERR(reg) != -EPROBE_DEFER) in hdmi_init_regulator()
147 struct omap_overlay_manager *mgr = hdmi.output.manager; in hdmi_power_on_full() local
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H A Dhdmi5.c1 // SPDX-License-Identifier: GPL-2.0-only
26 #include <linux/clk.h>
32 #include <sound/omap-hdmi-audio.h>
46 r = pm_runtime_resume_and_get(&hdmi.pdev->dev); in hdmi_runtime_get()
59 r = pm_runtime_put_sync(&hdmi.pdev->dev); in hdmi_runtime_put()
60 WARN_ON(r < 0 && r != -ENOSYS); in hdmi_runtime_put()
116 reg = devm_regulator_get(&hdmi.pdev->dev, "vdda"); in hdmi_init_regulator()
164 struct omap_overlay_manager *mgr = hdmi.output.manager; in hdmi_power_on_full() local
173 DSSDBG("hdmi_power_on x_res= %d y_res = %d\n", p->x_res, p->y_res); in hdmi_power_on_full()
175 hdmi_pll_compute(&hdmi.pll, p->pixelclock, &hdmi_cinfo); in hdmi_power_on_full()
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H A Ddsi.c1 // SPDX-License-Identifier: GPL-2.0-only
13 #include <linux/clk.h>
207 struct omap_overlay_manager *mgr);
209 struct omap_overlay_manager *mgr);
303 struct clk *dss_clk;
408 return to_platform_device(dssdev->dev); in dsi_get_dsidev_from_dssdev()
429 return out ? to_platform_device(out->dev) : NULL; in dsi_get_dsidev_from_id()
439 case DSI_PROTO: base = dsi->proto_base; break; in dsi_write_reg()
440 case DSI_PHY: base = dsi->phy_base; break; in dsi_write_reg()
441 case DSI_PLL: base = dsi->pll_base; break; in dsi_write_reg()
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/linux/Documentation/devicetree/bindings/arm/altera/
H A Dsocfpga-clk-manager.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/arm/altera/socfpga-clk-manager.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dinh Nguyen <dinguyen@kernel.org>
17 - const: altr,clk-mgr
22 - compatible
27 - |
29 compatible = "altr,clk-mgr";
/linux/Documentation/devicetree/bindings/i2c/
H A Dnuvoton,npcm7xx-i2c.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/i2c/nuvoton,npcm7xx-i2c.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
15 - Tali Perry <tali.perry1@gmail.com>
20 - nuvoton,npcm750-i2c
21 - nuvoton,npcm845-i2c
33 clock-frequency:
40 nuvoton,sys-mgr:
45 - compatible
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/linux/arch/arm/boot/dts/intel/socfpga/
H A Dsocfpga.dtsi1 // SPDX-License-Identifier: GPL-2.0+
6 #include <dt-bindings/reset/altr,rst-mgr.h>
9 #address-cells = <1>;
10 #size-cells = <1>;
22 #address-cells = <1>;
23 #size-cells = <0>;
24 enable-method = "altr,socfpga-smp";
27 compatible = "arm,cortex-a9";
30 next-level-cache = <&L2>;
33 compatible = "arm,cortex-a9";
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/linux/arch/arm64/boot/dts/altera/
H A Dsocfpga_stratix10.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
6 /dts-v1/;
7 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/clock/stratix10-clock.h>
12 compatible = "altr,socfpga-stratix10";
13 #address-cells = <2>;
14 #size-cells = <2>;
16 reserved-memory {
17 #address-cells = <2>;
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/linux/Documentation/devicetree/bindings/fpga/
H A Dfpga-region.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/fpga/fpga-region.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Michal Simek <michal.simek@amd.com>
14 - Introduction
15 - Terminology
16 - Sequence
17 - FPGA Region
18 - Supported Use Models
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/linux/drivers/clk/socfpga/
H A Dclk-pll.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 2011-2012 Calxeda, Inc.
4 * Copyright (C) 2012-2013 Altera Corporation <www.altera.com>
6 * Based from clk-highbank.c
9 #include <linux/clk-provider.h>
14 #include "clk.h"
46 reg = readl(socfpgaclk->hw.reg); in clk_pll_recalc_rate()
63 pll_src = readl(socfpgaclk->hw.reg); in clk_pll_get_parent()
79 const char *clk_name = node->name; in __socfpga_pll_init()
91 clkmgr_np = of_find_compatible_node(NULL, NULL, "altr,clk-mgr"); in __socfpga_pll_init()
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/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/
H A Ddce112_clk_mgr.h2 * Copyright 2012-16 Advanced Micro Devices, Inc.
34 /* functions shared with other clk mgr */
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/
H A Ddce110_clk_mgr.h2 * Copyright 2012-16 Advanced Micro Devices, Inc.
37 /* functions shared with other clk mgr*/
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn401/
H A Ddcn401_fpu.c1 // SPDX-License-Identifier: MIT
16 double pstate_latency_us = clk_mgr->ctx->dc->dml.soc.dram_clock_change_latency_us; in dcn401_build_wm_range_table_fpu()
17 double fclk_change_latency_us = clk_mgr->ctx->dc->dml.soc.fclk_change_latency_us; in dcn401_build_wm_range_table_fpu()
18 double sr_exit_time_us = clk_mgr->ctx->dc->dml.soc.sr_exit_time_us; in dcn401_build_wm_range_table_fpu()
19 double sr_enter_plus_exit_time_us = clk_mgr->ctx->dc->dml.soc.sr_enter_plus_exit_time_us; in dcn401_build_wm_range_table_fpu()
21 uint16_t min_uclk_mhz = clk_mgr->bw_params->clk_table.entries[0].memclk_mhz; in dcn401_build_wm_range_table_fpu()
22 uint16_t min_dcfclk_mhz = clk_mgr->bw_params->clk_table.entries[0].dcfclk_mhz; in dcn401_build_wm_range_table_fpu()
24 uint16_t dcfclk_mhz_for_the_second_state = clk_mgr->ctx->dc->dml.soc.clock_limits[2].dcfclk_mhz; in dcn401_build_wm_range_table_fpu()
30 …clk_mgr->bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.min_dcfclk = dcfclk_mhz_for_the_secon… in dcn401_build_wm_range_table_fpu()
32 …clk_mgr->bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.min_dcfclk = clk_mgr->bw_params->clk_… in dcn401_build_wm_range_table_fpu()
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/linux/drivers/gpu/drm/amd/display/dc/dml/dcn321/
H A Ddcn321_fpu.c1 // SPDX-License-Identifier: MIT
164 if (entry->dcfclk_mhz > 0) { in get_optimal_ntuple()
165 …float bw_on_sdp = entry->dcfclk_mhz * dcn3_21_soc.return_bus_width_bytes * ((float)dcn3_21_soc.pct… in get_optimal_ntuple()
167 …entry->fabricclk_mhz = bw_on_sdp / (dcn3_21_soc.return_bus_width_bytes * ((float)dcn3_21_soc.pct_i… in get_optimal_ntuple()
168 entry->dram_speed_mts = bw_on_sdp / (dcn3_21_soc.num_chans * in get_optimal_ntuple()
170 } else if (entry->fabricclk_mhz > 0) { in get_optimal_ntuple()
171 …float bw_on_fabric = entry->fabricclk_mhz * dcn3_21_soc.return_bus_width_bytes * ((float)dcn3_21_s… in get_optimal_ntuple()
173 …entry->dcfclk_mhz = bw_on_fabric / (dcn3_21_soc.return_bus_width_bytes * ((float)dcn3_21_soc.pct_i… in get_optimal_ntuple()
174 entry->dram_speed_mts = bw_on_fabric / (dcn3_21_soc.num_chans * in get_optimal_ntuple()
176 } else if (entry->dram_speed_mts > 0) { in get_optimal_ntuple()
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/linux/drivers/slimbus/
H A Dqcom-ctrl.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2011-2017, The Linux Foundation
14 #include <linux/clk.h>
88 /* Resource group info for manager, and non-ported generic device-components */
116 struct clk *rclk;
117 struct clk *hclk;
125 __iowrite32_copy(ctrl->base + tx_reg, buf, count); in qcom_slim_queue_tx()
136 spin_lock_irqsave(&ctrl->rx.lock, flags); in slim_alloc_rxbuf()
137 if ((ctrl->rx.tail + 1) % ctrl->rx.n == ctrl->rx.head) { in slim_alloc_rxbuf()
138 spin_unlock_irqrestore(&ctrl->rx.lock, flags); in slim_alloc_rxbuf()
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/linux/drivers/gpu/drm/amd/display/dc/dml/dcn35/
H A Ddcn35_fpu.c1 // SPDX-License-Identifier: MIT
214 * - with passed few options from dc->config
215 * - with dentist_vco_frequency from Clk Mgr (currently hardcoded, but might
217 * - with passed latency values (passed in ns units) in dc-> bb override for
219 * - with passed latencies from VBIOS (in 100_ns units) if available for
221 * - with number of DRAM channels from VBIOS (which differ for certain dGPU SKU
223 * - clocks levels with passed clk_table entries from Clk Mgr as reported by PM
232 struct clk_limit_table *clk_table = &bw_params->clk_table; in dcn35_update_bw_bounding_box_fpu()
234 dc->scratch.update_bw_bounding_box.clock_limits; in dcn35_update_bw_bounding_box_fpu()
240 dc->res_pool->res_cap->num_timing_generator; in dcn35_update_bw_bounding_box_fpu()
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/linux/drivers/gpu/drm/amd/display/dc/dml/dcn32/
H A Ddcn32_fpu.c1 // SPDX-License-Identifier: MIT
189 double pstate_latency_us = clk_mgr->base.ctx->dc->dml.soc.dram_clock_change_latency_us; in dcn32_build_wm_range_table_fpu()
190 double fclk_change_latency_us = clk_mgr->base.ctx->dc->dml.soc.fclk_change_latency_us; in dcn32_build_wm_range_table_fpu()
191 double sr_exit_time_us = clk_mgr->base.ctx->dc->dml.soc.sr_exit_time_us; in dcn32_build_wm_range_table_fpu()
192 double sr_enter_plus_exit_time_us = clk_mgr->base.ctx->dc->dml.soc.sr_enter_plus_exit_time_us; in dcn32_build_wm_range_table_fpu()
194 uint16_t min_uclk_mhz = clk_mgr->base.bw_params->clk_table.entries[0].memclk_mhz; in dcn32_build_wm_range_table_fpu()
195 uint16_t min_dcfclk_mhz = clk_mgr->base.bw_params->clk_table.entries[0].dcfclk_mhz; in dcn32_build_wm_range_table_fpu()
197 …uint16_t dcfclk_mhz_for_the_second_state = clk_mgr->base.ctx->dc->dml.soc.clock_limits[2].dcfclk_m… in dcn32_build_wm_range_table_fpu()
203 …clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.min_dcfclk = dcfclk_mhz_for_the_… in dcn32_build_wm_range_table_fpu()
205 …clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.min_dcfclk = clk_mgr->base.bw_pa… in dcn32_build_wm_range_table_fpu()
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/linux/drivers/gpu/drm/amd/display/amdgpu_dm/
H A Damdgpu_dm_helpers.c53 return (u32)edid->mfg_id[0] << 24 | in edid_extract_panel_id()
54 (u32)edid->mfg_id[1] << 16 | in edid_extract_panel_id()
68 edid_caps->panel_patch.disable_fams = true; in apply_edid_quirks()
77 edid_caps->panel_patch.remove_sink_ext_caps = true; in apply_edid_quirks()
81 edid_caps->panel_patch.disable_colorimetry = true; in apply_edid_quirks()
89 * dm_helpers_parse_edid_caps() - Parse edid caps
102 struct amdgpu_dm_connector *aconnector = link->priv; in dm_helpers_parse_edid_caps()
103 struct drm_connector *connector = &aconnector->base; in dm_helpers_parse_edid_caps()
104 struct edid *edid_buf = edid ? (struct edid *) edid->raw_edid : NULL; in dm_helpers_parse_edid_caps()
106 int sad_count = -1; in dm_helpers_parse_edid_caps()
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H A Damdgpu_dm.c101 #include <media/cec-notifier.h>
185 switch (link->dpcd_caps.dongle_type) { in get_subconnector_type()
204 struct dc_link *link = aconnector->dc_link; in update_subconnector_property()
205 struct drm_connector *connector = &aconnector->base; in update_subconnector_property()
208 if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort) in update_subconnector_property()
211 if (aconnector->dc_sink) in update_subconnector_property()
214 drm_object_property_set_value(&connector->base, in update_subconnector_property()
215 connector->dev->mode_config.dp_subconnector_property, in update_subconnector_property()
258 * struct amdgpu_device *adev - [in] desired amdgpu device
259 * int disp_idx - [in] which CRTC to get the counter from
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/linux/drivers/gpu/drm/amd/display/dc/dml/calcs/
H A Ddcn_calcs.c40 dc->ctx->logger
50 * This file is gcc-parseable HW gospel, coming straight from HW engineers.
54 * remain as-is as it provides us with a guarantee from HW that it is correct.
70 * slow-slow corner + 10% margin with voltages aligned to FCLK.
74 /* default DCF CLK DPM on RV*/
80 /* default DISP CLK voltage state on RV */
86 /* default DPP CLK voltage state on RV */
92 /* default PHY CLK voltage state on RV */
305 input->src.is_hsplit = false; in pipe_ctx_to_e2e_pipe_params()
308 if (pipe->plane_state->stereo_format == PLANE_STEREO_FORMAT_SIDE_BY_SIDE || in pipe_ctx_to_e2e_pipe_params()
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/linux/drivers/i2c/busses/
H A Di2c-npcm7xx.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk.h>
125 #define NPCM_I2CTXF_CTL 0x12 /* Tx-FIFO Control */
128 #define NPCM_I2CTXF_STS 0x1A /* Tx-FIFO Status */
129 #define NPCM_I2CRXF_STS 0x1C /* Rx-FIFO Status */
130 #define NPCM_I2CRXF_CTL 0x1E /* Rx-FIFO Control */
262 /* supported clk settings. values in Hz. */
602 u8 i2cctl3 = ioread8(bus->reg + NPCM_I2CCTL3); in npcm_i2c_select_bank()
608 iowrite8(i2cctl3, bus->reg + NPCM_I2CCTL3); in npcm_i2c_select_bank()
613 bus->stop_ind = I2C_NO_STATUS_IND; in npcm_i2c_init_params()
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/linux/drivers/gpu/drm/amd/display/dmub/inc/
H A Ddmub_cmd.h143 * Physical framebuffer address location, 64-bit.
255 * @knee_threshold: Current x-position of ACE knee (u0.16).
275 * union dmub_addr - DMUB physical/virtual 64-bit address.
330 * Use HW Lock Mgr object to do HW locking in FW.
457 * 0x1 (bit 0) - Desync Error flag.
462 * 0x2 (bit 1) - State Transition Error flag.
467 * 0x4 (bit 2) - Crc Error flag
472 * 0x8 (bit 3) - Reserved
477 * 0x10 (bit 4) - Incorrect Coasting vtotal checking --> use debug flag to control DPCD write.
483 * 0x20 (bit 5) - No doubled Refresh Rate.
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/linux/
H A DMAINTAINERS5 ---------------------------------------------------
21 W: *Web-page* with status/info
23 B: URI for where to file *bugs*. A web-page with detailed bug
28 patches to the given subsystem. This is either an in-tree file,
29 or a URI. See Documentation/maintainer/maintainer-entry-profile.rst
46 N: [^a-z]tegra all files whose path contains tegra
64 ----------------
83 3WARE SAS/SATA-RAID SCSI DRIVERS (3W-XXXX, 3W-9XXX, 3W-SAS)
85 L: linux-scsi@vger.kernel.org
88 F: drivers/scsi/3w-*
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