1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include <linux/string.h> 27 #include <linux/acpi.h> 28 #include <linux/i2c.h> 29 30 #include <drm/drm_atomic.h> 31 #include <drm/drm_probe_helper.h> 32 #include <drm/amdgpu_drm.h> 33 #include <drm/drm_edid.h> 34 #include <drm/drm_fixed.h> 35 36 #include "dm_services.h" 37 #include "amdgpu.h" 38 #include "dc.h" 39 #include "amdgpu_dm.h" 40 #include "amdgpu_dm_irq.h" 41 #include "amdgpu_dm_mst_types.h" 42 #include "dpcd_defs.h" 43 #include "dc/inc/core_types.h" 44 45 #include "dm_helpers.h" 46 #include "ddc_service_types.h" 47 48 static u32 edid_extract_panel_id(struct edid *edid) 49 { 50 return (u32)edid->mfg_id[0] << 24 | 51 (u32)edid->mfg_id[1] << 16 | 52 (u32)EDID_PRODUCT_ID(edid); 53 } 54 55 static void apply_edid_quirks(struct edid *edid, struct dc_edid_caps *edid_caps) 56 { 57 uint32_t panel_id = edid_extract_panel_id(edid); 58 59 switch (panel_id) { 60 /* Workaround for some monitors which does not work well with FAMS */ 61 case drm_edid_encode_panel_id('S', 'A', 'M', 0x0E5E): 62 case drm_edid_encode_panel_id('S', 'A', 'M', 0x7053): 63 case drm_edid_encode_panel_id('S', 'A', 'M', 0x71AC): 64 DRM_DEBUG_DRIVER("Disabling FAMS on monitor with panel id %X\n", panel_id); 65 edid_caps->panel_patch.disable_fams = true; 66 break; 67 /* Workaround for some monitors that do not clear DPCD 0x317 if FreeSync is unsupported */ 68 case drm_edid_encode_panel_id('A', 'U', 'O', 0xA7AB): 69 case drm_edid_encode_panel_id('A', 'U', 'O', 0xE69B): 70 case drm_edid_encode_panel_id('B', 'O', 'E', 0x092A): 71 case drm_edid_encode_panel_id('L', 'G', 'D', 0x06D1): 72 case drm_edid_encode_panel_id('M', 'S', 'F', 0x1003): 73 DRM_DEBUG_DRIVER("Clearing DPCD 0x317 on monitor with panel id %X\n", panel_id); 74 edid_caps->panel_patch.remove_sink_ext_caps = true; 75 break; 76 default: 77 return; 78 } 79 } 80 81 /** 82 * dm_helpers_parse_edid_caps() - Parse edid caps 83 * 84 * @link: current detected link 85 * @edid: [in] pointer to edid 86 * @edid_caps: [in] pointer to edid caps 87 * 88 * Return: void 89 */ 90 enum dc_edid_status dm_helpers_parse_edid_caps( 91 struct dc_link *link, 92 const struct dc_edid *edid, 93 struct dc_edid_caps *edid_caps) 94 { 95 struct amdgpu_dm_connector *aconnector = link->priv; 96 struct drm_connector *connector = &aconnector->base; 97 struct edid *edid_buf = edid ? (struct edid *) edid->raw_edid : NULL; 98 struct cea_sad *sads; 99 int sad_count = -1; 100 int sadb_count = -1; 101 int i = 0; 102 uint8_t *sadb = NULL; 103 104 enum dc_edid_status result = EDID_OK; 105 106 if (!edid_caps || !edid) 107 return EDID_BAD_INPUT; 108 109 if (!drm_edid_is_valid(edid_buf)) 110 result = EDID_BAD_CHECKSUM; 111 112 edid_caps->manufacturer_id = (uint16_t) edid_buf->mfg_id[0] | 113 ((uint16_t) edid_buf->mfg_id[1])<<8; 114 edid_caps->product_id = (uint16_t) edid_buf->prod_code[0] | 115 ((uint16_t) edid_buf->prod_code[1])<<8; 116 edid_caps->serial_number = edid_buf->serial; 117 edid_caps->manufacture_week = edid_buf->mfg_week; 118 edid_caps->manufacture_year = edid_buf->mfg_year; 119 120 drm_edid_get_monitor_name(edid_buf, 121 edid_caps->display_name, 122 AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS); 123 124 edid_caps->edid_hdmi = connector->display_info.is_hdmi; 125 126 apply_edid_quirks(edid_buf, edid_caps); 127 128 sad_count = drm_edid_to_sad((struct edid *) edid->raw_edid, &sads); 129 if (sad_count <= 0) 130 return result; 131 132 edid_caps->audio_mode_count = min(sad_count, DC_MAX_AUDIO_DESC_COUNT); 133 for (i = 0; i < edid_caps->audio_mode_count; ++i) { 134 struct cea_sad *sad = &sads[i]; 135 136 edid_caps->audio_modes[i].format_code = sad->format; 137 edid_caps->audio_modes[i].channel_count = sad->channels + 1; 138 edid_caps->audio_modes[i].sample_rate = sad->freq; 139 edid_caps->audio_modes[i].sample_size = sad->byte2; 140 } 141 142 sadb_count = drm_edid_to_speaker_allocation((struct edid *) edid->raw_edid, &sadb); 143 144 if (sadb_count < 0) { 145 DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sadb_count); 146 sadb_count = 0; 147 } 148 149 if (sadb_count) 150 edid_caps->speaker_flags = sadb[0]; 151 else 152 edid_caps->speaker_flags = DEFAULT_SPEAKER_LOCATION; 153 154 kfree(sads); 155 kfree(sadb); 156 157 return result; 158 } 159 160 static void 161 fill_dc_mst_payload_table_from_drm(struct dc_link *link, 162 bool enable, 163 struct drm_dp_mst_atomic_payload *target_payload, 164 struct dc_dp_mst_stream_allocation_table *table) 165 { 166 struct dc_dp_mst_stream_allocation_table new_table = { 0 }; 167 struct dc_dp_mst_stream_allocation *sa; 168 struct link_mst_stream_allocation_table copy_of_link_table = 169 link->mst_stream_alloc_table; 170 171 int i; 172 int current_hw_table_stream_cnt = copy_of_link_table.stream_count; 173 struct link_mst_stream_allocation *dc_alloc; 174 175 /* TODO: refactor to set link->mst_stream_alloc_table directly if possible.*/ 176 if (enable) { 177 dc_alloc = 178 ©_of_link_table.stream_allocations[current_hw_table_stream_cnt]; 179 dc_alloc->vcp_id = target_payload->vcpi; 180 dc_alloc->slot_count = target_payload->time_slots; 181 } else { 182 for (i = 0; i < copy_of_link_table.stream_count; i++) { 183 dc_alloc = 184 ©_of_link_table.stream_allocations[i]; 185 186 if (dc_alloc->vcp_id == target_payload->vcpi) { 187 dc_alloc->vcp_id = 0; 188 dc_alloc->slot_count = 0; 189 break; 190 } 191 } 192 ASSERT(i != copy_of_link_table.stream_count); 193 } 194 195 /* Fill payload info*/ 196 for (i = 0; i < MAX_CONTROLLER_NUM; i++) { 197 dc_alloc = 198 ©_of_link_table.stream_allocations[i]; 199 if (dc_alloc->vcp_id > 0 && dc_alloc->slot_count > 0) { 200 sa = &new_table.stream_allocations[new_table.stream_count]; 201 sa->slot_count = dc_alloc->slot_count; 202 sa->vcp_id = dc_alloc->vcp_id; 203 new_table.stream_count++; 204 } 205 } 206 207 /* Overwrite the old table */ 208 *table = new_table; 209 } 210 211 void dm_helpers_dp_update_branch_info( 212 struct dc_context *ctx, 213 const struct dc_link *link) 214 {} 215 216 static void dm_helpers_construct_old_payload( 217 struct drm_dp_mst_topology_mgr *mgr, 218 struct drm_dp_mst_topology_state *mst_state, 219 struct drm_dp_mst_atomic_payload *new_payload, 220 struct drm_dp_mst_atomic_payload *old_payload) 221 { 222 struct drm_dp_mst_atomic_payload *pos; 223 int pbn_per_slot = dfixed_trunc(mst_state->pbn_div); 224 u8 next_payload_vc_start = mgr->next_start_slot; 225 u8 payload_vc_start = new_payload->vc_start_slot; 226 u8 allocated_time_slots; 227 228 *old_payload = *new_payload; 229 230 /* Set correct time_slots/PBN of old payload. 231 * other fields (delete & dsc_enabled) in 232 * struct drm_dp_mst_atomic_payload are don't care fields 233 * while calling drm_dp_remove_payload_part2() 234 */ 235 list_for_each_entry(pos, &mst_state->payloads, next) { 236 if (pos != new_payload && 237 pos->vc_start_slot > payload_vc_start && 238 pos->vc_start_slot < next_payload_vc_start) 239 next_payload_vc_start = pos->vc_start_slot; 240 } 241 242 allocated_time_slots = next_payload_vc_start - payload_vc_start; 243 244 old_payload->time_slots = allocated_time_slots; 245 old_payload->pbn = allocated_time_slots * pbn_per_slot; 246 } 247 248 /* 249 * Writes payload allocation table in immediate downstream device. 250 */ 251 bool dm_helpers_dp_mst_write_payload_allocation_table( 252 struct dc_context *ctx, 253 const struct dc_stream_state *stream, 254 struct dc_dp_mst_stream_allocation_table *proposed_table, 255 bool enable) 256 { 257 struct amdgpu_dm_connector *aconnector; 258 struct drm_dp_mst_topology_state *mst_state; 259 struct drm_dp_mst_atomic_payload *target_payload, *new_payload, old_payload; 260 struct drm_dp_mst_topology_mgr *mst_mgr; 261 262 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context; 263 /* Accessing the connector state is required for vcpi_slots allocation 264 * and directly relies on behaviour in commit check 265 * that blocks before commit guaranteeing that the state 266 * is not gonna be swapped while still in use in commit tail 267 */ 268 269 if (!aconnector || !aconnector->mst_root) 270 return false; 271 272 mst_mgr = &aconnector->mst_root->mst_mgr; 273 mst_state = to_drm_dp_mst_topology_state(mst_mgr->base.state); 274 new_payload = drm_atomic_get_mst_payload_state(mst_state, aconnector->mst_output_port); 275 276 if (enable) { 277 target_payload = new_payload; 278 279 /* It's OK for this to fail */ 280 drm_dp_add_payload_part1(mst_mgr, mst_state, new_payload); 281 } else { 282 /* construct old payload by VCPI*/ 283 dm_helpers_construct_old_payload(mst_mgr, mst_state, 284 new_payload, &old_payload); 285 target_payload = &old_payload; 286 287 drm_dp_remove_payload_part1(mst_mgr, mst_state, new_payload); 288 } 289 290 /* mst_mgr->->payloads are VC payload notify MST branch using DPCD or 291 * AUX message. The sequence is slot 1-63 allocated sequence for each 292 * stream. AMD ASIC stream slot allocation should follow the same 293 * sequence. copy DRM MST allocation to dc 294 */ 295 fill_dc_mst_payload_table_from_drm(stream->link, enable, target_payload, proposed_table); 296 297 return true; 298 } 299 300 /* 301 * poll pending down reply 302 */ 303 void dm_helpers_dp_mst_poll_pending_down_reply( 304 struct dc_context *ctx, 305 const struct dc_link *link) 306 {} 307 308 /* 309 * Clear payload allocation table before enable MST DP link. 310 */ 311 void dm_helpers_dp_mst_clear_payload_allocation_table( 312 struct dc_context *ctx, 313 const struct dc_link *link) 314 {} 315 316 /* 317 * Polls for ACT (allocation change trigger) handled and sends 318 * ALLOCATE_PAYLOAD message. 319 */ 320 enum act_return_status dm_helpers_dp_mst_poll_for_allocation_change_trigger( 321 struct dc_context *ctx, 322 const struct dc_stream_state *stream) 323 { 324 struct amdgpu_dm_connector *aconnector; 325 struct drm_dp_mst_topology_mgr *mst_mgr; 326 int ret; 327 328 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context; 329 330 if (!aconnector || !aconnector->mst_root) 331 return ACT_FAILED; 332 333 mst_mgr = &aconnector->mst_root->mst_mgr; 334 335 if (!mst_mgr->mst_state) 336 return ACT_FAILED; 337 338 ret = drm_dp_check_act_status(mst_mgr); 339 340 if (ret) 341 return ACT_FAILED; 342 343 return ACT_SUCCESS; 344 } 345 346 void dm_helpers_dp_mst_send_payload_allocation( 347 struct dc_context *ctx, 348 const struct dc_stream_state *stream) 349 { 350 struct amdgpu_dm_connector *aconnector; 351 struct drm_dp_mst_topology_state *mst_state; 352 struct drm_dp_mst_topology_mgr *mst_mgr; 353 struct drm_dp_mst_atomic_payload *new_payload; 354 enum mst_progress_status set_flag = MST_ALLOCATE_NEW_PAYLOAD; 355 enum mst_progress_status clr_flag = MST_CLEAR_ALLOCATED_PAYLOAD; 356 int ret = 0; 357 358 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context; 359 360 if (!aconnector || !aconnector->mst_root) 361 return; 362 363 mst_mgr = &aconnector->mst_root->mst_mgr; 364 mst_state = to_drm_dp_mst_topology_state(mst_mgr->base.state); 365 new_payload = drm_atomic_get_mst_payload_state(mst_state, aconnector->mst_output_port); 366 367 ret = drm_dp_add_payload_part2(mst_mgr, new_payload); 368 369 if (ret) { 370 amdgpu_dm_set_mst_status(&aconnector->mst_status, 371 set_flag, false); 372 } else { 373 amdgpu_dm_set_mst_status(&aconnector->mst_status, 374 set_flag, true); 375 amdgpu_dm_set_mst_status(&aconnector->mst_status, 376 clr_flag, false); 377 } 378 } 379 380 void dm_helpers_dp_mst_update_mst_mgr_for_deallocation( 381 struct dc_context *ctx, 382 const struct dc_stream_state *stream) 383 { 384 struct amdgpu_dm_connector *aconnector; 385 struct drm_dp_mst_topology_state *mst_state; 386 struct drm_dp_mst_topology_mgr *mst_mgr; 387 struct drm_dp_mst_atomic_payload *new_payload, old_payload; 388 enum mst_progress_status set_flag = MST_CLEAR_ALLOCATED_PAYLOAD; 389 enum mst_progress_status clr_flag = MST_ALLOCATE_NEW_PAYLOAD; 390 391 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context; 392 393 if (!aconnector || !aconnector->mst_root) 394 return; 395 396 mst_mgr = &aconnector->mst_root->mst_mgr; 397 mst_state = to_drm_dp_mst_topology_state(mst_mgr->base.state); 398 new_payload = drm_atomic_get_mst_payload_state(mst_state, aconnector->mst_output_port); 399 dm_helpers_construct_old_payload(mst_mgr, mst_state, 400 new_payload, &old_payload); 401 402 drm_dp_remove_payload_part2(mst_mgr, mst_state, &old_payload, new_payload); 403 404 amdgpu_dm_set_mst_status(&aconnector->mst_status, set_flag, true); 405 amdgpu_dm_set_mst_status(&aconnector->mst_status, clr_flag, false); 406 } 407 408 void dm_dtn_log_begin(struct dc_context *ctx, 409 struct dc_log_buffer_ctx *log_ctx) 410 { 411 static const char msg[] = "[dtn begin]\n"; 412 413 if (!log_ctx) { 414 pr_info("%s", msg); 415 return; 416 } 417 418 dm_dtn_log_append_v(ctx, log_ctx, "%s", msg); 419 } 420 421 __printf(3, 4) 422 void dm_dtn_log_append_v(struct dc_context *ctx, 423 struct dc_log_buffer_ctx *log_ctx, 424 const char *msg, ...) 425 { 426 va_list args; 427 size_t total; 428 int n; 429 430 if (!log_ctx) { 431 /* No context, redirect to dmesg. */ 432 struct va_format vaf; 433 434 vaf.fmt = msg; 435 vaf.va = &args; 436 437 va_start(args, msg); 438 pr_info("%pV", &vaf); 439 va_end(args); 440 441 return; 442 } 443 444 /* Measure the output. */ 445 va_start(args, msg); 446 n = vsnprintf(NULL, 0, msg, args); 447 va_end(args); 448 449 if (n <= 0) 450 return; 451 452 /* Reallocate the string buffer as needed. */ 453 total = log_ctx->pos + n + 1; 454 455 if (total > log_ctx->size) { 456 char *buf = kvcalloc(total, sizeof(char), GFP_KERNEL); 457 458 if (buf) { 459 memcpy(buf, log_ctx->buf, log_ctx->pos); 460 kfree(log_ctx->buf); 461 462 log_ctx->buf = buf; 463 log_ctx->size = total; 464 } 465 } 466 467 if (!log_ctx->buf) 468 return; 469 470 /* Write the formatted string to the log buffer. */ 471 va_start(args, msg); 472 n = vscnprintf( 473 log_ctx->buf + log_ctx->pos, 474 log_ctx->size - log_ctx->pos, 475 msg, 476 args); 477 va_end(args); 478 479 if (n > 0) 480 log_ctx->pos += n; 481 } 482 483 void dm_dtn_log_end(struct dc_context *ctx, 484 struct dc_log_buffer_ctx *log_ctx) 485 { 486 static const char msg[] = "[dtn end]\n"; 487 488 if (!log_ctx) { 489 pr_info("%s", msg); 490 return; 491 } 492 493 dm_dtn_log_append_v(ctx, log_ctx, "%s", msg); 494 } 495 496 bool dm_helpers_dp_mst_start_top_mgr( 497 struct dc_context *ctx, 498 const struct dc_link *link, 499 bool boot) 500 { 501 struct amdgpu_dm_connector *aconnector = link->priv; 502 int ret; 503 504 if (!aconnector) { 505 DRM_ERROR("Failed to find connector for link!"); 506 return false; 507 } 508 509 if (boot) { 510 DRM_INFO("DM_MST: Differing MST start on aconnector: %p [id: %d]\n", 511 aconnector, aconnector->base.base.id); 512 return true; 513 } 514 515 DRM_INFO("DM_MST: starting TM on aconnector: %p [id: %d]\n", 516 aconnector, aconnector->base.base.id); 517 518 ret = drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true); 519 if (ret < 0) { 520 DRM_ERROR("DM_MST: Failed to set the device into MST mode!"); 521 return false; 522 } 523 524 DRM_INFO("DM_MST: DP%x, %d-lane link detected\n", aconnector->mst_mgr.dpcd[0], 525 aconnector->mst_mgr.dpcd[2] & DP_MAX_LANE_COUNT_MASK); 526 527 return true; 528 } 529 530 bool dm_helpers_dp_mst_stop_top_mgr( 531 struct dc_context *ctx, 532 struct dc_link *link) 533 { 534 struct amdgpu_dm_connector *aconnector = link->priv; 535 536 if (!aconnector) { 537 DRM_ERROR("Failed to find connector for link!"); 538 return false; 539 } 540 541 DRM_INFO("DM_MST: stopping TM on aconnector: %p [id: %d]\n", 542 aconnector, aconnector->base.base.id); 543 544 if (aconnector->mst_mgr.mst_state == true) { 545 drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, false); 546 link->cur_link_settings.lane_count = 0; 547 } 548 549 return false; 550 } 551 552 bool dm_helpers_dp_read_dpcd( 553 struct dc_context *ctx, 554 const struct dc_link *link, 555 uint32_t address, 556 uint8_t *data, 557 uint32_t size) 558 { 559 560 struct amdgpu_dm_connector *aconnector = link->priv; 561 562 if (!aconnector) 563 return false; 564 565 return drm_dp_dpcd_read(&aconnector->dm_dp_aux.aux, address, data, 566 size) == size; 567 } 568 569 bool dm_helpers_dp_write_dpcd( 570 struct dc_context *ctx, 571 const struct dc_link *link, 572 uint32_t address, 573 const uint8_t *data, 574 uint32_t size) 575 { 576 struct amdgpu_dm_connector *aconnector = link->priv; 577 578 if (!aconnector) 579 return false; 580 581 return drm_dp_dpcd_write(&aconnector->dm_dp_aux.aux, 582 address, (uint8_t *)data, size) > 0; 583 } 584 585 bool dm_helpers_submit_i2c( 586 struct dc_context *ctx, 587 const struct dc_link *link, 588 struct i2c_command *cmd) 589 { 590 struct amdgpu_dm_connector *aconnector = link->priv; 591 struct i2c_msg *msgs; 592 int i = 0; 593 int num = cmd->number_of_payloads; 594 bool result; 595 596 if (!aconnector) { 597 DRM_ERROR("Failed to find connector for link!"); 598 return false; 599 } 600 601 msgs = kcalloc(num, sizeof(struct i2c_msg), GFP_KERNEL); 602 603 if (!msgs) 604 return false; 605 606 for (i = 0; i < num; i++) { 607 msgs[i].flags = cmd->payloads[i].write ? 0 : I2C_M_RD; 608 msgs[i].addr = cmd->payloads[i].address; 609 msgs[i].len = cmd->payloads[i].length; 610 msgs[i].buf = cmd->payloads[i].data; 611 } 612 613 result = i2c_transfer(&aconnector->i2c->base, msgs, num) == num; 614 615 kfree(msgs); 616 617 return result; 618 } 619 620 static bool execute_synaptics_rc_command(struct drm_dp_aux *aux, 621 bool is_write_cmd, 622 unsigned char cmd, 623 unsigned int length, 624 unsigned int offset, 625 unsigned char *data) 626 { 627 bool success = false; 628 unsigned char rc_data[16] = {0}; 629 unsigned char rc_offset[4] = {0}; 630 unsigned char rc_length[2] = {0}; 631 unsigned char rc_cmd = 0; 632 unsigned char rc_result = 0xFF; 633 unsigned char i = 0; 634 int ret; 635 636 if (is_write_cmd) { 637 // write rc data 638 memmove(rc_data, data, length); 639 ret = drm_dp_dpcd_write(aux, SYNAPTICS_RC_DATA, rc_data, sizeof(rc_data)); 640 } 641 642 // write rc offset 643 rc_offset[0] = (unsigned char) offset & 0xFF; 644 rc_offset[1] = (unsigned char) (offset >> 8) & 0xFF; 645 rc_offset[2] = (unsigned char) (offset >> 16) & 0xFF; 646 rc_offset[3] = (unsigned char) (offset >> 24) & 0xFF; 647 ret = drm_dp_dpcd_write(aux, SYNAPTICS_RC_OFFSET, rc_offset, sizeof(rc_offset)); 648 649 // write rc length 650 rc_length[0] = (unsigned char) length & 0xFF; 651 rc_length[1] = (unsigned char) (length >> 8) & 0xFF; 652 ret = drm_dp_dpcd_write(aux, SYNAPTICS_RC_LENGTH, rc_length, sizeof(rc_length)); 653 654 // write rc cmd 655 rc_cmd = cmd | 0x80; 656 ret = drm_dp_dpcd_write(aux, SYNAPTICS_RC_COMMAND, &rc_cmd, sizeof(rc_cmd)); 657 658 if (ret < 0) { 659 DRM_ERROR("%s: write cmd ..., err = %d\n", __func__, ret); 660 return false; 661 } 662 663 // poll until active is 0 664 for (i = 0; i < 10; i++) { 665 drm_dp_dpcd_read(aux, SYNAPTICS_RC_COMMAND, &rc_cmd, sizeof(rc_cmd)); 666 if (rc_cmd == cmd) 667 // active is 0 668 break; 669 msleep(10); 670 } 671 672 // read rc result 673 drm_dp_dpcd_read(aux, SYNAPTICS_RC_RESULT, &rc_result, sizeof(rc_result)); 674 success = (rc_result == 0); 675 676 if (success && !is_write_cmd) { 677 // read rc data 678 drm_dp_dpcd_read(aux, SYNAPTICS_RC_DATA, data, length); 679 } 680 681 drm_dbg_dp(aux->drm_dev, "success = %d\n", success); 682 683 return success; 684 } 685 686 static void apply_synaptics_fifo_reset_wa(struct drm_dp_aux *aux) 687 { 688 unsigned char data[16] = {0}; 689 690 drm_dbg_dp(aux->drm_dev, "Start\n"); 691 692 // Step 2 693 data[0] = 'P'; 694 data[1] = 'R'; 695 data[2] = 'I'; 696 data[3] = 'U'; 697 data[4] = 'S'; 698 699 if (!execute_synaptics_rc_command(aux, true, 0x01, 5, 0, data)) 700 return; 701 702 // Step 3 and 4 703 if (!execute_synaptics_rc_command(aux, false, 0x31, 4, 0x220998, data)) 704 return; 705 706 data[0] &= (~(1 << 1)); // set bit 1 to 0 707 if (!execute_synaptics_rc_command(aux, true, 0x21, 4, 0x220998, data)) 708 return; 709 710 if (!execute_synaptics_rc_command(aux, false, 0x31, 4, 0x220D98, data)) 711 return; 712 713 data[0] &= (~(1 << 1)); // set bit 1 to 0 714 if (!execute_synaptics_rc_command(aux, true, 0x21, 4, 0x220D98, data)) 715 return; 716 717 if (!execute_synaptics_rc_command(aux, false, 0x31, 4, 0x221198, data)) 718 return; 719 720 data[0] &= (~(1 << 1)); // set bit 1 to 0 721 if (!execute_synaptics_rc_command(aux, true, 0x21, 4, 0x221198, data)) 722 return; 723 724 // Step 3 and 5 725 if (!execute_synaptics_rc_command(aux, false, 0x31, 4, 0x220998, data)) 726 return; 727 728 data[0] |= (1 << 1); // set bit 1 to 1 729 if (!execute_synaptics_rc_command(aux, true, 0x21, 4, 0x220998, data)) 730 return; 731 732 if (!execute_synaptics_rc_command(aux, false, 0x31, 4, 0x220D98, data)) 733 return; 734 735 data[0] |= (1 << 1); // set bit 1 to 1 736 737 if (!execute_synaptics_rc_command(aux, false, 0x31, 4, 0x221198, data)) 738 return; 739 740 data[0] |= (1 << 1); // set bit 1 to 1 741 if (!execute_synaptics_rc_command(aux, true, 0x21, 4, 0x221198, data)) 742 return; 743 744 // Step 6 745 if (!execute_synaptics_rc_command(aux, true, 0x02, 0, 0, NULL)) 746 return; 747 748 drm_dbg_dp(aux->drm_dev, "Done\n"); 749 } 750 751 /* MST Dock */ 752 static const uint8_t SYNAPTICS_DEVICE_ID[] = "SYNA"; 753 754 static uint8_t write_dsc_enable_synaptics_non_virtual_dpcd_mst( 755 struct drm_dp_aux *aux, 756 const struct dc_stream_state *stream, 757 bool enable) 758 { 759 uint8_t ret = 0; 760 761 drm_dbg_dp(aux->drm_dev, 762 "Configure DSC to non-virtual dpcd synaptics\n"); 763 764 if (enable) { 765 /* When DSC is enabled on previous boot and reboot with the hub, 766 * there is a chance that Synaptics hub gets stuck during reboot sequence. 767 * Applying a workaround to reset Synaptics SDP fifo before enabling the first stream 768 */ 769 if (!stream->link->link_status.link_active && 770 memcmp(stream->link->dpcd_caps.branch_dev_name, 771 (int8_t *)SYNAPTICS_DEVICE_ID, 4) == 0) 772 apply_synaptics_fifo_reset_wa(aux); 773 774 ret = drm_dp_dpcd_write(aux, DP_DSC_ENABLE, &enable, 1); 775 DRM_INFO("Send DSC enable to synaptics\n"); 776 777 } else { 778 /* Synaptics hub not support virtual dpcd, 779 * external monitor occur garbage while disable DSC, 780 * Disable DSC only when entire link status turn to false, 781 */ 782 if (!stream->link->link_status.link_active) { 783 ret = drm_dp_dpcd_write(aux, DP_DSC_ENABLE, &enable, 1); 784 DRM_INFO("Send DSC disable to synaptics\n"); 785 } 786 } 787 788 return ret; 789 } 790 791 bool dm_helpers_dp_write_dsc_enable( 792 struct dc_context *ctx, 793 const struct dc_stream_state *stream, 794 bool enable) 795 { 796 static const uint8_t DSC_DISABLE; 797 static const uint8_t DSC_DECODING = 0x01; 798 static const uint8_t DSC_PASSTHROUGH = 0x02; 799 800 struct amdgpu_dm_connector *aconnector = 801 (struct amdgpu_dm_connector *)stream->dm_stream_context; 802 struct drm_device *dev = aconnector->base.dev; 803 struct drm_dp_mst_port *port; 804 uint8_t enable_dsc = enable ? DSC_DECODING : DSC_DISABLE; 805 uint8_t enable_passthrough = enable ? DSC_PASSTHROUGH : DSC_DISABLE; 806 uint8_t ret = 0; 807 808 if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) { 809 if (!aconnector->dsc_aux) 810 return false; 811 812 // apply w/a to synaptics 813 if (needs_dsc_aux_workaround(aconnector->dc_link) && 814 (aconnector->mst_downstream_port_present.byte & 0x7) != 0x3) 815 return write_dsc_enable_synaptics_non_virtual_dpcd_mst( 816 aconnector->dsc_aux, stream, enable_dsc); 817 818 port = aconnector->mst_output_port; 819 820 if (enable) { 821 if (port->passthrough_aux) { 822 ret = drm_dp_dpcd_write(port->passthrough_aux, 823 DP_DSC_ENABLE, 824 &enable_passthrough, 1); 825 drm_dbg_dp(dev, 826 "Sent DSC pass-through enable to virtual dpcd port, ret = %u\n", 827 ret); 828 } 829 830 ret = drm_dp_dpcd_write(aconnector->dsc_aux, 831 DP_DSC_ENABLE, &enable_dsc, 1); 832 drm_dbg_dp(dev, 833 "Sent DSC decoding enable to %s port, ret = %u\n", 834 (port->passthrough_aux) ? "remote RX" : 835 "virtual dpcd", 836 ret); 837 } else { 838 ret = drm_dp_dpcd_write(aconnector->dsc_aux, 839 DP_DSC_ENABLE, &enable_dsc, 1); 840 drm_dbg_dp(dev, 841 "Sent DSC decoding disable to %s port, ret = %u\n", 842 (port->passthrough_aux) ? "remote RX" : 843 "virtual dpcd", 844 ret); 845 846 if (port->passthrough_aux) { 847 ret = drm_dp_dpcd_write(port->passthrough_aux, 848 DP_DSC_ENABLE, 849 &enable_passthrough, 1); 850 drm_dbg_dp(dev, 851 "Sent DSC pass-through disable to virtual dpcd port, ret = %u\n", 852 ret); 853 } 854 } 855 } 856 857 if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT || stream->signal == SIGNAL_TYPE_EDP) { 858 if (stream->sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_NONE) { 859 ret = dm_helpers_dp_write_dpcd(ctx, stream->link, DP_DSC_ENABLE, &enable_dsc, 1); 860 drm_dbg_dp(dev, 861 "Send DSC %s to SST RX\n", 862 enable_dsc ? "enable" : "disable"); 863 } else if (stream->sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER) { 864 ret = dm_helpers_dp_write_dpcd(ctx, stream->link, DP_DSC_ENABLE, &enable_dsc, 1); 865 drm_dbg_dp(dev, 866 "Send DSC %s to DP-HDMI PCON\n", 867 enable_dsc ? "enable" : "disable"); 868 } 869 } 870 871 return ret; 872 } 873 874 bool dm_helpers_is_dp_sink_present(struct dc_link *link) 875 { 876 bool dp_sink_present; 877 struct amdgpu_dm_connector *aconnector = link->priv; 878 879 if (!aconnector) { 880 BUG_ON("Failed to find connector for link!"); 881 return true; 882 } 883 884 mutex_lock(&aconnector->dm_dp_aux.aux.hw_mutex); 885 dp_sink_present = dc_link_is_dp_sink_present(link); 886 mutex_unlock(&aconnector->dm_dp_aux.aux.hw_mutex); 887 return dp_sink_present; 888 } 889 890 enum dc_edid_status dm_helpers_read_local_edid( 891 struct dc_context *ctx, 892 struct dc_link *link, 893 struct dc_sink *sink) 894 { 895 struct amdgpu_dm_connector *aconnector = link->priv; 896 struct drm_connector *connector = &aconnector->base; 897 struct i2c_adapter *ddc; 898 int retry = 3; 899 enum dc_edid_status edid_status; 900 struct edid *edid; 901 902 if (link->aux_mode) 903 ddc = &aconnector->dm_dp_aux.aux.ddc; 904 else 905 ddc = &aconnector->i2c->base; 906 907 /* some dongles read edid incorrectly the first time, 908 * do check sum and retry to make sure read correct edid. 909 */ 910 do { 911 912 edid = drm_get_edid(&aconnector->base, ddc); 913 914 /* DP Compliance Test 4.2.2.6 */ 915 if (link->aux_mode && connector->edid_corrupt) 916 drm_dp_send_real_edid_checksum(&aconnector->dm_dp_aux.aux, connector->real_edid_checksum); 917 918 if (!edid && connector->edid_corrupt) { 919 connector->edid_corrupt = false; 920 return EDID_BAD_CHECKSUM; 921 } 922 923 if (!edid) 924 return EDID_NO_RESPONSE; 925 926 sink->dc_edid.length = EDID_LENGTH * (edid->extensions + 1); 927 memmove(sink->dc_edid.raw_edid, (uint8_t *)edid, sink->dc_edid.length); 928 929 /* We don't need the original edid anymore */ 930 kfree(edid); 931 932 edid_status = dm_helpers_parse_edid_caps( 933 link, 934 &sink->dc_edid, 935 &sink->edid_caps); 936 937 } while (edid_status == EDID_BAD_CHECKSUM && --retry > 0); 938 939 if (edid_status != EDID_OK) 940 DRM_ERROR("EDID err: %d, on connector: %s", 941 edid_status, 942 aconnector->base.name); 943 if (link->aux_mode) { 944 union test_request test_request = {0}; 945 union test_response test_response = {0}; 946 947 dm_helpers_dp_read_dpcd(ctx, 948 link, 949 DP_TEST_REQUEST, 950 &test_request.raw, 951 sizeof(union test_request)); 952 953 if (!test_request.bits.EDID_READ) 954 return edid_status; 955 956 test_response.bits.EDID_CHECKSUM_WRITE = 1; 957 958 dm_helpers_dp_write_dpcd(ctx, 959 link, 960 DP_TEST_EDID_CHECKSUM, 961 &sink->dc_edid.raw_edid[sink->dc_edid.length-1], 962 1); 963 964 dm_helpers_dp_write_dpcd(ctx, 965 link, 966 DP_TEST_RESPONSE, 967 &test_response.raw, 968 sizeof(test_response)); 969 970 } 971 972 return edid_status; 973 } 974 int dm_helper_dmub_aux_transfer_sync( 975 struct dc_context *ctx, 976 const struct dc_link *link, 977 struct aux_payload *payload, 978 enum aux_return_code_type *operation_result) 979 { 980 if (!link->hpd_status) { 981 *operation_result = AUX_RET_ERROR_HPD_DISCON; 982 return -1; 983 } 984 985 return amdgpu_dm_process_dmub_aux_transfer_sync(ctx, link->link_index, payload, 986 operation_result); 987 } 988 989 int dm_helpers_dmub_set_config_sync(struct dc_context *ctx, 990 const struct dc_link *link, 991 struct set_config_cmd_payload *payload, 992 enum set_config_status *operation_result) 993 { 994 return amdgpu_dm_process_dmub_set_config_sync(ctx, link->link_index, payload, 995 operation_result); 996 } 997 998 void dm_set_dcn_clocks(struct dc_context *ctx, struct dc_clocks *clks) 999 { 1000 /* TODO: something */ 1001 } 1002 1003 void dm_helpers_smu_timeout(struct dc_context *ctx, unsigned int msg_id, unsigned int param, unsigned int timeout_us) 1004 { 1005 // TODO: 1006 //amdgpu_device_gpu_recover(dc_context->driver-context, NULL); 1007 } 1008 1009 void dm_helpers_init_panel_settings( 1010 struct dc_context *ctx, 1011 struct dc_panel_config *panel_config, 1012 struct dc_sink *sink) 1013 { 1014 // Extra Panel Power Sequence 1015 panel_config->pps.extra_t3_ms = sink->edid_caps.panel_patch.extra_t3_ms; 1016 panel_config->pps.extra_t7_ms = sink->edid_caps.panel_patch.extra_t7_ms; 1017 panel_config->pps.extra_delay_backlight_off = sink->edid_caps.panel_patch.extra_delay_backlight_off; 1018 panel_config->pps.extra_post_t7_ms = 0; 1019 panel_config->pps.extra_pre_t11_ms = 0; 1020 panel_config->pps.extra_t12_ms = sink->edid_caps.panel_patch.extra_t12_ms; 1021 panel_config->pps.extra_post_OUI_ms = 0; 1022 // Feature DSC 1023 panel_config->dsc.disable_dsc_edp = false; 1024 panel_config->dsc.force_dsc_edp_policy = 0; 1025 } 1026 1027 void dm_helpers_override_panel_settings( 1028 struct dc_context *ctx, 1029 struct dc_panel_config *panel_config) 1030 { 1031 // Feature DSC 1032 if (amdgpu_dc_debug_mask & DC_DISABLE_DSC) 1033 panel_config->dsc.disable_dsc_edp = true; 1034 } 1035 1036 void *dm_helpers_allocate_gpu_mem( 1037 struct dc_context *ctx, 1038 enum dc_gpu_mem_alloc_type type, 1039 size_t size, 1040 long long *addr) 1041 { 1042 struct amdgpu_device *adev = ctx->driver_context; 1043 1044 return dm_allocate_gpu_mem(adev, type, size, addr); 1045 } 1046 1047 void dm_helpers_free_gpu_mem( 1048 struct dc_context *ctx, 1049 enum dc_gpu_mem_alloc_type type, 1050 void *pvMem) 1051 { 1052 struct amdgpu_device *adev = ctx->driver_context; 1053 struct dal_allocation *da; 1054 1055 /* walk the da list in DM */ 1056 list_for_each_entry(da, &adev->dm.da_list, list) { 1057 if (pvMem == da->cpu_ptr) { 1058 amdgpu_bo_free_kernel(&da->bo, &da->gpu_addr, &da->cpu_ptr); 1059 list_del(&da->list); 1060 kfree(da); 1061 break; 1062 } 1063 } 1064 } 1065 1066 bool dm_helpers_dmub_outbox_interrupt_control(struct dc_context *ctx, bool enable) 1067 { 1068 enum dc_irq_source irq_source; 1069 bool ret; 1070 1071 irq_source = DC_IRQ_SOURCE_DMCUB_OUTBOX; 1072 1073 ret = dc_interrupt_set(ctx->dc, irq_source, enable); 1074 1075 DRM_DEBUG_DRIVER("Dmub trace irq %sabling: r=%d\n", 1076 enable ? "en" : "dis", ret); 1077 return ret; 1078 } 1079 1080 void dm_helpers_mst_enable_stream_features(const struct dc_stream_state *stream) 1081 { 1082 /* TODO: virtual DPCD */ 1083 struct dc_link *link = stream->link; 1084 union down_spread_ctrl old_downspread; 1085 union down_spread_ctrl new_downspread; 1086 1087 if (link->aux_access_disabled) 1088 return; 1089 1090 if (!dm_helpers_dp_read_dpcd(link->ctx, link, DP_DOWNSPREAD_CTRL, 1091 &old_downspread.raw, 1092 sizeof(old_downspread))) 1093 return; 1094 1095 new_downspread.raw = old_downspread.raw; 1096 new_downspread.bits.IGNORE_MSA_TIMING_PARAM = 1097 (stream->ignore_msa_timing_param) ? 1 : 0; 1098 1099 if (new_downspread.raw != old_downspread.raw) 1100 dm_helpers_dp_write_dpcd(link->ctx, link, DP_DOWNSPREAD_CTRL, 1101 &new_downspread.raw, 1102 sizeof(new_downspread)); 1103 } 1104 1105 bool dm_helpers_dp_handle_test_pattern_request( 1106 struct dc_context *ctx, 1107 const struct dc_link *link, 1108 union link_test_pattern dpcd_test_pattern, 1109 union test_misc dpcd_test_params) 1110 { 1111 enum dp_test_pattern test_pattern; 1112 enum dp_test_pattern_color_space test_pattern_color_space = 1113 DP_TEST_PATTERN_COLOR_SPACE_UNDEFINED; 1114 enum dc_color_depth requestColorDepth = COLOR_DEPTH_UNDEFINED; 1115 enum dc_pixel_encoding requestPixelEncoding = PIXEL_ENCODING_UNDEFINED; 1116 struct pipe_ctx *pipes = link->dc->current_state->res_ctx.pipe_ctx; 1117 struct pipe_ctx *pipe_ctx = NULL; 1118 struct amdgpu_dm_connector *aconnector = link->priv; 1119 struct drm_device *dev = aconnector->base.dev; 1120 int i; 1121 1122 for (i = 0; i < MAX_PIPES; i++) { 1123 if (pipes[i].stream == NULL) 1124 continue; 1125 1126 if (pipes[i].stream->link == link && !pipes[i].top_pipe && 1127 !pipes[i].prev_odm_pipe) { 1128 pipe_ctx = &pipes[i]; 1129 break; 1130 } 1131 } 1132 1133 if (pipe_ctx == NULL) 1134 return false; 1135 1136 switch (dpcd_test_pattern.bits.PATTERN) { 1137 case LINK_TEST_PATTERN_COLOR_RAMP: 1138 test_pattern = DP_TEST_PATTERN_COLOR_RAMP; 1139 break; 1140 case LINK_TEST_PATTERN_VERTICAL_BARS: 1141 test_pattern = DP_TEST_PATTERN_VERTICAL_BARS; 1142 break; /* black and white */ 1143 case LINK_TEST_PATTERN_COLOR_SQUARES: 1144 test_pattern = (dpcd_test_params.bits.DYN_RANGE == 1145 TEST_DYN_RANGE_VESA ? 1146 DP_TEST_PATTERN_COLOR_SQUARES : 1147 DP_TEST_PATTERN_COLOR_SQUARES_CEA); 1148 break; 1149 default: 1150 test_pattern = DP_TEST_PATTERN_VIDEO_MODE; 1151 break; 1152 } 1153 1154 if (dpcd_test_params.bits.CLR_FORMAT == 0) 1155 test_pattern_color_space = DP_TEST_PATTERN_COLOR_SPACE_RGB; 1156 else 1157 test_pattern_color_space = dpcd_test_params.bits.YCBCR_COEFS ? 1158 DP_TEST_PATTERN_COLOR_SPACE_YCBCR709 : 1159 DP_TEST_PATTERN_COLOR_SPACE_YCBCR601; 1160 1161 switch (dpcd_test_params.bits.BPC) { 1162 case 0: // 6 bits 1163 requestColorDepth = COLOR_DEPTH_666; 1164 break; 1165 case 1: // 8 bits 1166 requestColorDepth = COLOR_DEPTH_888; 1167 break; 1168 case 2: // 10 bits 1169 requestColorDepth = COLOR_DEPTH_101010; 1170 break; 1171 case 3: // 12 bits 1172 requestColorDepth = COLOR_DEPTH_121212; 1173 break; 1174 default: 1175 break; 1176 } 1177 1178 switch (dpcd_test_params.bits.CLR_FORMAT) { 1179 case 0: 1180 requestPixelEncoding = PIXEL_ENCODING_RGB; 1181 break; 1182 case 1: 1183 requestPixelEncoding = PIXEL_ENCODING_YCBCR422; 1184 break; 1185 case 2: 1186 requestPixelEncoding = PIXEL_ENCODING_YCBCR444; 1187 break; 1188 default: 1189 requestPixelEncoding = PIXEL_ENCODING_RGB; 1190 break; 1191 } 1192 1193 if ((requestColorDepth != COLOR_DEPTH_UNDEFINED 1194 && pipe_ctx->stream->timing.display_color_depth != requestColorDepth) 1195 || (requestPixelEncoding != PIXEL_ENCODING_UNDEFINED 1196 && pipe_ctx->stream->timing.pixel_encoding != requestPixelEncoding)) { 1197 drm_dbg(dev, 1198 "original bpc %d pix encoding %d, changing to %d %d\n", 1199 pipe_ctx->stream->timing.display_color_depth, 1200 pipe_ctx->stream->timing.pixel_encoding, 1201 requestColorDepth, 1202 requestPixelEncoding); 1203 pipe_ctx->stream->timing.display_color_depth = requestColorDepth; 1204 pipe_ctx->stream->timing.pixel_encoding = requestPixelEncoding; 1205 1206 dc_link_update_dsc_config(pipe_ctx); 1207 1208 aconnector->timing_changed = true; 1209 /* store current timing */ 1210 if (aconnector->timing_requested) 1211 *aconnector->timing_requested = pipe_ctx->stream->timing; 1212 else 1213 drm_err(dev, "timing storage failed\n"); 1214 1215 } 1216 1217 pipe_ctx->stream->test_pattern.type = test_pattern; 1218 pipe_ctx->stream->test_pattern.color_space = test_pattern_color_space; 1219 1220 dc_link_dp_set_test_pattern( 1221 (struct dc_link *) link, 1222 test_pattern, 1223 test_pattern_color_space, 1224 NULL, 1225 NULL, 1226 0); 1227 1228 return false; 1229 } 1230 1231 void dm_set_phyd32clk(struct dc_context *ctx, int freq_khz) 1232 { 1233 // TODO 1234 } 1235 1236 void dm_helpers_enable_periodic_detection(struct dc_context *ctx, bool enable) 1237 { 1238 struct amdgpu_device *adev = ctx->driver_context; 1239 1240 if (adev->dm.idle_workqueue) { 1241 adev->dm.idle_workqueue->enable = enable; 1242 if (enable && !adev->dm.idle_workqueue->running && amdgpu_dm_is_headless(adev)) 1243 schedule_work(&adev->dm.idle_workqueue->work); 1244 } 1245 } 1246 1247 void dm_helpers_dp_mst_update_branch_bandwidth( 1248 struct dc_context *ctx, 1249 struct dc_link *link) 1250 { 1251 // TODO 1252 } 1253 1254 static bool dm_is_freesync_pcon_whitelist(const uint32_t branch_dev_id) 1255 { 1256 bool ret_val = false; 1257 1258 switch (branch_dev_id) { 1259 case DP_BRANCH_DEVICE_ID_0060AD: 1260 case DP_BRANCH_DEVICE_ID_00E04C: 1261 case DP_BRANCH_DEVICE_ID_90CC24: 1262 ret_val = true; 1263 break; 1264 default: 1265 break; 1266 } 1267 1268 return ret_val; 1269 } 1270 1271 enum adaptive_sync_type dm_get_adaptive_sync_support_type(struct dc_link *link) 1272 { 1273 struct dpcd_caps *dpcd_caps = &link->dpcd_caps; 1274 enum adaptive_sync_type as_type = ADAPTIVE_SYNC_TYPE_NONE; 1275 1276 switch (dpcd_caps->dongle_type) { 1277 case DISPLAY_DONGLE_DP_HDMI_CONVERTER: 1278 if (dpcd_caps->adaptive_sync_caps.dp_adap_sync_caps.bits.ADAPTIVE_SYNC_SDP_SUPPORT == true && 1279 dpcd_caps->allow_invalid_MSA_timing_param == true && 1280 dm_is_freesync_pcon_whitelist(dpcd_caps->branch_dev_id)) 1281 as_type = FREESYNC_TYPE_PCON_IN_WHITELIST; 1282 break; 1283 default: 1284 break; 1285 } 1286 1287 return as_type; 1288 } 1289