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/linux/Documentation/devicetree/bindings/interconnect/
H A Dsamsung,exynos-bus.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/interconnect/samsung,exynos-bus.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung Exynos SoC Bus and Interconnect
10 - Chanwoo Choi <cw00.choi@samsung.com>
11 - Krzysztof Kozlowski <krzk@kernel.org>
15 sub-blocks in SoC. Most Exynos SoCs share the common architecture for buses.
16 Generally, each bus of Exynos SoC includes a source clock and a power line,
17 which are able to change the clock frequency of the bus in runtime. To
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/linux/Documentation/admin-guide/perf/
H A Dthunderx2-pmu.rst5 The ThunderX2 SoC PMU consists of independent, system-wide, per-socket
6 PMUs such as the Level 3 Cache (L3C), DDR4 Memory Controller (DMC) and
9 The DMC has 8 interleaved channels and the L3C has 16 interleaved tiles.
13 The DMC and L3C support up to 4 counters, while the CCPI2 supports up to 8
16 overflow interrupt. DMC and L3C counters are 32-bit and read every 2 seconds.
17 The CCPI2 counters are 64-bit and assumed not to overflow in normal operation.
21 The thunderx2_pmu driver registers per-socket perf PMUs for the DMC and
22 L3C devices. Each PMU can be used to count up to 4 (DMC/L3C) or up to 8
25 /sys/bus/event_source/devices/uncore_<l3c_S/dmc_S/ccpi2_S/>; S is the socket id.
28 work. Per-task perf sessions are also not supported.
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/linux/Documentation/devicetree/bindings/memory-controllers/
H A Drockchip,rk3399-dmc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/rockchip,rk3399-dmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip rk3399 DMC (Dynamic Memory Controller) device
10 - Brian Norris <briannorris@chromium.org>
15 - rockchip,rk3399-dmc
17 devfreq-events:
26 clock-names:
28 - const: dmc_clk
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/linux/drivers/devfreq/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
20 to a device by 1-to-1. The device registering devfreq takes the
39 Simple-Ondemand should be able to provide busy/total counter
79 tristate "ARM Exynos Generic Memory Bus DEVFREQ Driver"
86 This adds the common DEVFREQ driver for Exynos Memory bus. Exynos
87 Memory bus has one more group of memory bus (e.g, MIF and INT block).
88 Each memory bus group could contain many memoby bus block. It reads
89 PPMU counters of memory controllers by using DEVFREQ-event device
94 tristate "i.MX Generic Bus DEVFREQ Driver"
133 tristate "ARM RK3399 DMC DEVFREQ Driver"
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/linux/drivers/pmdomain/amlogic/
H A Dmeson-secure-pwrc.c1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
13 #include <dt-bindings/power/meson-a1-power.h>
14 #include <dt-bindings/power/amlogic,c3-pwrc.h>
15 #include <dt-bindings/power/meson-s4-power.h>
16 #include <dt-bindings/power/amlogic,t7-pwrc.h>
17 #include <dt-bindings/power/amlogic,a4-pwrc.h>
18 #include <dt-bindings/power/amlogic,a5-pwrc.h>
19 #include <linux/arm-smccc.h>
57 if (meson_sm_call(pwrc_domain->pwrc->fw, SM_A1_PWRC_GET, &is_off, in pwrc_secure_is_off()
58 pwrc_domain->index, 0, 0, 0, 0) < 0) in pwrc_secure_is_off()
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/linux/drivers/cpufreq/
H A Ds5pv210-cpufreq.c1 // SPDX-License-Identifier: GPL-2.0-only
194 * ch: DMC port number 0 or 1
207 pr_err("Cannot find DMC port\n"); in s5pv210_set_refresh()
238 ret = -EINVAL; in s5pv210_target()
242 old_freq = policy->cur; in s5pv210_target()
267 /* Check if there need to change System bus clock */ in s5pv210_target()
287 * APLL -> MPLL(for stable transition) -> APLL in s5pv210_target()
294 * SCLKA2M(200/1=200)->(200/4=50)Mhz in s5pv210_target()
309 * (200/4=50)->(667/4=166)Mhz in s5pv210_target()
329 /* 4. SCLKAPLL -> SCLKMPLL */ in s5pv210_target()
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/linux/drivers/edac/
H A Ddmc520_edac.c1 // SPDX-License-Identifier: GPL-2.0
4 * EDAC driver for DMC-520 memory controller.
25 /* DMC-520 registers */
43 /* DMC-520 types, masks and bitfields */
78 * The max-length message would be: "rank:7 bank:15 row:262143 col:1023".
79 * Max length is 34. Using a 40-size buffer is enough.
82 #define EDAC_MOD_NAME "dmc520-edac"
85 /* the data bus width for the attached memory chips. */
165 * error_lock is to protect concurrent writes to the mci->error_desc through
180 return readl(pvt->reg_base + offset); in dmc520_read_reg()
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/linux/arch/arm/boot/dts/samsung/
H A Ds5pv210.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (c) 2013-2014 Samsung Electronics, Co. Ltd.
19 #include <dt-bindings/clock/s5pv210.h>
20 #include <dt-bindings/clock/s5pv210-audss.h>
23 #address-cells = <1>;
24 #size-cells = <1>;
45 #address-cells = <1>;
46 #size-cells = <0>;
50 compatible = "arm,cortex-a8";
55 xxti: oscillator-0 {
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H A Dexynos3250.dtsi1 // SPDX-License-Identifier: GPL-2.0
17 #include "exynos4-cpu-thermal.dtsi"
18 #include <dt-bindings/clock/exynos3250.h>
19 #include <dt-bindings/interrupt-controller/arm-gic.h>
20 #include <dt-bindings/interrupt-controller/irq.h>
24 interrupt-parent = <&gic>;
25 #address-cells = <1>;
26 #size-cells = <1>;
46 bus_dmc: bus-dmc {
47 compatible = "samsung,exynos-bus";
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H A Dexynos4210.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
7 * Copyright (c) 2010-2011 Linaro Ltd.
20 #include "exynos4-cpu-thermal.dtsi"
31 bus_acp: bus-acp {
32 compatible = "samsung,exynos-bus";
34 clock-names = "bus";
35 operating-points-v2 = <&bus_acp_opp_table>;
38 bus_acp_opp_table: opp-table {
39 compatible = "operating-points-v2";
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H A Dexynos5420.dtsi1 // SPDX-License-Identifier: GPL-2.0
14 #include <dt-bindings/clock/exynos5420.h>
15 #include <dt-bindings/clock/exynos-audss-clk.h>
16 #include <dt-bindings/interrupt-controller/arm-gic.h>
37 bus_disp1: bus-disp1 {
38 compatible = "samsung,exynos-bus";
40 clock-names = "bus";
44 bus_disp1_fimd: bus-disp1-fimd {
45 compatible = "samsung,exynos-bus";
47 clock-names = "bus";
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H A Dexynos4x12.dtsi1 // SPDX-License-Identifier: GPL-2.0
19 #include "exynos4-cpu-thermal.dtsi"
27 fimc-lite0 = &fimc_lite_0;
28 fimc-lite1 = &fimc_lite_1;
31 bus_acp: bus-acp {
32 compatible = "samsung,exynos-bus";
34 clock-names = "bus";
35 operating-points-v2 = <&bus_acp_opp_table>;
38 bus_acp_opp_table: opp-table {
39 compatible = "operating-points-v2";
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H A Dexynos5422-odroid-core.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Hardkernel Odroid XU3/XU3-Lite/XU4/HC1 boards core device tree source
6 * Copyright (c) 2013-2017 Samsung Electronics Co., Ltd.
10 #include <dt-bindings/clock/samsung,s2mps11.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/gpio/gpio.h>
14 #include "exynos5422-cpus.dtsi"
27 stdout-path = "serial2:115200n8";
31 compatible = "samsung,secure-firmware";
35 fixed-rate-clocks {
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/linux/drivers/net/ethernet/sun/
H A Dniu.h1 /* SPDX-License-Identifier: GPL-2.0 */
19 #define DMC 0x600000UL macro
130 /* XMAC registers, offset from np->mac_regs */
415 /* BMAC registers, offset from np->mac_regs */
591 /* XPCS registers, offset from np->regs + np->xpcs_off */
688 /* PCS registers, offset from np->regs + np->pcs_off */
1201 #define TCAM_KEY_0_KEY 0x00000000000000ffULL /* bits 192-199 */
1204 #define TCAM_KEY_1_KEY 0xffffffffffffffffULL /* bits 128-191 */
1207 #define TCAM_KEY_2_KEY 0xffffffffffffffffULL /* bits 64-127 */
1210 #define TCAM_KEY_3_KEY 0xffffffffffffffffULL /* bits 0-63 */
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/linux/drivers/gpu/drm/i915/display/
H A Dintel_display_core.h1 /* SPDX-License-Identifier: MIT */
65 * fills out the pipe-config with the hw state.
195 * if we get a HPD irq from DP and a HPD irq from non-DP
196 * the non-DP HPD could block the workqueue on a mode config
199 * blocked behind the non-DP one.
277 * protects * intel_crtc->wm.active and
278 * crtc_state->wm.need_postvbl_update.
291 /* Top level crtc-ish functions */
376 struct intel_dmc *dmc; member
378 } dmc; member
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H A Dintel_cdclk.c2 * Copyright © 2006-2017 Intel Corporation
68 * On SKL+ the DMC will toggle the CDCLK off/on during DC5/6 entry/exit.
69 * DMC will not change the active CDCLK frequency however, so that part
75 * - We have the CDCLK PLL, which generates an output clock based on a
77 * - The CD2X Divider, which divides the output of the PLL based on a
78 * divisor selected from a set of pre-defined choices.
79 * - The CD2X Squasher, which further divides the output based on a
82 * - And, finally, a fixed divider that divides the output frequency by 2.
101 * - Full PLL disable + re-enable with new VCO frequency. Pipes must be inactive.
102 * - CD2X divider update. Single pipe can be active as the divider update
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/linux/drivers/input/touchscreen/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
20 support for the built-in touchscreen.
25 module will be called 88pm860x-ts.
34 and your board-specific setup code includes that in its
51 AD7877 controller, and your board-specific initialization
60 tristate "Analog Devices AD7879-1/AD7889-1 touchscreen interface"
63 the AD7879-1/AD7889-1 controller.
65 You should select a bus connection too.
71 tristate "support I2C bus connection"
75 Say Y here if you have AD7879-1/AD7889-1 hooked to an I2C bus.
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/linux/drivers/scsi/
H A Dscsi_devinfo.c1 // SPDX-License-Identifier: GPL-2.0
43 * from the default, includes black-listed (broken) devices. The entries here
61 {"CHINON", "CD-ROM CDS-431", "H42", BLIST_NOLUN}, /* locks up */
62 {"CHINON", "CD-ROM CDS-535", "Q14", BLIST_NOLUN}, /* locks up */
63 {"DENON", "DRD-25X", "V", BLIST_NOLUN}, /* locks up */
66 {"IBM", "2104-DU3", NULL, BLIST_NOLUN}, /* locks up */
67 {"IBM", "2104-TU3", NULL, BLIST_NOLUN}, /* locks up */
69 {"MAXTOR", "XT-3280", "PR02", BLIST_NOLUN}, /* locks up */
70 {"MAXTOR", "XT-4380S", "B3C", BLIST_NOLUN}, /* locks up */
71 {"MAXTOR", "MXT-1240S", "I1.2", BLIST_NOLUN}, /* locks up */
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/linux/drivers/clk/meson/
H A Da1-peripherals.c1 // SPDX-License-Identifier: GPL-2.0+
10 #include <linux/clk-provider.h>
13 #include "a1-peripherals.h"
14 #include "clk-dualdiv.h"
15 #include "clk-regmap.h"
16 #include "meson-clkc-utils.h"
18 #include <dt-bindings/clock/amlogic,a1-peripherals-clkc.h>
360 * This clock is used by APB bus which is set in boot ROM code
365 * b) CCF has a clock hand-off mechanism to make the sure the
1168 * ---------| |---DIV--| | | | spicc out
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/linux/arch/arm64/boot/dts/rockchip/
H A Drk3399-gru-scarlet.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Google Gru-scarlet board device tree source
8 #include "rk3399-gru.dtsi"
11 chassis-type = "tablet";
16 pp1250_s3: pp1250-s3 {
17 compatible = "regulator-fixed";
18 regulator-name = "pp1250_s3";
21 regulator-always-on;
22 regulator-boot-on;
23 regulator-min-microvolt = <1250000>;
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H A Drk3399-gru.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 * Copyright 2016-2017 Google, Inc
8 #include <dt-bindings/input/input.h>
9 #include "rk3399-op1.dtsi"
18 stdout-path = "serial2:115200n8";
27 * - Rails that only connect to the EC (or devices that the EC talks to)
29 * - Rails _are_ included if the rails go to the AP even if the AP
38 * - The EC controls the enable and the EC always enables a rail as
40 * - The rails are actually connected to each other by a jumper and
45 ppvar_sys: ppvar-sys {
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H A Drk3399-base.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/rk3399-cru.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/rk3399-power.h>
12 #include <dt-bindings/thermal/thermal.h>
17 interrupt-parent = <&gic>;
18 #address-cells = <2>;
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/linux/arch/arm64/boot/dts/amlogic/
H A Dmeson-g12-common.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/phy/phy.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/clock/g12a-clkc.h>
9 #include <dt-bindings/clock/g12a-aoclkc.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/interrupt-controller/amlogic,meson-g12a-gpio-intc.h>
13 #include <dt-bindings/reset/amlogic,meson-g12a-reset.h>
14 #include <dt-bindings/thermal/thermal.h>
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/linux/drivers/pmdomain/rockchip/
H A Dpm-domains.c1 // SPDX-License-Identifier: GPL-2.0-only
23 #include <dt-bindings/power/px30-power.h>
24 #include <dt-bindings/power/rockchip,rv1126-power.h>
25 #include <dt-bindings/power/rk3036-power.h>
26 #include <dt-bindings/power/rk3066-power.h>
27 #include <dt-bindings/power/rk3128-power.h>
28 #include <dt-bindings/power/rk3188-power.h>
29 #include <dt-bindings/power/rk3228-power.h>
30 #include <dt-bindings/power/rk3288-power.h>
31 #include <dt-bindings/power/rk3328-power.h>
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/linux/drivers/usb/storage/
H A Dunusual_devs.h1 /* SPDX-License-Identifier: GPL-2.0+ */
7 * (c) 2000-2002 Matthew Dharm (mdharm-usb@one-eyed-alien.net)
26 * - a patch that adds the entry for your device, including your
29 * - a copy of /sys/kernel/debug/usb/devices with your device plugged in
31 * Send your submission to the USB development list <linux-usb@vger.kernel.org>
42 * In-kernel mode switching is deprecated. Do not add new devices to
71 "CD-Writer+",
74 /* Reported by Ben Efros <ben@pc-doctor.com> */
82 * Reported by Grant Grundler <grundler@parisc-linux.org>
107 /* Patch submitted by Mihnea-Costin Grigore <mihnea@zulu.ro> */
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