Lines Matching +full:bus +full:- +full:dmc
1 /* SPDX-License-Identifier: GPL-2.0 */
19 #define DMC 0x600000UL macro
130 /* XMAC registers, offset from np->mac_regs */
415 /* BMAC registers, offset from np->mac_regs */
591 /* XPCS registers, offset from np->regs + np->xpcs_off */
688 /* PCS registers, offset from np->regs + np->pcs_off */
1201 #define TCAM_KEY_0_KEY 0x00000000000000ffULL /* bits 192-199 */
1204 #define TCAM_KEY_1_KEY 0xffffffffffffffffULL /* bits 128-191 */
1207 #define TCAM_KEY_2_KEY 0xffffffffffffffffULL /* bits 64-127 */
1210 #define TCAM_KEY_3_KEY 0xffffffffffffffffULL /* bits 0-63 */
1213 #define TCAM_KEY_MASK_0_KEY_SEL 0x00000000000000ffULL /* bits 192-199 */
1216 #define TCAM_KEY_MASK_1_KEY_SEL 0xffffffffffffffffULL /* bits 128-191 */
1219 #define TCAM_KEY_MASK_2_KEY_SEL 0xffffffffffffffffULL /* bits 64-127 */
1222 #define TCAM_KEY_MASK_3_KEY_SEL 0xffffffffffffffffULL /* bits 0-63 */
1322 #define TCAM_ETHKEY1_FRAME_BYTE0_7(NUM) (0xff << ((7 - NUM) * 8))
1426 /* FCRAM hash table entries are up to 8 64-bit words in size.
1437 /* Generic HASH entry header, used for all non-optimized formats. */
1978 #define RXDMA_CFIG1(IDX) (DMC + 0x00000UL + (IDX) * 0x200UL)
1984 #define RXDMA_CFIG2(IDX) (DMC + 0x00008UL + (IDX) * 0x200UL)
1990 #define RBR_CFIG_A(IDX) (DMC + 0x00010UL + (IDX) * 0x200UL)
1996 #define RBR_CFIG_B(IDX) (DMC + 0x00018UL + (IDX) * 0x200UL)
2026 #define RBR_KICK(IDX) (DMC + 0x00020UL + (IDX) * 0x200UL)
2029 #define RBR_STAT(IDX) (DMC + 0x00028UL + (IDX) * 0x200UL)
2032 #define RBR_HDH(IDX) (DMC + 0x00030UL + (IDX) * 0x200UL)
2035 #define RBR_HDL(IDX) (DMC + 0x00038UL + (IDX) * 0x200UL)
2038 #define RCRCFIG_A(IDX) (DMC + 0x00040UL + (IDX) * 0x200UL)
2044 #define RCRCFIG_B(IDX) (DMC + 0x00048UL + (IDX) * 0x200UL)
2051 #define RCRSTAT_A(IDX) (DMC + 0x00050UL + (IDX) * 0x200UL)
2054 #define RCRSTAT_B(IDX) (DMC + 0x00058UL + (IDX) * 0x200UL)
2057 #define RCRSTAT_C(IDX) (DMC + 0x00060UL + (IDX) * 0x200UL)
2060 #define RX_DMA_CTL_STAT(IDX) (DMC + 0x00070UL + (IDX) * 0x200UL)
2113 #define RCR_FLSH(IDX) (DMC + 0x00078UL + (IDX) * 0x200UL)
2116 #define RXMISC(IDX) (DMC + 0x00090UL + (IDX) * 0x200UL)
2120 #define RX_DMA_CTL_STAT_DBG(IDX) (DMC + 0x00098UL + (IDX) * 0x200UL)
2146 #define RX_DMA_ENT_MSK(IDX) (DMC + 0x00068UL + (IDX) * 0x200UL)
2170 #define TX_RNG_CFIG(IDX) (DMC + 0x40000UL + (IDX) * 0x200UL)
2176 #define TX_RING_HDL(IDX) (DMC + 0x40010UL + (IDX) * 0x200UL)
2181 #define TX_RING_KICK(IDX) (DMC + 0x40018UL + (IDX) * 0x200UL)
2185 #define TX_ENT_MSK(IDX) (DMC + 0x40020UL + (IDX) * 0x200UL)
2196 #define TX_CS(IDX) (DMC + 0x40028UL + (IDX)*0x200UL)
2217 #define TXDMA_MBH(IDX) (DMC + 0x40030UL + (IDX) * 0x200UL)
2220 #define TXDMA_MBL(IDX) (DMC + 0x40038UL + (IDX) * 0x200UL)
2223 #define TX_DMA_PRE_ST(IDX) (DMC + 0x40040UL + (IDX) * 0x200UL)
2226 #define TX_RNG_ERR_LOGH(IDX) (DMC + 0x40048UL + (IDX) * 0x200UL)
2232 #define TX_RNG_ERR_LOGL(IDX) (DMC + 0x40050UL + (IDX) * 0x200UL)
2235 #define TDMC_INTR_DBG(IDX) (DMC + 0x40060UL + (IDX) * 0x200UL)
2246 #define TX_CS_DBG(IDX) (DMC + 0x40068UL + (IDX) * 0x200UL)
2249 #define TDMC_INJ_PAR_ERR(IDX) (DMC + 0x45040UL + (IDX) * 0x200UL)
2252 #define TDMC_DBG_SEL(IDX) (DMC + 0x45080UL + (IDX) * 0x200UL)
2255 #define TDMC_TRAINING_VECTOR(IDX) (DMC + 0x45088UL + (IDX) * 0x200UL)
2880 (((index) + 1) < (tp)->pending ? ((index) + 1) : 0)
2884 return (tp->pending - in niu_tx_avail()
2885 ((tp->prod - tp->cons) & (MAX_TX_RING_SIZE - 1))); in niu_tx_avail()
2947 (((index) + 1) < (rp)->rcr_table_size ? ((index) + 1) : 0)
2949 (((index) + 1) < (rp)->rbr_table_size ? ((index) + 1) : 0)
2959 #define NIU_QGC_LP_BM_STR "501-7606"
2960 #define NIU_2XGF_LP_BM_STR "501-7283"
2961 #define NIU_QGC_PEM_BM_STR "501-7765"
2962 #define NIU_2XGF_PEM_BM_STR "501-7626"
2963 #define NIU_ALONSO_BM_STR "373-0202"
2964 #define NIU_FOXXY_BM_STR "501-7961"
2965 #define NIU_2XGF_MRVL_BM_STR "SK-6E82"
2966 #define NIU_QGC_LP_MDL_STR "SUNW,pcie-qgc"
2967 #define NIU_2XGF_LP_MDL_STR "SUNW,pcie-2xgf"
2968 #define NIU_QGC_PEM_MDL_STR "SUNW,pcie-qgc-pem"
2969 #define NIU_2XGF_PEM_MDL_STR "SUNW,pcie-2xgf-pem"
2972 #define NIU_MARAMBA_MDL_STR "SUNW,pcie-neptune"
2973 #define NIU_FOXXY_MDL_STR "SUNW,pcie-rfem"
2974 #define NIU_2XGF_MRVL_MDL_STR "SysKonnect,pcie-2xgf"
3059 int bus; member
3252 #define NIU_FLAGS_MSIX 0x00400000 /* MSI-X in use */