Lines Matching +full:bus +full:- +full:dmc
2 * Copyright © 2006-2017 Intel Corporation
68 * On SKL+ the DMC will toggle the CDCLK off/on during DC5/6 entry/exit.
69 * DMC will not change the active CDCLK frequency however, so that part
75 * - We have the CDCLK PLL, which generates an output clock based on a
77 * - The CD2X Divider, which divides the output of the PLL based on a
78 * divisor selected from a set of pre-defined choices.
79 * - The CD2X Squasher, which further divides the output based on a
82 * - And, finally, a fixed divider that divides the output frequency by 2.
101 * - Full PLL disable + re-enable with new VCO frequency. Pipes must be inactive.
102 * - CD2X divider update. Single pipe can be active as the divider update
104 * - Crawl the PLL smoothly to the new VCO frequency. Pipes can be active.
105 * - Squash waveform update. Pipes can be active.
106 * - Crawl and squash can also be done back to back. Pipes can be active.
127 dev_priv->display.funcs.cdclk->get_cdclk(dev_priv, cdclk_config); in intel_cdclk_get_cdclk()
134 dev_priv->display.funcs.cdclk->set_cdclk(dev_priv, cdclk_config, pipe); in intel_cdclk_set_cdclk()
139 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in intel_cdclk_modeset_calc_cdclk()
141 return dev_priv->display.funcs.cdclk->modeset_calc_cdclk(state); in intel_cdclk_modeset_calc_cdclk()
147 return dev_priv->display.funcs.cdclk->calc_voltage_level(cdclk); in intel_cdclk_calc_voltage_level()
153 cdclk_config->cdclk = 133333; in fixed_133mhz_get_cdclk()
159 cdclk_config->cdclk = 200000; in fixed_200mhz_get_cdclk()
165 cdclk_config->cdclk = 266667; in fixed_266mhz_get_cdclk()
171 cdclk_config->cdclk = 333333; in fixed_333mhz_get_cdclk()
177 cdclk_config->cdclk = 400000; in fixed_400mhz_get_cdclk()
183 cdclk_config->cdclk = 450000; in fixed_450mhz_get_cdclk()
189 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); in i85x_get_cdclk()
197 if (pdev->revision == 0x1) { in i85x_get_cdclk()
198 cdclk_config->cdclk = 133333; in i85x_get_cdclk()
202 pci_bus_read_config_word(pdev->bus, in i85x_get_cdclk()
212 cdclk_config->cdclk = 200000; in i85x_get_cdclk()
215 cdclk_config->cdclk = 250000; in i85x_get_cdclk()
218 cdclk_config->cdclk = 133333; in i85x_get_cdclk()
223 cdclk_config->cdclk = 266667; in i85x_get_cdclk()
231 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); in i915gm_get_cdclk()
237 cdclk_config->cdclk = 133333; in i915gm_get_cdclk()
243 cdclk_config->cdclk = 333333; in i915gm_get_cdclk()
247 cdclk_config->cdclk = 190000; in i915gm_get_cdclk()
255 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); in i945gm_get_cdclk()
261 cdclk_config->cdclk = 133333; in i945gm_get_cdclk()
267 cdclk_config->cdclk = 320000; in i945gm_get_cdclk()
271 cdclk_config->cdclk = 200000; in i945gm_get_cdclk()
338 drm_err(&dev_priv->drm, "Bad HPLL VCO (HPLLVCO=0x%02x)\n", in intel_hpll_vco()
341 drm_dbg_kms(&dev_priv->drm, "HPLL VCO %u kHz\n", vco); in intel_hpll_vco()
349 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); in g33_get_cdclk()
358 cdclk_config->vco = intel_hpll_vco(dev_priv); in g33_get_cdclk()
367 switch (cdclk_config->vco) { in g33_get_cdclk()
384 cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco, in g33_get_cdclk()
389 drm_err(&dev_priv->drm, in g33_get_cdclk()
391 cdclk_config->vco, tmp); in g33_get_cdclk()
392 cdclk_config->cdclk = 190476; in g33_get_cdclk()
398 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); in pnv_get_cdclk()
405 cdclk_config->cdclk = 266667; in pnv_get_cdclk()
408 cdclk_config->cdclk = 333333; in pnv_get_cdclk()
411 cdclk_config->cdclk = 444444; in pnv_get_cdclk()
414 cdclk_config->cdclk = 200000; in pnv_get_cdclk()
417 drm_err(&dev_priv->drm, in pnv_get_cdclk()
421 cdclk_config->cdclk = 133333; in pnv_get_cdclk()
424 cdclk_config->cdclk = 166667; in pnv_get_cdclk()
432 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); in i965gm_get_cdclk()
440 cdclk_config->vco = intel_hpll_vco(dev_priv); in i965gm_get_cdclk()
444 cdclk_sel = ((tmp >> 8) & 0x1f) - 1; in i965gm_get_cdclk()
449 switch (cdclk_config->vco) { in i965gm_get_cdclk()
463 cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco, in i965gm_get_cdclk()
468 drm_err(&dev_priv->drm, in i965gm_get_cdclk()
470 cdclk_config->vco, tmp); in i965gm_get_cdclk()
471 cdclk_config->cdclk = 200000; in i965gm_get_cdclk()
477 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); in gm45_get_cdclk()
481 cdclk_config->vco = intel_hpll_vco(dev_priv); in gm45_get_cdclk()
487 switch (cdclk_config->vco) { in gm45_get_cdclk()
491 cdclk_config->cdclk = cdclk_sel ? 333333 : 222222; in gm45_get_cdclk()
494 cdclk_config->cdclk = cdclk_sel ? 320000 : 228571; in gm45_get_cdclk()
497 drm_err(&dev_priv->drm, in gm45_get_cdclk()
499 cdclk_config->vco, tmp); in gm45_get_cdclk()
500 cdclk_config->cdclk = 222222; in gm45_get_cdclk()
512 cdclk_config->cdclk = 800000; in hsw_get_cdclk()
514 cdclk_config->cdclk = 450000; in hsw_get_cdclk()
516 cdclk_config->cdclk = 450000; in hsw_get_cdclk()
518 cdclk_config->cdclk = 337500; in hsw_get_cdclk()
520 cdclk_config->cdclk = 540000; in hsw_get_cdclk()
525 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? in vlv_calc_cdclk()
558 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1; in vlv_calc_voltage_level()
570 cdclk_config->vco = vlv_get_hpll_vco(dev_priv); in vlv_get_cdclk()
571 cdclk_config->cdclk = vlv_get_cck_clock(dev_priv, "cdclk", in vlv_get_cdclk()
573 cdclk_config->vco); in vlv_get_cdclk()
581 cdclk_config->voltage_level = (val & DSPFREQGUAR_MASK) >> in vlv_get_cdclk()
584 cdclk_config->voltage_level = (val & DSPFREQGUAR_MASK_CHV) >> in vlv_get_cdclk()
597 if (dev_priv->display.cdclk.hw.cdclk >= dev_priv->czclk_freq) { in vlv_program_pfi_credits()
608 * WA - write default credits before re-programming in vlv_program_pfi_credits()
621 drm_WARN_ON(&dev_priv->drm, in vlv_program_pfi_credits()
629 int cdclk = cdclk_config->cdclk; in vlv_set_cdclk()
630 u32 val, cmd = cdclk_config->voltage_level; in vlv_set_cdclk()
665 drm_err(&dev_priv->drm, in vlv_set_cdclk()
672 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, in vlv_set_cdclk()
673 cdclk) - 1; in vlv_set_cdclk()
684 drm_err(&dev_priv->drm, in vlv_set_cdclk()
688 /* adjust self-refresh exit latency value */ in vlv_set_cdclk()
718 int cdclk = cdclk_config->cdclk; in chv_set_cdclk()
719 u32 val, cmd = cdclk_config->voltage_level; in chv_set_cdclk()
749 drm_err(&dev_priv->drm, in chv_set_cdclk()
796 cdclk_config->cdclk = 800000; in bdw_get_cdclk()
798 cdclk_config->cdclk = 450000; in bdw_get_cdclk()
800 cdclk_config->cdclk = 450000; in bdw_get_cdclk()
802 cdclk_config->cdclk = 540000; in bdw_get_cdclk()
804 cdclk_config->cdclk = 337500; in bdw_get_cdclk()
806 cdclk_config->cdclk = 675000; in bdw_get_cdclk()
812 cdclk_config->voltage_level = in bdw_get_cdclk()
813 bdw_calc_voltage_level(cdclk_config->cdclk); in bdw_get_cdclk()
837 int cdclk = cdclk_config->cdclk; in bdw_set_cdclk()
840 if (drm_WARN(&dev_priv->drm, in bdw_set_cdclk()
849 ret = snb_pcode_write(&dev_priv->uncore, BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0); in bdw_set_cdclk()
851 drm_err(&dev_priv->drm, in bdw_set_cdclk()
865 drm_err(&dev_priv->drm, "Switching to FCLK failed\n"); in bdw_set_cdclk()
875 drm_err(&dev_priv->drm, "Switching back to LCPLL failed\n"); in bdw_set_cdclk()
877 snb_pcode_write(&dev_priv->uncore, HSW_PCODE_DE_WRITE_FREQ_REQ, in bdw_set_cdclk()
878 cdclk_config->voltage_level); in bdw_set_cdclk()
881 DIV_ROUND_CLOSEST(cdclk, 1000) - 1); in bdw_set_cdclk()
926 cdclk_config->ref = 24000; in skl_dpll0_update()
927 cdclk_config->vco = 0; in skl_dpll0_update()
933 if (drm_WARN_ON(&dev_priv->drm, (val & LCPLL_PLL_LOCK) == 0)) in skl_dpll0_update()
938 if (drm_WARN_ON(&dev_priv->drm, in skl_dpll0_update()
950 cdclk_config->vco = 8100000; in skl_dpll0_update()
954 cdclk_config->vco = 8640000; in skl_dpll0_update()
969 cdclk_config->cdclk = cdclk_config->bypass = cdclk_config->ref; in skl_get_cdclk()
971 if (cdclk_config->vco == 0) in skl_get_cdclk()
976 if (cdclk_config->vco == 8640000) { in skl_get_cdclk()
979 cdclk_config->cdclk = 432000; in skl_get_cdclk()
982 cdclk_config->cdclk = 308571; in skl_get_cdclk()
985 cdclk_config->cdclk = 540000; in skl_get_cdclk()
988 cdclk_config->cdclk = 617143; in skl_get_cdclk()
997 cdclk_config->cdclk = 450000; in skl_get_cdclk()
1000 cdclk_config->cdclk = 337500; in skl_get_cdclk()
1003 cdclk_config->cdclk = 540000; in skl_get_cdclk()
1006 cdclk_config->cdclk = 675000; in skl_get_cdclk()
1019 cdclk_config->voltage_level = in skl_get_cdclk()
1020 skl_calc_voltage_level(cdclk_config->cdclk); in skl_get_cdclk()
1023 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
1026 return DIV_ROUND_CLOSEST(cdclk - 1000, 500); in skl_cdclk_decimal()
1031 bool changed = i915->display.cdclk.skl_preferred_vco_freq != vco; in skl_set_preferred_cdclk_vco()
1033 i915->display.cdclk.skl_preferred_vco_freq = vco; in skl_set_preferred_cdclk_vco()
1041 drm_WARN_ON(&dev_priv->drm, vco != 8100000 && vco != 8640000); in skl_dpll0_link_rate()
1072 drm_err(&dev_priv->drm, "DPLL0 not locked\n"); in skl_dpll0_enable()
1074 dev_priv->display.cdclk.hw.vco = vco; in skl_dpll0_enable()
1086 drm_err(&dev_priv->drm, "Couldn't disable DPLL0\n"); in skl_dpll0_disable()
1088 dev_priv->display.cdclk.hw.vco = 0; in skl_dpll0_disable()
1096 drm_WARN_ON(&dev_priv->drm, in skl_cdclk_freq_sel()
1097 cdclk != dev_priv->display.cdclk.hw.bypass); in skl_cdclk_freq_sel()
1098 drm_WARN_ON(&dev_priv->drm, vco != 0); in skl_cdclk_freq_sel()
1118 int cdclk = cdclk_config->cdclk; in skl_set_cdclk()
1119 int vco = cdclk_config->vco; in skl_set_cdclk()
1131 drm_WARN_ON_ONCE(&dev_priv->drm, in skl_set_cdclk()
1134 ret = skl_pcode_request(&dev_priv->uncore, SKL_PCODE_CDCLK_CONTROL, in skl_set_cdclk()
1139 drm_err(&dev_priv->drm, in skl_set_cdclk()
1146 if (dev_priv->display.cdclk.hw.vco != 0 && in skl_set_cdclk()
1147 dev_priv->display.cdclk.hw.vco != vco) in skl_set_cdclk()
1152 if (dev_priv->display.cdclk.hw.vco != vco) { in skl_set_cdclk()
1164 if (dev_priv->display.cdclk.hw.vco != vco) in skl_set_cdclk()
1180 snb_pcode_write(&dev_priv->uncore, SKL_PCODE_CDCLK_CONTROL, in skl_set_cdclk()
1181 cdclk_config->voltage_level); in skl_set_cdclk()
1191 * check if the pre-os initialized the display in skl_sanitize_cdclk()
1193 * pre-os which can be used by the OS drivers to check the status in skl_sanitize_cdclk()
1199 intel_cdclk_dump_config(dev_priv, &dev_priv->display.cdclk.hw, "Current CDCLK"); in skl_sanitize_cdclk()
1202 if (dev_priv->display.cdclk.hw.vco == 0 || in skl_sanitize_cdclk()
1203 dev_priv->display.cdclk.hw.cdclk == dev_priv->display.cdclk.hw.bypass) in skl_sanitize_cdclk()
1209 * decimal part is programmed wrong from BIOS where pre-os does not in skl_sanitize_cdclk()
1214 skl_cdclk_decimal(dev_priv->display.cdclk.hw.cdclk); in skl_sanitize_cdclk()
1220 drm_dbg_kms(&dev_priv->drm, "Sanitizing cdclk programmed by pre-os\n"); in skl_sanitize_cdclk()
1223 dev_priv->display.cdclk.hw.cdclk = 0; in skl_sanitize_cdclk()
1225 dev_priv->display.cdclk.hw.vco = ~0; in skl_sanitize_cdclk()
1234 if (dev_priv->display.cdclk.hw.cdclk != 0 && in skl_cdclk_init_hw()
1235 dev_priv->display.cdclk.hw.vco != 0) { in skl_cdclk_init_hw()
1240 if (dev_priv->display.cdclk.skl_preferred_vco_freq == 0) in skl_cdclk_init_hw()
1242 dev_priv->display.cdclk.hw.vco); in skl_cdclk_init_hw()
1246 cdclk_config = dev_priv->display.cdclk.hw; in skl_cdclk_init_hw()
1248 cdclk_config.vco = dev_priv->display.cdclk.skl_preferred_vco_freq; in skl_cdclk_init_hw()
1259 struct intel_cdclk_config cdclk_config = dev_priv->display.cdclk.hw; in skl_cdclk_uninit_hw()
1475 const struct intel_cdclk_vals *table = dev_priv->display.cdclk.table; in bxt_calc_cdclk()
1479 if (table[i].refclk == dev_priv->display.cdclk.hw.ref && in bxt_calc_cdclk()
1483 drm_WARN(&dev_priv->drm, 1, in bxt_calc_cdclk()
1485 min_cdclk, dev_priv->display.cdclk.hw.ref); in bxt_calc_cdclk()
1491 const struct intel_cdclk_vals *table = dev_priv->display.cdclk.table; in bxt_calc_cdclk_pll_vco()
1494 if (cdclk == dev_priv->display.cdclk.hw.bypass) in bxt_calc_cdclk_pll_vco()
1498 if (table[i].refclk == dev_priv->display.cdclk.hw.ref && in bxt_calc_cdclk_pll_vco()
1500 return dev_priv->display.cdclk.hw.ref * table[i].ratio; in bxt_calc_cdclk_pll_vco()
1502 drm_WARN(&dev_priv->drm, 1, "cdclk %d not valid for refclk %u\n", in bxt_calc_cdclk_pll_vco()
1503 cdclk, dev_priv->display.cdclk.hw.ref); in bxt_calc_cdclk_pll_vco()
1523 return num_voltage_levels - 1; in calc_voltage_level()
1595 cdclk_config->ref = 24000; in icl_readout_refclk()
1598 cdclk_config->ref = 19200; in icl_readout_refclk()
1601 cdclk_config->ref = 38400; in icl_readout_refclk()
1612 cdclk_config->ref = 38400; in bxt_de_pll_readout()
1616 cdclk_config->ref = 19200; in bxt_de_pll_readout()
1625 cdclk_config->vco = 0; in bxt_de_pll_readout()
1638 cdclk_config->vco = ratio * cdclk_config->ref; in bxt_de_pll_readout()
1651 cdclk_config->bypass = cdclk_config->ref / 2; in bxt_get_cdclk()
1653 cdclk_config->bypass = 50000; in bxt_get_cdclk()
1655 cdclk_config->bypass = cdclk_config->ref; in bxt_get_cdclk()
1657 if (cdclk_config->vco == 0) { in bxt_get_cdclk()
1658 cdclk_config->cdclk = cdclk_config->bypass; in bxt_get_cdclk()
1690 waveform = REG_FIELD_GET(CDCLK_SQUASH_WAVEFORM_MASK, squash_ctl) >> (16 - size); in bxt_get_cdclk()
1692 cdclk_config->cdclk = DIV_ROUND_CLOSEST(hweight16(waveform) * in bxt_get_cdclk()
1693 cdclk_config->vco, size * div); in bxt_get_cdclk()
1695 cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco, div); in bxt_get_cdclk()
1700 cdclk_config->joined_mbus = intel_de_read(dev_priv, MBUS_CTL) & MBUS_JOIN; in bxt_get_cdclk()
1705 cdclk_config->voltage_level = in bxt_get_cdclk()
1706 intel_cdclk_calc_voltage_level(dev_priv, cdclk_config->cdclk); in bxt_get_cdclk()
1716 drm_err(&dev_priv->drm, "timeout waiting for DE PLL unlock\n"); in bxt_de_pll_disable()
1718 dev_priv->display.cdclk.hw.vco = 0; in bxt_de_pll_disable()
1723 int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->display.cdclk.hw.ref); in bxt_de_pll_enable()
1733 drm_err(&dev_priv->drm, "timeout waiting for DE PLL lock\n"); in bxt_de_pll_enable()
1735 dev_priv->display.cdclk.hw.vco = vco; in bxt_de_pll_enable()
1745 drm_err(&dev_priv->drm, "timeout waiting for CDCLK PLL unlock\n"); in icl_cdclk_pll_disable()
1747 dev_priv->display.cdclk.hw.vco = 0; in icl_cdclk_pll_disable()
1752 int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->display.cdclk.hw.ref); in icl_cdclk_pll_enable()
1763 drm_err(&dev_priv->drm, "timeout waiting for CDCLK PLL lock\n"); in icl_cdclk_pll_enable()
1765 dev_priv->display.cdclk.hw.vco = vco; in icl_cdclk_pll_enable()
1770 int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->display.cdclk.hw.ref); in adlp_cdclk_pll_crawl()
1784 drm_err(&dev_priv->drm, "timeout waiting for FREQ change request ack\n"); in adlp_cdclk_pll_crawl()
1789 dev_priv->display.cdclk.hw.vco = vco; in adlp_cdclk_pll_crawl()
1818 drm_WARN_ON(&dev_priv->drm, in bxt_cdclk_cd2x_div_sel()
1819 cdclk != dev_priv->display.cdclk.hw.bypass); in bxt_cdclk_cd2x_div_sel()
1820 drm_WARN_ON(&dev_priv->drm, vco != 0); in bxt_cdclk_cd2x_div_sel()
1836 const struct intel_cdclk_vals *table = dev_priv->display.cdclk.table; in cdclk_squash_waveform()
1839 if (cdclk == dev_priv->display.cdclk.hw.bypass) in cdclk_squash_waveform()
1843 if (table[i].refclk == dev_priv->display.cdclk.hw.ref && in cdclk_squash_waveform()
1847 drm_WARN(&dev_priv->drm, 1, "cdclk %d not valid for refclk %u\n", in cdclk_squash_waveform()
1848 cdclk, dev_priv->display.cdclk.hw.ref); in cdclk_squash_waveform()
1855 if (i915->display.cdclk.hw.vco != 0 && in icl_cdclk_pll_update()
1856 i915->display.cdclk.hw.vco != vco) in icl_cdclk_pll_update()
1859 if (i915->display.cdclk.hw.vco != vco) in icl_cdclk_pll_update()
1865 if (i915->display.cdclk.hw.vco != 0 && in bxt_cdclk_pll_update()
1866 i915->display.cdclk.hw.vco != vco) in bxt_cdclk_pll_update()
1869 if (i915->display.cdclk.hw.vco != vco) in bxt_cdclk_pll_update()
1912 return DIV_ROUND_UP(cdclk_config->vco, cdclk_config->cdclk); in intel_mdclk_cdclk_ratio()
1923 cdclk_config->joined_mbus); in xe2lpd_mdclk_cdclk_ratio_program()
1934 /* Return if PLL is in an unknown state, force a complete disable and re-enable. */ in cdclk_compute_crawl_and_squash_midpoint()
1935 if (cdclk_pll_is_unknown(old_cdclk_config->vco)) in cdclk_compute_crawl_and_squash_midpoint()
1942 old_waveform = cdclk_squash_waveform(i915, old_cdclk_config->cdclk); in cdclk_compute_crawl_and_squash_midpoint()
1943 new_waveform = cdclk_squash_waveform(i915, new_cdclk_config->cdclk); in cdclk_compute_crawl_and_squash_midpoint()
1946 if (old_cdclk_config->vco == 0 || new_cdclk_config->vco == 0 || in cdclk_compute_crawl_and_squash_midpoint()
1947 old_cdclk_config->vco == new_cdclk_config->vco || in cdclk_compute_crawl_and_squash_midpoint()
1951 old_div = cdclk_divider(old_cdclk_config->cdclk, in cdclk_compute_crawl_and_squash_midpoint()
1952 old_cdclk_config->vco, old_waveform); in cdclk_compute_crawl_and_squash_midpoint()
1953 new_div = cdclk_divider(new_cdclk_config->cdclk, in cdclk_compute_crawl_and_squash_midpoint()
1954 new_cdclk_config->vco, new_waveform); in cdclk_compute_crawl_and_squash_midpoint()
1960 if (drm_WARN_ON(&i915->drm, old_div != new_div)) in cdclk_compute_crawl_and_squash_midpoint()
1967 * - If moving to a higher cdclk, the desired action is squashing. in cdclk_compute_crawl_and_squash_midpoint()
1969 * - If moving to a lower cdclk, the desired action is crawling. in cdclk_compute_crawl_and_squash_midpoint()
1974 mid_cdclk_config->vco = old_cdclk_config->vco; in cdclk_compute_crawl_and_squash_midpoint()
1978 mid_cdclk_config->vco = new_cdclk_config->vco; in cdclk_compute_crawl_and_squash_midpoint()
1983 mid_cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_squash_divider(mid_waveform) * in cdclk_compute_crawl_and_squash_midpoint()
1984 mid_cdclk_config->vco, in cdclk_compute_crawl_and_squash_midpoint()
1989 drm_WARN_ON(&i915->drm, mid_cdclk_config->cdclk < in cdclk_compute_crawl_and_squash_midpoint()
1990 min(old_cdclk_config->cdclk, new_cdclk_config->cdclk)); in cdclk_compute_crawl_and_squash_midpoint()
1991 drm_WARN_ON(&i915->drm, mid_cdclk_config->cdclk > in cdclk_compute_crawl_and_squash_midpoint()
1992 i915->display.cdclk.max_cdclk_freq); in cdclk_compute_crawl_and_squash_midpoint()
1993 drm_WARN_ON(&i915->drm, cdclk_squash_waveform(i915, mid_cdclk_config->cdclk) != in cdclk_compute_crawl_and_squash_midpoint()
2004 dev_priv->display.cdclk.hw.vco > 0; in pll_enable_wa_needed()
2011 int cdclk = cdclk_config->cdclk; in bxt_cdclk_ctl()
2012 int vco = cdclk_config->vco; in bxt_cdclk_ctl()
2041 int cdclk = cdclk_config->cdclk; in _bxt_set_cdclk()
2042 int vco = cdclk_config->vco; in _bxt_set_cdclk()
2044 if (HAS_CDCLK_CRAWL(dev_priv) && dev_priv->display.cdclk.hw.vco > 0 && vco > 0 && in _bxt_set_cdclk()
2045 !cdclk_pll_is_unknown(dev_priv->display.cdclk.hw.vco)) { in _bxt_set_cdclk()
2046 if (dev_priv->display.cdclk.hw.vco != vco) in _bxt_set_cdclk()
2074 int cdclk = cdclk_config->cdclk; in bxt_set_cdclk()
2086 ret = skl_pcode_request(&dev_priv->uncore, SKL_PCODE_CDCLK_CONTROL, in bxt_set_cdclk()
2095 ret = snb_pcode_write_timeout(&dev_priv->uncore, in bxt_set_cdclk()
2100 drm_err(&dev_priv->drm, in bxt_set_cdclk()
2106 if (DISPLAY_VER(dev_priv) >= 20 && cdclk < dev_priv->display.cdclk.hw.cdclk) in bxt_set_cdclk()
2109 if (cdclk_compute_crawl_and_squash_midpoint(dev_priv, &dev_priv->display.cdclk.hw, in bxt_set_cdclk()
2117 if (DISPLAY_VER(dev_priv) >= 20 && cdclk > dev_priv->display.cdclk.hw.cdclk) in bxt_set_cdclk()
2122 * NOOP - No Pcode communication needed for in bxt_set_cdclk()
2126 ret = snb_pcode_write(&dev_priv->uncore, SKL_PCODE_CDCLK_CONTROL, in bxt_set_cdclk()
2127 cdclk_config->voltage_level); in bxt_set_cdclk()
2135 ret = snb_pcode_write_timeout(&dev_priv->uncore, in bxt_set_cdclk()
2137 cdclk_config->voltage_level, in bxt_set_cdclk()
2141 drm_err(&dev_priv->drm, in bxt_set_cdclk()
2154 dev_priv->display.cdclk.hw.voltage_level = cdclk_config->voltage_level; in bxt_set_cdclk()
2163 intel_cdclk_dump_config(dev_priv, &dev_priv->display.cdclk.hw, "Current CDCLK"); in bxt_sanitize_cdclk()
2165 if (dev_priv->display.cdclk.hw.vco == 0 || in bxt_sanitize_cdclk()
2166 dev_priv->display.cdclk.hw.cdclk == dev_priv->display.cdclk.hw.bypass) in bxt_sanitize_cdclk()
2170 cdclk = bxt_calc_cdclk(dev_priv, dev_priv->display.cdclk.hw.cdclk); in bxt_sanitize_cdclk()
2171 if (cdclk != dev_priv->display.cdclk.hw.cdclk) in bxt_sanitize_cdclk()
2176 if (vco != dev_priv->display.cdclk.hw.vco) in bxt_sanitize_cdclk()
2185 expected = bxt_cdclk_ctl(dev_priv, &dev_priv->display.cdclk.hw, INVALID_PIPE); in bxt_sanitize_cdclk()
2200 drm_dbg_kms(&dev_priv->drm, "Sanitizing cdclk programmed by pre-os\n"); in bxt_sanitize_cdclk()
2203 dev_priv->display.cdclk.hw.cdclk = 0; in bxt_sanitize_cdclk()
2206 dev_priv->display.cdclk.hw.vco = ~0; in bxt_sanitize_cdclk()
2215 if (dev_priv->display.cdclk.hw.cdclk != 0 && in bxt_cdclk_init_hw()
2216 dev_priv->display.cdclk.hw.vco != 0) in bxt_cdclk_init_hw()
2219 cdclk_config = dev_priv->display.cdclk.hw; in bxt_cdclk_init_hw()
2223 * - The initial CDCLK needs to be read from VBT. in bxt_cdclk_init_hw()
2236 struct intel_cdclk_config cdclk_config = dev_priv->display.cdclk.hw; in bxt_cdclk_uninit_hw()
2247 * intel_cdclk_init_hw - Initialize CDCLK hardware
2250 * Initialize CDCLK. This consists mainly of initializing dev_priv->display.cdclk.hw and
2252 * during the display core initialization sequence, after which the DMC will
2264 * intel_cdclk_uninit_hw - Uninitialize CDCLK hardware
2285 drm_WARN_ON(&i915->drm, cdclk_pll_is_unknown(a->vco)); in intel_cdclk_can_crawl_and_squash()
2287 if (a->vco == 0 || b->vco == 0) in intel_cdclk_can_crawl_and_squash()
2293 old_waveform = cdclk_squash_waveform(i915, a->cdclk); in intel_cdclk_can_crawl_and_squash()
2294 new_waveform = cdclk_squash_waveform(i915, b->cdclk); in intel_cdclk_can_crawl_and_squash()
2296 return a->vco != b->vco && in intel_cdclk_can_crawl_and_squash()
2313 a_div = DIV_ROUND_CLOSEST(a->vco, a->cdclk); in intel_cdclk_can_crawl()
2314 b_div = DIV_ROUND_CLOSEST(b->vco, b->cdclk); in intel_cdclk_can_crawl()
2316 return a->vco != 0 && b->vco != 0 && in intel_cdclk_can_crawl()
2317 a->vco != b->vco && in intel_cdclk_can_crawl()
2319 a->ref == b->ref; in intel_cdclk_can_crawl()
2335 return a->cdclk != b->cdclk && in intel_cdclk_can_squash()
2336 a->vco != 0 && in intel_cdclk_can_squash()
2337 a->vco == b->vco && in intel_cdclk_can_squash()
2338 a->ref == b->ref; in intel_cdclk_can_squash()
2342 * intel_cdclk_clock_changed - Check whether the clock changed
2347 * True if CDCLK changed in a way that requires re-programming and
2353 return a->cdclk != b->cdclk || in intel_cdclk_clock_changed()
2354 a->vco != b->vco || in intel_cdclk_clock_changed()
2355 a->ref != b->ref; in intel_cdclk_clock_changed()
2359 * intel_cdclk_can_cd2x_update - Determine if changing between the two CDCLK
2386 return a->cdclk != b->cdclk && in intel_cdclk_can_cd2x_update()
2387 a->vco != 0 && in intel_cdclk_can_cd2x_update()
2388 a->vco == b->vco && in intel_cdclk_can_cd2x_update()
2389 a->ref == b->ref; in intel_cdclk_can_cd2x_update()
2393 * intel_cdclk_changed - Determine if two CDCLK configurations are different
2404 a->voltage_level != b->voltage_level; in intel_cdclk_changed()
2411 drm_dbg_kms(&i915->drm, "%s %d kHz, VCO %d kHz, ref %d kHz, bypass %d kHz, voltage level %d\n", in intel_cdclk_dump_config()
2412 context, cdclk_config->cdclk, cdclk_config->vco, in intel_cdclk_dump_config()
2413 cdclk_config->ref, cdclk_config->bypass, in intel_cdclk_dump_config()
2414 cdclk_config->voltage_level); in intel_cdclk_dump_config()
2438 ret = skl_pcode_request(&i915->uncore, SKL_PCODE_CDCLK_CONTROL, in intel_pcode_notify()
2444 drm_err(&i915->drm, in intel_pcode_notify()
2455 if (!intel_cdclk_changed(&dev_priv->display.cdclk.hw, cdclk_config)) in intel_set_cdclk()
2458 if (drm_WARN_ON_ONCE(&dev_priv->drm, !dev_priv->display.funcs.cdclk->set_cdclk)) in intel_set_cdclk()
2463 for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) { in intel_set_cdclk()
2476 mutex_lock(&dev_priv->display.gmbus.mutex); in intel_set_cdclk()
2477 for_each_intel_dp(&dev_priv->drm, encoder) { in intel_set_cdclk()
2480 mutex_lock_nest_lock(&intel_dp->aux.hw_mutex, in intel_set_cdclk()
2481 &dev_priv->display.gmbus.mutex); in intel_set_cdclk()
2486 for_each_intel_dp(&dev_priv->drm, encoder) { in intel_set_cdclk()
2489 mutex_unlock(&intel_dp->aux.hw_mutex); in intel_set_cdclk()
2491 mutex_unlock(&dev_priv->display.gmbus.mutex); in intel_set_cdclk()
2493 for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) { in intel_set_cdclk()
2501 if (drm_WARN(&dev_priv->drm, in intel_set_cdclk()
2502 intel_cdclk_changed(&dev_priv->display.cdclk.hw, cdclk_config), in intel_set_cdclk()
2504 intel_cdclk_dump_config(dev_priv, &dev_priv->display.cdclk.hw, "[hw state]"); in intel_set_cdclk()
2511 struct drm_i915_private *i915 = to_i915(state->base.dev); in intel_cdclk_pcode_pre_notify()
2519 if (!intel_cdclk_changed(&old_cdclk_state->actual, in intel_cdclk_pcode_pre_notify()
2520 &new_cdclk_state->actual) && in intel_cdclk_pcode_pre_notify()
2521 new_cdclk_state->active_pipes == in intel_cdclk_pcode_pre_notify()
2522 old_cdclk_state->active_pipes) in intel_cdclk_pcode_pre_notify()
2528 change_cdclk = new_cdclk_state->actual.cdclk != old_cdclk_state->actual.cdclk; in intel_cdclk_pcode_pre_notify()
2529 update_pipe_count = hweight8(new_cdclk_state->active_pipes) > in intel_cdclk_pcode_pre_notify()
2530 hweight8(old_cdclk_state->active_pipes); in intel_cdclk_pcode_pre_notify()
2539 cdclk = max(new_cdclk_state->actual.cdclk, old_cdclk_state->actual.cdclk); in intel_cdclk_pcode_pre_notify()
2548 num_active_pipes = hweight8(new_cdclk_state->active_pipes); in intel_cdclk_pcode_pre_notify()
2556 struct drm_i915_private *i915 = to_i915(state->base.dev); in intel_cdclk_pcode_post_notify()
2565 voltage_level = new_cdclk_state->actual.voltage_level; in intel_cdclk_pcode_post_notify()
2567 update_cdclk = new_cdclk_state->actual.cdclk != old_cdclk_state->actual.cdclk; in intel_cdclk_pcode_post_notify()
2568 update_pipe_count = hweight8(new_cdclk_state->active_pipes) < in intel_cdclk_pcode_post_notify()
2569 hweight8(old_cdclk_state->active_pipes); in intel_cdclk_pcode_post_notify()
2576 cdclk = new_cdclk_state->actual.cdclk; in intel_cdclk_pcode_post_notify()
2585 num_active_pipes = hweight8(new_cdclk_state->active_pipes); in intel_cdclk_pcode_post_notify()
2598 return new_cdclk_state && !new_cdclk_state->disable_pipes && in intel_cdclk_is_decreasing_later()
2599 new_cdclk_state->actual.cdclk < old_cdclk_state->actual.cdclk; in intel_cdclk_is_decreasing_later()
2603 * intel_set_cdclk_pre_plane_update - Push the CDCLK state to the hardware
2612 struct drm_i915_private *i915 = to_i915(state->base.dev); in intel_set_cdclk_pre_plane_update()
2620 if (!intel_cdclk_changed(&old_cdclk_state->actual, in intel_set_cdclk_pre_plane_update()
2621 &new_cdclk_state->actual)) in intel_set_cdclk_pre_plane_update()
2627 if (new_cdclk_state->disable_pipes) { in intel_set_cdclk_pre_plane_update()
2628 cdclk_config = new_cdclk_state->actual; in intel_set_cdclk_pre_plane_update()
2631 if (new_cdclk_state->actual.cdclk >= old_cdclk_state->actual.cdclk) { in intel_set_cdclk_pre_plane_update()
2632 cdclk_config = new_cdclk_state->actual; in intel_set_cdclk_pre_plane_update()
2633 pipe = new_cdclk_state->pipe; in intel_set_cdclk_pre_plane_update()
2635 cdclk_config = old_cdclk_state->actual; in intel_set_cdclk_pre_plane_update()
2639 cdclk_config.voltage_level = max(new_cdclk_state->actual.voltage_level, in intel_set_cdclk_pre_plane_update()
2640 old_cdclk_state->actual.voltage_level); in intel_set_cdclk_pre_plane_update()
2647 cdclk_config.joined_mbus = old_cdclk_state->actual.joined_mbus; in intel_set_cdclk_pre_plane_update()
2649 drm_WARN_ON(&i915->drm, !new_cdclk_state->base.changed); in intel_set_cdclk_pre_plane_update()
2656 * intel_set_cdclk_post_plane_update - Push the CDCLK state to the hardware
2665 struct drm_i915_private *i915 = to_i915(state->base.dev); in intel_set_cdclk_post_plane_update()
2672 if (!intel_cdclk_changed(&old_cdclk_state->actual, in intel_set_cdclk_post_plane_update()
2673 &new_cdclk_state->actual)) in intel_set_cdclk_post_plane_update()
2679 if (!new_cdclk_state->disable_pipes && in intel_set_cdclk_post_plane_update()
2680 new_cdclk_state->actual.cdclk < old_cdclk_state->actual.cdclk) in intel_set_cdclk_post_plane_update()
2681 pipe = new_cdclk_state->pipe; in intel_set_cdclk_post_plane_update()
2685 drm_WARN_ON(&i915->drm, !new_cdclk_state->base.changed); in intel_set_cdclk_post_plane_update()
2687 intel_set_cdclk(i915, &new_cdclk_state->actual, pipe, in intel_set_cdclk_post_plane_update()
2693 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); in intel_pixel_rate_to_cdclk()
2694 int pixel_rate = crtc_state->pixel_rate; in intel_pixel_rate_to_cdclk()
2703 else if (crtc_state->double_wide) in intel_pixel_rate_to_cdclk()
2711 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in intel_planes_min_cdclk()
2712 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in intel_planes_min_cdclk()
2716 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) in intel_planes_min_cdclk()
2717 min_cdclk = max(crtc_state->min_cdclk[plane->id], min_cdclk); in intel_planes_min_cdclk()
2724 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in intel_vdsc_min_cdclk()
2725 struct drm_i915_private *i915 = to_i915(crtc->base.dev); in intel_vdsc_min_cdclk()
2737 DIV_ROUND_UP(crtc_state->pixel_rate, num_vdsc_instances)); in intel_vdsc_min_cdclk()
2739 if (crtc_state->joiner_pipes) { in intel_vdsc_min_cdclk()
2740 int pixel_clock = intel_dp_mode_to_fec_clock(crtc_state->hw.adjusted_mode.clock); in intel_vdsc_min_cdclk()
2756 (fxp_q4_to_int_roundup(crtc_state->dsc.compressed_bpp_x16) * in intel_vdsc_min_cdclk()
2768 to_i915(crtc_state->uapi.crtc->dev); in intel_crtc_compute_min_cdclk()
2771 if (!crtc_state->hw.enable) in intel_crtc_compute_min_cdclk()
2786 crtc_state->has_audio && in intel_crtc_compute_min_cdclk()
2787 crtc_state->port_clock >= 540000 && in intel_crtc_compute_min_cdclk()
2788 crtc_state->lane_count == 4) { in intel_crtc_compute_min_cdclk()
2802 if (crtc_state->has_audio && DISPLAY_VER(dev_priv) >= 9) in intel_crtc_compute_min_cdclk()
2813 intel_crtc_has_dp_encoder(crtc_state) && crtc_state->has_audio) in intel_crtc_compute_min_cdclk()
2814 min_cdclk = max(crtc_state->port_clock, min_cdclk); in intel_crtc_compute_min_cdclk()
2836 if (crtc_state->dsc.compression_enable) in intel_crtc_compute_min_cdclk()
2844 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in intel_compute_min_cdclk()
2860 if (cdclk_state->min_cdclk[crtc->pipe] == min_cdclk) in intel_compute_min_cdclk()
2863 cdclk_state->min_cdclk[crtc->pipe] = min_cdclk; in intel_compute_min_cdclk()
2865 ret = intel_atomic_lock_global_state(&cdclk_state->base); in intel_compute_min_cdclk()
2874 if (cdclk_state->bw_min_cdclk != min_cdclk) { in intel_compute_min_cdclk()
2877 cdclk_state->bw_min_cdclk = min_cdclk; in intel_compute_min_cdclk()
2879 ret = intel_atomic_lock_global_state(&cdclk_state->base); in intel_compute_min_cdclk()
2885 min_cdclk = max(cdclk_state->force_min_cdclk, in intel_compute_min_cdclk()
2886 cdclk_state->bw_min_cdclk); in intel_compute_min_cdclk()
2888 min_cdclk = max(cdclk_state->min_cdclk[pipe], min_cdclk); in intel_compute_min_cdclk()
2898 if (IS_GEMINILAKE(dev_priv) && cdclk_state->active_pipes && in intel_compute_min_cdclk()
2899 !is_power_of_2(cdclk_state->active_pipes)) in intel_compute_min_cdclk()
2902 if (min_cdclk > dev_priv->display.cdclk.max_cdclk_freq) { in intel_compute_min_cdclk()
2903 drm_dbg_kms(&dev_priv->drm, in intel_compute_min_cdclk()
2905 min_cdclk, dev_priv->display.cdclk.max_cdclk_freq); in intel_compute_min_cdclk()
2906 return -EINVAL; in intel_compute_min_cdclk()
2927 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in bxt_compute_min_voltage_level()
2939 if (crtc_state->hw.enable) in bxt_compute_min_voltage_level()
2940 min_voltage_level = crtc_state->min_voltage_level; in bxt_compute_min_voltage_level()
2944 if (cdclk_state->min_voltage_level[crtc->pipe] == min_voltage_level) in bxt_compute_min_voltage_level()
2947 cdclk_state->min_voltage_level[crtc->pipe] = min_voltage_level; in bxt_compute_min_voltage_level()
2949 ret = intel_atomic_lock_global_state(&cdclk_state->base); in bxt_compute_min_voltage_level()
2956 min_voltage_level = max(cdclk_state->min_voltage_level[pipe], in bxt_compute_min_voltage_level()
2964 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in vlv_modeset_calc_cdclk()
2975 cdclk_state->logical.cdclk = cdclk; in vlv_modeset_calc_cdclk()
2976 cdclk_state->logical.voltage_level = in vlv_modeset_calc_cdclk()
2979 if (!cdclk_state->active_pipes) { in vlv_modeset_calc_cdclk()
2980 cdclk = vlv_calc_cdclk(dev_priv, cdclk_state->force_min_cdclk); in vlv_modeset_calc_cdclk()
2982 cdclk_state->actual.cdclk = cdclk; in vlv_modeset_calc_cdclk()
2983 cdclk_state->actual.voltage_level = in vlv_modeset_calc_cdclk()
2986 cdclk_state->actual = cdclk_state->logical; in vlv_modeset_calc_cdclk()
3004 cdclk_state->logical.cdclk = cdclk; in bdw_modeset_calc_cdclk()
3005 cdclk_state->logical.voltage_level = in bdw_modeset_calc_cdclk()
3008 if (!cdclk_state->active_pipes) { in bdw_modeset_calc_cdclk()
3009 cdclk = bdw_calc_cdclk(cdclk_state->force_min_cdclk); in bdw_modeset_calc_cdclk()
3011 cdclk_state->actual.cdclk = cdclk; in bdw_modeset_calc_cdclk()
3012 cdclk_state->actual.voltage_level = in bdw_modeset_calc_cdclk()
3015 cdclk_state->actual = cdclk_state->logical; in bdw_modeset_calc_cdclk()
3023 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in skl_dpll0_vco()
3030 vco = cdclk_state->logical.vco; in skl_dpll0_vco()
3032 vco = dev_priv->display.cdclk.skl_preferred_vco_freq; in skl_dpll0_vco()
3035 if (!crtc_state->hw.enable) in skl_dpll0_vco()
3045 switch (crtc_state->port_clock / 2) { in skl_dpll0_vco()
3073 cdclk_state->logical.vco = vco; in skl_modeset_calc_cdclk()
3074 cdclk_state->logical.cdclk = cdclk; in skl_modeset_calc_cdclk()
3075 cdclk_state->logical.voltage_level = in skl_modeset_calc_cdclk()
3078 if (!cdclk_state->active_pipes) { in skl_modeset_calc_cdclk()
3079 cdclk = skl_calc_cdclk(cdclk_state->force_min_cdclk, vco); in skl_modeset_calc_cdclk()
3081 cdclk_state->actual.vco = vco; in skl_modeset_calc_cdclk()
3082 cdclk_state->actual.cdclk = cdclk; in skl_modeset_calc_cdclk()
3083 cdclk_state->actual.voltage_level = in skl_modeset_calc_cdclk()
3086 cdclk_state->actual = cdclk_state->logical; in skl_modeset_calc_cdclk()
3094 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in bxt_modeset_calc_cdclk()
3110 cdclk_state->logical.vco = vco; in bxt_modeset_calc_cdclk()
3111 cdclk_state->logical.cdclk = cdclk; in bxt_modeset_calc_cdclk()
3112 cdclk_state->logical.voltage_level = in bxt_modeset_calc_cdclk()
3116 if (!cdclk_state->active_pipes) { in bxt_modeset_calc_cdclk()
3117 cdclk = bxt_calc_cdclk(dev_priv, cdclk_state->force_min_cdclk); in bxt_modeset_calc_cdclk()
3120 cdclk_state->actual.vco = vco; in bxt_modeset_calc_cdclk()
3121 cdclk_state->actual.cdclk = cdclk; in bxt_modeset_calc_cdclk()
3122 cdclk_state->actual.voltage_level = in bxt_modeset_calc_cdclk()
3125 cdclk_state->actual = cdclk_state->logical; in bxt_modeset_calc_cdclk()
3151 cdclk_state = kmemdup(obj->state, sizeof(*cdclk_state), GFP_KERNEL); in intel_cdclk_duplicate_state()
3155 cdclk_state->pipe = INVALID_PIPE; in intel_cdclk_duplicate_state()
3156 cdclk_state->disable_pipes = false; in intel_cdclk_duplicate_state()
3158 return &cdclk_state->base; in intel_cdclk_duplicate_state()
3175 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in intel_atomic_get_cdclk_state()
3178 cdclk_state = intel_atomic_get_global_obj_state(state, &dev_priv->display.cdclk.obj); in intel_atomic_get_cdclk_state()
3214 old_cdclk_state->force_min_cdclk != new_cdclk_state->force_min_cdclk) in intel_cdclk_atomic_check()
3228 cdclk_state->actual.joined_mbus = joined_mbus; in intel_cdclk_state_set_joined_mbus()
3229 cdclk_state->logical.joined_mbus = joined_mbus; in intel_cdclk_state_set_joined_mbus()
3231 return intel_atomic_lock_global_state(&cdclk_state->base); in intel_cdclk_state_set_joined_mbus()
3240 return -ENOMEM; in intel_cdclk_init()
3242 intel_atomic_global_obj_init(dev_priv, &dev_priv->display.cdclk.obj, in intel_cdclk_init()
3243 &cdclk_state->base, &intel_cdclk_funcs); in intel_cdclk_init()
3252 bool power_well_cnt_changed = hweight8(old_cdclk_state->active_pipes) != in intel_cdclk_need_serialize()
3253 hweight8(new_cdclk_state->active_pipes); in intel_cdclk_need_serialize()
3254 bool cdclk_changed = intel_cdclk_changed(&old_cdclk_state->actual, in intel_cdclk_need_serialize()
3255 &new_cdclk_state->actual); in intel_cdclk_need_serialize()
3265 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in intel_modeset_calc_cdclk()
3277 new_cdclk_state->active_pipes = in intel_modeset_calc_cdclk()
3278 intel_calc_active_pipes(state, old_cdclk_state->active_pipes); in intel_modeset_calc_cdclk()
3289 ret = intel_atomic_serialize_global_state(&new_cdclk_state->base); in intel_modeset_calc_cdclk()
3292 } else if (old_cdclk_state->active_pipes != new_cdclk_state->active_pipes || in intel_modeset_calc_cdclk()
3293 old_cdclk_state->force_min_cdclk != new_cdclk_state->force_min_cdclk || in intel_modeset_calc_cdclk()
3294 intel_cdclk_changed(&old_cdclk_state->logical, in intel_modeset_calc_cdclk()
3295 &new_cdclk_state->logical)) { in intel_modeset_calc_cdclk()
3296 ret = intel_atomic_lock_global_state(&new_cdclk_state->base); in intel_modeset_calc_cdclk()
3303 if (is_power_of_2(new_cdclk_state->active_pipes) && in intel_modeset_calc_cdclk()
3305 &old_cdclk_state->actual, in intel_modeset_calc_cdclk()
3306 &new_cdclk_state->actual)) { in intel_modeset_calc_cdclk()
3310 pipe = ilog2(new_cdclk_state->active_pipes); in intel_modeset_calc_cdclk()
3313 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc); in intel_modeset_calc_cdclk()
3322 &old_cdclk_state->actual, in intel_modeset_calc_cdclk()
3323 &new_cdclk_state->actual)) { in intel_modeset_calc_cdclk()
3324 drm_dbg_kms(&dev_priv->drm, in intel_modeset_calc_cdclk()
3327 &old_cdclk_state->actual, in intel_modeset_calc_cdclk()
3328 &new_cdclk_state->actual)) { in intel_modeset_calc_cdclk()
3329 drm_dbg_kms(&dev_priv->drm, in intel_modeset_calc_cdclk()
3332 &old_cdclk_state->actual, in intel_modeset_calc_cdclk()
3333 &new_cdclk_state->actual)) { in intel_modeset_calc_cdclk()
3334 drm_dbg_kms(&dev_priv->drm, in intel_modeset_calc_cdclk()
3337 new_cdclk_state->pipe = pipe; in intel_modeset_calc_cdclk()
3339 drm_dbg_kms(&dev_priv->drm, in intel_modeset_calc_cdclk()
3342 } else if (intel_cdclk_clock_changed(&old_cdclk_state->actual, in intel_modeset_calc_cdclk()
3343 &new_cdclk_state->actual)) { in intel_modeset_calc_cdclk()
3349 new_cdclk_state->disable_pipes = true; in intel_modeset_calc_cdclk()
3351 drm_dbg_kms(&dev_priv->drm, in intel_modeset_calc_cdclk()
3355 if (intel_mdclk_cdclk_ratio(dev_priv, &old_cdclk_state->actual) != in intel_modeset_calc_cdclk()
3356 intel_mdclk_cdclk_ratio(dev_priv, &new_cdclk_state->actual)) { in intel_modeset_calc_cdclk()
3357 int ratio = intel_mdclk_cdclk_ratio(dev_priv, &new_cdclk_state->actual); in intel_modeset_calc_cdclk()
3364 drm_dbg_kms(&dev_priv->drm, in intel_modeset_calc_cdclk()
3366 new_cdclk_state->logical.cdclk, in intel_modeset_calc_cdclk()
3367 new_cdclk_state->actual.cdclk); in intel_modeset_calc_cdclk()
3368 drm_dbg_kms(&dev_priv->drm, in intel_modeset_calc_cdclk()
3370 new_cdclk_state->logical.voltage_level, in intel_modeset_calc_cdclk()
3371 new_cdclk_state->actual.voltage_level); in intel_modeset_calc_cdclk()
3378 int max_cdclk_freq = dev_priv->display.cdclk.max_cdclk_freq; in intel_compute_max_dotclk()
3394 * intel_update_max_cdclk - Determine the maximum support CDCLK frequency
3404 if (dev_priv->display.cdclk.hw.ref == 24000) in intel_update_max_cdclk()
3405 dev_priv->display.cdclk.max_cdclk_freq = 552000; in intel_update_max_cdclk()
3407 dev_priv->display.cdclk.max_cdclk_freq = 556800; in intel_update_max_cdclk()
3409 if (dev_priv->display.cdclk.hw.ref == 24000) in intel_update_max_cdclk()
3410 dev_priv->display.cdclk.max_cdclk_freq = 648000; in intel_update_max_cdclk()
3412 dev_priv->display.cdclk.max_cdclk_freq = 652800; in intel_update_max_cdclk()
3414 dev_priv->display.cdclk.max_cdclk_freq = 316800; in intel_update_max_cdclk()
3416 dev_priv->display.cdclk.max_cdclk_freq = 624000; in intel_update_max_cdclk()
3421 vco = dev_priv->display.cdclk.skl_preferred_vco_freq; in intel_update_max_cdclk()
3422 drm_WARN_ON(&dev_priv->drm, vco != 8100000 && vco != 8640000); in intel_update_max_cdclk()
3438 dev_priv->display.cdclk.max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco); in intel_update_max_cdclk()
3447 dev_priv->display.cdclk.max_cdclk_freq = 450000; in intel_update_max_cdclk()
3449 dev_priv->display.cdclk.max_cdclk_freq = 450000; in intel_update_max_cdclk()
3451 dev_priv->display.cdclk.max_cdclk_freq = 540000; in intel_update_max_cdclk()
3453 dev_priv->display.cdclk.max_cdclk_freq = 675000; in intel_update_max_cdclk()
3455 dev_priv->display.cdclk.max_cdclk_freq = 320000; in intel_update_max_cdclk()
3457 dev_priv->display.cdclk.max_cdclk_freq = 400000; in intel_update_max_cdclk()
3460 dev_priv->display.cdclk.max_cdclk_freq = dev_priv->display.cdclk.hw.cdclk; in intel_update_max_cdclk()
3463 dev_priv->display.cdclk.max_dotclk_freq = intel_compute_max_dotclk(dev_priv); in intel_update_max_cdclk()
3465 drm_dbg(&dev_priv->drm, "Max CD clock rate: %d kHz\n", in intel_update_max_cdclk()
3466 dev_priv->display.cdclk.max_cdclk_freq); in intel_update_max_cdclk()
3468 drm_dbg(&dev_priv->drm, "Max dotclock rate: %d kHz\n", in intel_update_max_cdclk()
3469 dev_priv->display.cdclk.max_dotclk_freq); in intel_update_max_cdclk()
3473 * intel_update_cdclk - Determine the current CDCLK frequency
3480 intel_cdclk_get_cdclk(dev_priv, &dev_priv->display.cdclk.hw); in intel_update_cdclk()
3490 DIV_ROUND_UP(dev_priv->display.cdclk.hw.cdclk, 1000)); in intel_update_cdclk()
3525 fraction) - 1); in cnp_rawclk()
3553 * intel_read_rawclk - Determine the current RAWCLK frequency
3589 struct drm_i915_private *i915 = m->private; in i915_cdclk_info_show()
3591 seq_printf(m, "Current CD clock frequency: %d kHz\n", i915->display.cdclk.hw.cdclk); in i915_cdclk_info_show()
3592 seq_printf(m, "Max CD clock frequency: %d kHz\n", i915->display.cdclk.max_cdclk_freq); in i915_cdclk_info_show()
3593 seq_printf(m, "Max pixel clock frequency: %d kHz\n", i915->display.cdclk.max_dotclk_freq); in i915_cdclk_info_show()
3602 struct drm_minor *minor = i915->drm.primary; in intel_cdclk_debugfs_register()
3604 debugfs_create_file("i915_cdclk_info", 0444, minor->debugfs_root, in intel_cdclk_debugfs_register()
3745 * intel_init_cdclk_hooks - Initialize CDCLK related modesetting hooks
3751 dev_priv->display.funcs.cdclk = &rplu_cdclk_funcs; in intel_init_cdclk_hooks()
3752 dev_priv->display.cdclk.table = xe2lpd_cdclk_table; in intel_init_cdclk_hooks()
3754 dev_priv->display.funcs.cdclk = &rplu_cdclk_funcs; in intel_init_cdclk_hooks()
3755 dev_priv->display.cdclk.table = xe2hpd_cdclk_table; in intel_init_cdclk_hooks()
3757 dev_priv->display.funcs.cdclk = &rplu_cdclk_funcs; in intel_init_cdclk_hooks()
3758 dev_priv->display.cdclk.table = mtl_cdclk_table; in intel_init_cdclk_hooks()
3760 dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs; in intel_init_cdclk_hooks()
3761 dev_priv->display.cdclk.table = dg2_cdclk_table; in intel_init_cdclk_hooks()
3763 /* Wa_22011320316:adl-p[a0] */ in intel_init_cdclk_hooks()
3765 dev_priv->display.cdclk.table = adlp_a_step_cdclk_table; in intel_init_cdclk_hooks()
3766 dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs; in intel_init_cdclk_hooks()
3768 dev_priv->display.cdclk.table = rplu_cdclk_table; in intel_init_cdclk_hooks()
3769 dev_priv->display.funcs.cdclk = &rplu_cdclk_funcs; in intel_init_cdclk_hooks()
3771 dev_priv->display.cdclk.table = adlp_cdclk_table; in intel_init_cdclk_hooks()
3772 dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs; in intel_init_cdclk_hooks()
3775 dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs; in intel_init_cdclk_hooks()
3776 dev_priv->display.cdclk.table = rkl_cdclk_table; in intel_init_cdclk_hooks()
3778 dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs; in intel_init_cdclk_hooks()
3779 dev_priv->display.cdclk.table = icl_cdclk_table; in intel_init_cdclk_hooks()
3781 dev_priv->display.funcs.cdclk = &ehl_cdclk_funcs; in intel_init_cdclk_hooks()
3782 dev_priv->display.cdclk.table = icl_cdclk_table; in intel_init_cdclk_hooks()
3784 dev_priv->display.funcs.cdclk = &icl_cdclk_funcs; in intel_init_cdclk_hooks()
3785 dev_priv->display.cdclk.table = icl_cdclk_table; in intel_init_cdclk_hooks()
3787 dev_priv->display.funcs.cdclk = &bxt_cdclk_funcs; in intel_init_cdclk_hooks()
3789 dev_priv->display.cdclk.table = glk_cdclk_table; in intel_init_cdclk_hooks()
3791 dev_priv->display.cdclk.table = bxt_cdclk_table; in intel_init_cdclk_hooks()
3793 dev_priv->display.funcs.cdclk = &skl_cdclk_funcs; in intel_init_cdclk_hooks()
3795 dev_priv->display.funcs.cdclk = &bdw_cdclk_funcs; in intel_init_cdclk_hooks()
3797 dev_priv->display.funcs.cdclk = &hsw_cdclk_funcs; in intel_init_cdclk_hooks()
3799 dev_priv->display.funcs.cdclk = &chv_cdclk_funcs; in intel_init_cdclk_hooks()
3801 dev_priv->display.funcs.cdclk = &vlv_cdclk_funcs; in intel_init_cdclk_hooks()
3803 dev_priv->display.funcs.cdclk = &fixed_400mhz_cdclk_funcs; in intel_init_cdclk_hooks()
3805 dev_priv->display.funcs.cdclk = &ilk_cdclk_funcs; in intel_init_cdclk_hooks()
3807 dev_priv->display.funcs.cdclk = &gm45_cdclk_funcs; in intel_init_cdclk_hooks()
3809 dev_priv->display.funcs.cdclk = &g33_cdclk_funcs; in intel_init_cdclk_hooks()
3811 dev_priv->display.funcs.cdclk = &i965gm_cdclk_funcs; in intel_init_cdclk_hooks()
3813 dev_priv->display.funcs.cdclk = &fixed_400mhz_cdclk_funcs; in intel_init_cdclk_hooks()
3815 dev_priv->display.funcs.cdclk = &pnv_cdclk_funcs; in intel_init_cdclk_hooks()
3817 dev_priv->display.funcs.cdclk = &g33_cdclk_funcs; in intel_init_cdclk_hooks()
3819 dev_priv->display.funcs.cdclk = &i945gm_cdclk_funcs; in intel_init_cdclk_hooks()
3821 dev_priv->display.funcs.cdclk = &fixed_400mhz_cdclk_funcs; in intel_init_cdclk_hooks()
3823 dev_priv->display.funcs.cdclk = &i915gm_cdclk_funcs; in intel_init_cdclk_hooks()
3825 dev_priv->display.funcs.cdclk = &i915g_cdclk_funcs; in intel_init_cdclk_hooks()
3827 dev_priv->display.funcs.cdclk = &i865g_cdclk_funcs; in intel_init_cdclk_hooks()
3829 dev_priv->display.funcs.cdclk = &i85x_cdclk_funcs; in intel_init_cdclk_hooks()
3831 dev_priv->display.funcs.cdclk = &i845g_cdclk_funcs; in intel_init_cdclk_hooks()
3833 dev_priv->display.funcs.cdclk = &i830_cdclk_funcs; in intel_init_cdclk_hooks()
3836 if (drm_WARN(&dev_priv->drm, !dev_priv->display.funcs.cdclk, in intel_init_cdclk_hooks()
3838 dev_priv->display.funcs.cdclk = &i830_cdclk_funcs; in intel_init_cdclk_hooks()