Lines Matching +full:bus +full:- +full:dmc

5 The ThunderX2 SoC PMU consists of independent, system-wide, per-socket
6 PMUs such as the Level 3 Cache (L3C), DDR4 Memory Controller (DMC) and
9 The DMC has 8 interleaved channels and the L3C has 16 interleaved tiles.
13 The DMC and L3C support up to 4 counters, while the CCPI2 supports up to 8
16 overflow interrupt. DMC and L3C counters are 32-bit and read every 2 seconds.
17 The CCPI2 counters are 64-bit and assumed not to overflow in normal operation.
21 The thunderx2_pmu driver registers per-socket perf PMUs for the DMC and
22 L3C devices.  Each PMU can be used to count up to 4 (DMC/L3C) or up to 8
25 /sys/bus/event_source/devices/uncore_<l3c_S/dmc_S/ccpi2_S/>; S is the socket id.
28 work. Per-task perf sessions are also not supported.
32   # perf stat -a -e uncore_dmc_0/cnt_cycles/ sleep 1
34   # perf stat -a -e \
40   # perf stat -a -e \