Searched +full:bcm6345 +full:- +full:reset (Results 1 – 9 of 9) sorted by relevance
1 // SPDX-License-Identifier: GPL-2.03 #include "dt-bindings/clock/bcm63268-clock.h"4 #include "dt-bindings/reset/bcm63268-reset.h"5 #include "dt-bindings/soc/bcm63268-pm.h"8 #address-cells = <1>;9 #size-cells = <1>;13 #address-cells = <1>;14 #size-cells = <0>;16 mips-hpt-frequency = <200000000>;32 periph_osc: periph-osc {[all …]
1 // SPDX-License-Identifier: GPL-2.03 #include "dt-bindings/clock/bcm6362-clock.h"4 #include "dt-bindings/reset/bcm6362-reset.h"5 #include "dt-bindings/soc/bcm6362-pm.h"8 #address-cells = <1>;9 #size-cells = <1>;13 #address-cells = <1>;14 #size-cells = <0>;16 mips-hpt-frequency = <200000000>;32 periph_osc: periph-osc {[all …]
1 // SPDX-License-Identifier: GPL-2.03 #include "dt-bindings/clock/bcm6328-clock.h"4 #include "dt-bindings/reset/bcm6328-reset.h"5 #include "dt-bindings/soc/bcm6328-pm.h"8 #address-cells = <1>;9 #size-cells = <1>;13 #address-cells = <1>;14 #size-cells = <0>;16 mips-hpt-frequency = <160000000>;32 periph_osc: periph-osc {[all …]
1 // SPDX-License-Identifier: GPL-2.06 #include <dt-bindings/interrupt-controller/arm-gic.h>7 #include <dt-bindings/interrupt-controller/irq.h>10 #address-cells = <1>;11 #size-cells = <1>;14 interrupt-parent = <&gic>;22 #address-cells = <1>;23 #size-cells = <0>;27 compatible = "arm,cortex-a9";28 next-level-cache = <&L2>;[all …]
1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT3 #include <dt-bindings/interrupt-controller/irq.h>4 #include <dt-bindings/interrupt-controller/arm-gic.h>5 #include <dt-bindings/phy/phy.h>6 #include <dt-bindings/soc/bcm-pmb.h>8 /dts-v1/;11 interrupt-parent = <&gic>;13 #address-cells = <2>;14 #size-cells = <2>;21 stdout-path = "serial0:115200n8";[all …]
1 # SPDX-License-Identifier: GPL-2.0-only6 bool "Reset Controller Support"9 Generic Reset Controller support.11 This framework is designed to abstract reset handling of devices12 via GPIOs or SoC-internal reset controller modules.19 tristate "Altera Arria10 System Resource Reset"22 This option enables support for the external reset functions for26 tristate "ASPEED Reset Driver"30 This enables the reset controller driver for AST2700.33 bool "AR71xx Reset Driver" if COMPILE_TEST[all …]
1 # SPDX-License-Identifier: GPL-2.02 obj-y += core.o3 obj-y += amlogic/4 obj-y += hisilicon/5 obj-y += starfive/6 obj-y += sti/7 obj-y += tegra/8 obj-$(CONFIG_RESET_A10SR) += reset-a10sr.o9 obj-$(CONFIG_RESET_ASPEED) += reset-aspeed.o10 obj-$(CONFIG_RESET_ATH79) += reset-ath79.o[all …]
1 // SPDX-License-Identifier: GPL-2.037 * - rx fifo full38 * - rx fifo above threshold39 * - rx fifo not empty for too long53 * - tx fifo empty54 * - tx fifo below threshold76 return __raw_readl(port->membase + offset); in bcm_uart_readl()82 __raw_writel(value, port->membase + offset); in bcm_uart_writel()221 return (port->type == PORT_BCM63XX) ? "bcm63xx_uart" : NULL; in bcm_uart_type()229 struct tty_port *tty_port = &port->state->port; in bcm_uart_do_rx()[all …]
1 /* SPDX-License-Identifier: GPL-2.0 */90 /* BCM6345 clock bits are shifted by 16 on the left, because of the test91 * control register which is 16-bits wide. That way we do not have any92 * specific BCM6345 code for handling clocks, and writing 0 to the test269 /* Soft Reset register */460 /* Watchdog reset length register */463 /* Watchdog soft reset register (BCM6328 only) */996 /* Endpoint<->DMA mappings */1003 /* Misc per-endpoint settings */1267 #define SPI_6348_CMD 0x00 /* 16-bits register */[all …]