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Searched full:where (Results 1 – 25 of 3457) sorted by relevance

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/linux/drivers/pci/controller/
H A D	pci-thunder-ecam.c	18 static void set_val(u32 v, int where, int size, u32 val) in set_val() argument 20 int shift = (where & 3) 8; in set_val() 22 pr_debug("set_val %04x: %08x\n", (unsigned int)(where & ~3), v); in set_val() 32 unsigned int devfn, int where, int size, u32 val) in handle_ea_bar() argument 38 int where_a = where & 0xc; in handle_ea_bar() 41 set_val(e0, where, size, val); in handle_ea_bar() 52 set_val(v, where, size, val); in handle_ea_bar() 70 set_val(v, where, size, val); in handle_ea_bar() 79 set_val(v, where, size, val); in handle_ea_bar() 86 int where, int size, u32 val) in thunder_ecam_p2_config_read() argument [all …]
H A D	pcie-altera.c	118 int (rp_read_cfg)(struct altera_pcie pcie, int where, 121 int where, int size, u32 value); 123 unsigned int devfn, int where, int size, u32 value); 125 unsigned int devfn, int where, int size, u32 value); 376 int where, u8 byte_en, bool read, u32 headers) in get_tlp_header() argument 390 headers[2] = TLP_CFG_DW2(bus, devfn, where); in get_tlp_header() 394 int where, u8 byte_en, u32 *value) in tlp_cfg_dword_read() argument 398 get_tlp_header(pcie, bus, devfn, where, byte_en, true, in tlp_cfg_dword_read() 407 int where, u8 byte_en, u32 value) in tlp_cfg_dword_write() argument 412 get_tlp_header(pcie, bus, devfn, where, byte_en, false, in tlp_cfg_dword_write() [all …]
/linux/tools/perf/pmu-events/arch/x86/amdzen6/
H A D	load-store.json	96 "BriefDescription": "Demand data cache fills where data is returned from local L2 cache.", 102 …"BriefDescription": "Demand data cache fills where data is returned from L3 cache or different L2 … 108 …"BriefDescription": "Demand data cache fills where data is returned from local L2 cache, L3 cache … 114 …"BriefDescription": "Demand data cache fills where data is returned from cache of another CCX in t… 120 …"BriefDescription": "Demand data cache fills where data is returned from either DRAM or MMIO in th… 126 …"BriefDescription": "Demand data cache fills where data is returned from cache of another CCX in a… 132 …"BriefDescription": "Demand data cache fills where data is returned from cache of another CCX in t… 138 …"BriefDescription": "Demand data cache fills where data is returned from either DRAM or MMIO in a … 144 …"BriefDescription": "Demand data cache fills where data is returned from either DRAM or MMIO in th… 150 …"BriefDescription": "Demand data cache fills where data is returned from either cache of another C… [all …]
H A D	decode.json	5 …"BriefDescription": "Cycles where the op queue is empty. Such cycles indicate that the frontend is… 40 …"BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to int… 46 …"BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to loa… 52 …"BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to sto… 58 …"BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to tak… 64 …"BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to flo… 70 …"BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to una… 76 …"BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to una… 82 …"BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to una… 88 …"BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to una… [all …]
H A D	inst-cache.json	51 "BriefDescription": "Instruction cache fills where data is returned from local L2 cache.", 57 …"BriefDescription": "Instruction cache fills where data is returned from L3 cache or different L2 … 63 …"BriefDescription": "Instruction cache fills where data is returned from local L2 cache, L3 cache … 69 …"BriefDescription": "Instruction cache fills where data is returned from cache of another CCX in t… 75 …"BriefDescription": "Instruction cache fills where data is returned from either DRAM or MMIO in th… 81 …"BriefDescription": "Instruction cache fills where data is returned from cache of another CCX in a… 87 …"BriefDescription": "Instruction cache fills where data is returned from cache of another CCX in t… 93 …"BriefDescription": "Instruction cache fills where data is returned from either DRAM or MMIO in a … 99 …"BriefDescription": "Instruction cache fills where data is returned from either DRAM or MMIO in th… 105 …"BriefDescription": "Instruction cache fills where data is returned from either cache of another C… [all …]
/linux/arch/mips/pci/
H A D	ops-bcm63xx.c	20 static int postprocess_read(u32 data, int where, unsigned int size) in postprocess_read() argument 27 ret = (data >> ((where & 3) << 3)) & 0xff; in postprocess_read() 30 ret = (data >> ((where & 3) << 3)) & 0xffff; in postprocess_read() 39 static int preprocess_write(u32 orig_data, u32 val, int where, in preprocess_write() argument 47 ret = (orig_data & ~(0xff << ((where & 3) << 3))) \| in preprocess_write() 48 (val << ((where & 3) << 3)); in preprocess_write() 51 ret = (orig_data & ~(0xffff << ((where & 3) << 3))) \| in preprocess_write() 52 (val << ((where & 3) << 3)); in preprocess_write() 65 unsigned int devfn, int where) in bcm63xx_setup_cfg_access() argument 72 reg = where >> 2; in bcm63xx_setup_cfg_access() [all …]
H A D	ops-msc.c	34 struct pci_bus bus, unsigned int devfn, int where, u32 data) in msc_pcibios_config_access() argument 47 ((where / 4) << MSC01_PCI_CFGADDR_RNUM_SHF))); in msc_pcibios_config_access() 76 int where, int size, u32 * val) in msc_pcibios_read() argument 80 if ((size == 2) && (where & 1)) in msc_pcibios_read() 82 else if ((size == 4) && (where & 3)) in msc_pcibios_read() 85 if (msc_pcibios_config_access(PCI_ACCESS_READ, bus, devfn, where, in msc_pcibios_read() 90 val = (data >> ((where & 3) << 3)) & 0xff; in msc_pcibios_read() 92 val = (data >> ((where & 3) << 3)) & 0xffff; in msc_pcibios_read() 100 int where, int size, u32 val) in msc_pcibios_write() argument 104 if ((size == 2) && (where & 1)) in msc_pcibios_write() [all …]
H A D	ops-bonito64.c	26 unsigned int devfn, int where, in bonito64_pcibios_config_access() argument 35 int reg = where & ~3; in bonito64_pcibios_config_access() 90 int where, int size, u32 * val) in bonito64_pcibios_read() argument 94 if ((size == 2) && (where & 1)) in bonito64_pcibios_read() 96 else if ((size == 4) && (where & 3)) in bonito64_pcibios_read() 99 if (bonito64_pcibios_config_access(PCI_ACCESS_READ, bus, devfn, where, in bonito64_pcibios_read() 104 val = (data >> ((where & 3) << 3)) & 0xff; in bonito64_pcibios_read() 106 val = (data >> ((where & 3) << 3)) & 0xffff; in bonito64_pcibios_read() 114 int where, int size, u32 val) in bonito64_pcibios_write() argument 118 if ((size == 2) && (where & 1)) in bonito64_pcibios_write() [all …]
H A D	pci-bcm1480ht.c	38 #define CFGOFFSET(bus, devfn, where) (((bus)<<16)+((devfn)<<8)+(where)) argument 39 #define CFGADDR(bus, devfn, where) CFGOFFSET((bus)->number, (devfn), where) argument 97 int where, int size, u32 * val) in bcm1480ht_pcibios_read() argument 101 if ((size == 2) && (where & 1)) in bcm1480ht_pcibios_read() 103 else if ((size == 4) && (where & 3)) in bcm1480ht_pcibios_read() 107 data = READCFG32(CFGADDR(bus, devfn, where)); in bcm1480ht_pcibios_read() 112 val = (data >> ((where & 3) << 3)) & 0xff; in bcm1480ht_pcibios_read() 114 val = (data >> ((where & 3) << 3)) & 0xffff; in bcm1480ht_pcibios_read() 122 int where, int size, u32 val) in bcm1480ht_pcibios_write() argument 124 u32 cfgaddr = CFGADDR(bus, devfn, where); in bcm1480ht_pcibios_write() [all …]
H A D	ops-loongson2.c	34 unsigned int devfn, int where, in loongson_pcibios_config_access() argument 43 int reg = where & ~3; in loongson_pcibios_config_access() 119 int where, int size, u32 val) in loongson_pcibios_read() argument 123 if ((size == 2) && (where & 1)) in loongson_pcibios_read() 125 else if ((size == 4) && (where & 3)) in loongson_pcibios_read() 128 if (loongson_pcibios_config_access(PCI_ACCESS_READ, bus, devfn, where, in loongson_pcibios_read() 133 val = (data >> ((where & 3) << 3)) & 0xff; in loongson_pcibios_read() 135 *val = (data >> ((where & 3) << 3)) & 0xffff; in loongson_pcibios_read() 143 int where, int size, u32 val) in loongson_pcibios_write() argument 147 if ((size == 2) && (where & 1)) in loongson_pcibios_write() [all …]
H A D	ops-lantiq.c	27 unsigned int devfn, unsigned int where, u32 data) in ltq_pci_config_access() argument 43 LTQ_PCI_CFG_FUNNUM_SHF) \| (where & ~0x3); in ltq_pci_config_access() 72 int where, int size, u32 val) in ltq_pci_read_config_dword() argument 76 if (ltq_pci_config_access(PCI_ACCESS_READ, bus, devfn, where, &data)) in ltq_pci_read_config_dword() 80 val = (data >> ((where & 3) << 3)) & 0xff; in ltq_pci_read_config_dword() 82 val = (data >> ((where & 3) << 3)) & 0xffff; in ltq_pci_read_config_dword() 90 int where, int size, u32 val) in ltq_pci_write_config_dword() argument 98 devfn, where, &data)) in ltq_pci_write_config_dword() 102 data = (data & ~(0xff << ((where & 3) << 3))) \| in ltq_pci_write_config_dword() 103 (val << ((where & 3) << 3)); in ltq_pci_write_config_dword() [all …]
H A D	ops-gt64xxx_pci0.c	31 struct pci_bus bus, unsigned int devfn, int where, u32 data) in gt64xxx_pci0_pcibios_config_access() argument 47 ((where / 4) << GT_PCI0_CFGADDR_REGNUM_SHF) \| in gt64xxx_pci0_pcibios_config_access() 92 int where, int size, u32 * val) in gt64xxx_pci0_pcibios_read() argument 97 where, &data)) in gt64xxx_pci0_pcibios_read() 101 val = (data >> ((where & 3) << 3)) & 0xff; in gt64xxx_pci0_pcibios_read() 103 val = (data >> ((where & 3) << 3)) & 0xffff; in gt64xxx_pci0_pcibios_read() 111 int where, int size, u32 val) in gt64xxx_pci0_pcibios_write() argument 119 devfn, where, &data)) in gt64xxx_pci0_pcibios_write() 123 data = (data & ~(0xff << ((where & 3) << 3))) \| in gt64xxx_pci0_pcibios_write() 124 (val << ((where & 3) << 3)); in gt64xxx_pci0_pcibios_write() [all …]
/linux/tools/perf/pmu-events/arch/s390/cf_z13/
H A D	extended.json	7 …"PublicDescription": "A directory write to the Level-1 Data cache where the line was originally in… 42 …"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cac… 63 …"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the retur… 105 …"PublicDescription": "Increments by one for any cycle where a Level-1 cache or Level-1 TLB miss is… 112 …"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cac… 119 …"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cac… 126 …"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cac… 133 …"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cac… 140 …"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cac… 147 …"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cac… [all …]
/linux/tools/perf/pmu-events/arch/arm64/arm/cortex-a510/
H A D	pipeline.json	39 …ration issued due to the backend interlock. This event counts every cycle where the issue of an op… 42 …ration issued due to the backend interlock. This event counts every cycle where the issue of an op… 45 …sued due to the backend, address interlock. This event counts every cycle where the issue of an op… 48 …sued due to the backend, address interlock. This event counts every cycle where the issue of an op… 51 …rlock, or the Vector Processing Unit (VPU). This event counts every cycle where there is a stall o… 54 …rlock, or the Vector Processing Unit (VPU). This event counts every cycle where there is a stall o… 57 … operation issued due to the backend, load. This event counts every cycle where there is a stall i… 60 … operation issued due to the backend, load. This event counts every cycle where there is a stall i… 63 …operation issued due to the backend, store. This event counts every cycle where there is a stall i… 66 …operation issued due to the backend, store. This event counts every cycle where there is a stall i… [all …]
/linux/tools/perf/pmu-events/arch/x86/amdzen2/
H A D	other.json	5 "BriefDescription": "Cycles where the Micro-Op Queue is empty." 28 …"BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a t… 34 …"BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a t… 40 …"BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a t… 46 …"BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a t… 52 …"BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a t… 58 …"BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a t… 64 …"BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a t… 70 …"BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a t… 76 …"BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a t… [all …]
/linux/arch/sh/drivers/pci/
H A D	ops-sh7786.c	20 struct pci_bus bus, unsigned int devfn, int where, u32 data) in sh7786_pcie_config_access() argument 28 reg = where & ~3; in sh7786_pcie_config_access() 90 int where, int size, u32 val) in sh7786_pcie_read() argument 96 if ((size == 2) && (where & 1)) in sh7786_pcie_read() 98 else if ((size == 4) && (where & 3)) in sh7786_pcie_read() 103 devfn, where, &data); in sh7786_pcie_read() 110 val = (data >> ((where & 3) << 3)) & 0xff; in sh7786_pcie_read() 112 val = (data >> ((where & 2) << 3)) & 0xffff; in sh7786_pcie_read() 117 "where=0x%04x size=%d val=0x%08lx\n", bus->number, in sh7786_pcie_read() 118 devfn, where, size, (unsigned long)val); in sh7786_pcie_read() [all …]
/linux/tools/perf/pmu-events/arch/s390/cf_z14/
H A D	extended.json	7 …"PublicDescription": "A directory write to the Level-1 Data cache where the line was originally in… 42 …"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cac… 63 …"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the retur… 105 …"PublicDescription": "Increments by one for any cycle where a level-1 cache or level-2 TLB miss is… 112 …"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cac… 119 …"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cac… 126 …"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cac… 133 …"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cac… 140 …"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cac… 147 …"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cac… [all …]
/linux/arch/sparc/kernel/
H A D	pci_common.c	55 int where, int size, u32 value) in sun4u_read_pci_cfg_host() argument 61 addr = sun4u_config_mkaddr(pbm, bus, devfn, where); in sun4u_read_pci_cfg_host() 67 if (where < 8) { in sun4u_read_pci_cfg_host() 72 if (where & 1) in sun4u_read_pci_cfg_host() 83 if (where < 8) { in sun4u_read_pci_cfg_host() 97 where, 2, &tmp32); in sun4u_read_pci_cfg_host() 102 where + 2, 2, &tmp32); in sun4u_read_pci_cfg_host() 110 int where, int size, u32 value) in sun4u_read_pci_cfg() argument 131 return sun4u_read_pci_cfg_host(pbm, bus, devfn, where, in sun4u_read_pci_cfg() 134 addr = sun4u_config_mkaddr(pbm, bus, devfn, where); in sun4u_read_pci_cfg() [all …]
/linux/rust/syn/gen/
H A D	hash.rs	`13 where in hash() 23 where in hash() 34 where in hash() 48 where in hash() 60 where in hash() 72 where in hash() 89 where in hash() 100 where in hash() 112 where in hash() 124 where in hash() [all …]`
/linux/tools/perf/pmu-events/arch/s390/cf_z15/
H A D	extended.json	7 …"PublicDescription": "A directory write to the Level-1 Data cache where the line was originally in… 42 …"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cac… 63 …"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the retur… 105 …"PublicDescription": "Increments by one for any cycle where a level-1 cache or level-2 TLB miss is… 112 …"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cac… 119 …"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cac… 126 …"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cac… 133 …"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cac… 140 …"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cac… 147 …"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cac… [all …]
/linux/tools/perf/pmu-events/arch/s390/cf_z16/
H A D	extended.json	7 …"PublicDescription": "A directory write to the Level-1 Data cache where the line was originally in… 91 …"PublicDescription": "Increments by one for any cycle where a level-1 cache or level-2 TLB miss is… 98 …"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cac… 105 …"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cac… 112 …"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cac… 119 …"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cac… 126 …"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cac… 133 …"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cac… 140 …"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cac… 147 …"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cac… [all …]
/linux/tools/perf/pmu-events/arch/x86/amdzen3/
H A D	other.json	5 "BriefDescription": "Cycles where the Micro-Op Queue is empty." 22 …"BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a T… 28 …"BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a T… 34 …"BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a T… 40 …"BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a T… 46 …"BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a t… 52 …"BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a T… 58 …"BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a T… 64 …"BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a T… 70 …"BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a t… [all …]
/linux/tools/perf/pmu-events/arch/s390/cf_zec12/
H A D	extended.json	21 …"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cac… 28 …"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the retur… 35 …"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cac… 49 …"PublicDescription": "A directory write to the Level-1 Data cache where the installed cache line w… 56 …"PublicDescription": "A directory write to the Level-1 Instruction cache where the installed cache… 63 …"PublicDescription": "A directory write to the Level-1 Data Cache where the line was originally in… 105 …"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cac… 112 …"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cac… 119 …"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cac… 126 …"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cac… [all …]
/linux/tools/perf/pmu-events/arch/x86/elkhartlake/
H A D	cache.json	323 …"BriefDescription": "Counts all code reads that were supplied by the L3 cache where a snoop was se… 329 …"PublicDescription": "Counts all code reads that were supplied by the L3 cache where a snoop was s… 334 …"BriefDescription": "Counts all code reads that were supplied by the L3 cache where a snoop was se… 340 …"PublicDescription": "Counts all code reads that were supplied by the L3 cache where a snoop was s… 345 …"BriefDescription": "Counts all code reads that were supplied by the L3 cache where a snoop was se… 351 …"PublicDescription": "Counts all code reads that were supplied by the L3 cache where a snoop was s… 356 …"BriefDescription": "Counts all code reads that were supplied by the L3 cache where a snoop was se… 362 …"PublicDescription": "Counts all code reads that were supplied by the L3 cache where a snoop was s… 367 …"BriefDescription": "Counts all code reads that were supplied by the L3 cache where no snoop was n… 373 …"PublicDescription": "Counts all code reads that were supplied by the L3 cache where no snoop was … [all …]
/linux/tools/perf/pmu-events/arch/x86/snowridgex/
H A D	cache.json	323 …"BriefDescription": "Counts all code reads that were supplied by the L3 cache where a snoop was se… 329 …"PublicDescription": "Counts all code reads that were supplied by the L3 cache where a snoop was s… 334 …"BriefDescription": "Counts all code reads that were supplied by the L3 cache where a snoop was se… 340 …"PublicDescription": "Counts all code reads that were supplied by the L3 cache where a snoop was s… 345 …"BriefDescription": "Counts all code reads that were supplied by the L3 cache where a snoop was se… 351 …"PublicDescription": "Counts all code reads that were supplied by the L3 cache where a snoop was s… 356 …"BriefDescription": "Counts all code reads that were supplied by the L3 cache where a snoop was se… 362 …"PublicDescription": "Counts all code reads that were supplied by the L3 cache where a snoop was s… 367 …"BriefDescription": "Counts all code reads that were supplied by the L3 cache where no snoop was n… 373 …"PublicDescription": "Counts all code reads that were supplied by the L3 cache where no snoop was … [all …]

12 3 4 5 6 7 8 9 10 >>...139