1bc17f949SThomas Richter[ 2bc17f949SThomas Richter { 39bacbcedSThomas Richter "Unit": "CPU-M-CF", 4bc17f949SThomas Richter "EventCode": "128", 5bc17f949SThomas Richter "EventName": "L1D_RO_EXCL_WRITES", 6bc17f949SThomas Richter "BriefDescription": "L1D Read-only Exclusive Writes", 7bc17f949SThomas Richter "PublicDescription": "A directory write to the Level-1 Data cache where the line was originally in a Read-Only state in the cache but has been updated to be in the Exclusive state that allows stores to the cache line." 8bc17f949SThomas Richter }, 9bc17f949SThomas Richter { 109bacbcedSThomas Richter "Unit": "CPU-M-CF", 11bc17f949SThomas Richter "EventCode": "129", 12bc17f949SThomas Richter "EventName": "DTLB1_WRITES", 13bc17f949SThomas Richter "BriefDescription": "DTLB1 Writes", 14*e9c26fd6SThomas Richter "PublicDescription": "A translation entry has been written to the Level-1 Data Translation Lookaside Buffer (DTLB1)." 15bc17f949SThomas Richter }, 16bc17f949SThomas Richter { 179bacbcedSThomas Richter "Unit": "CPU-M-CF", 18bc17f949SThomas Richter "EventCode": "130", 19bc17f949SThomas Richter "EventName": "DTLB1_MISSES", 20bc17f949SThomas Richter "BriefDescription": "DTLB1 Misses", 21bc17f949SThomas Richter "PublicDescription": "Level-1 Data TLB miss in progress. Incremented by one for every cycle a DTLB1 miss is in progress." 22bc17f949SThomas Richter }, 23bc17f949SThomas Richter { 249bacbcedSThomas Richter "Unit": "CPU-M-CF", 25bc17f949SThomas Richter "EventCode": "131", 26bc17f949SThomas Richter "EventName": "DTLB1_HPAGE_WRITES", 27bc17f949SThomas Richter "BriefDescription": "DTLB1 One-Megabyte Page Writes", 28*e9c26fd6SThomas Richter "PublicDescription": "A translation entry has been written to the Level-1 Data Translation Lookaside Buffer for a one-megabyte page." 29bc17f949SThomas Richter }, 30bc17f949SThomas Richter { 319bacbcedSThomas Richter "Unit": "CPU-M-CF", 32bc17f949SThomas Richter "EventCode": "132", 33bc17f949SThomas Richter "EventName": "DTLB1_GPAGE_WRITES", 34bc17f949SThomas Richter "BriefDescription": "DTLB1 Two-Gigabyte Page Writes", 3528396b7dSEd Maste "PublicDescription": "A translation entry has been written to the Level-1 Data Translation Lookaside Buffer for a two-gigabyte page." 36bc17f949SThomas Richter }, 37bc17f949SThomas Richter { 389bacbcedSThomas Richter "Unit": "CPU-M-CF", 39bc17f949SThomas Richter "EventCode": "133", 40bc17f949SThomas Richter "EventName": "L1D_L2D_SOURCED_WRITES", 41bc17f949SThomas Richter "BriefDescription": "L1D L2D Sourced Writes", 42*e9c26fd6SThomas Richter "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from the Level-2 Data cache." 43bc17f949SThomas Richter }, 44bc17f949SThomas Richter { 459bacbcedSThomas Richter "Unit": "CPU-M-CF", 46bc17f949SThomas Richter "EventCode": "134", 47bc17f949SThomas Richter "EventName": "ITLB1_WRITES", 48bc17f949SThomas Richter "BriefDescription": "ITLB1 Writes", 49*e9c26fd6SThomas Richter "PublicDescription": "A translation entry has been written to the Level-1 Instruction Translation Lookaside Buffer (ITLB1)." 50bc17f949SThomas Richter }, 51bc17f949SThomas Richter { 529bacbcedSThomas Richter "Unit": "CPU-M-CF", 53bc17f949SThomas Richter "EventCode": "135", 54bc17f949SThomas Richter "EventName": "ITLB1_MISSES", 55bc17f949SThomas Richter "BriefDescription": "ITLB1 Misses", 56*e9c26fd6SThomas Richter "PublicDescription": "Level-1 Instruction TLB miss in progress. Incremented by one for every cycle an ITLB1 miss is in progress." 57bc17f949SThomas Richter }, 58bc17f949SThomas Richter { 599bacbcedSThomas Richter "Unit": "CPU-M-CF", 60bc17f949SThomas Richter "EventCode": "136", 61bc17f949SThomas Richter "EventName": "L1I_L2I_SOURCED_WRITES", 62bc17f949SThomas Richter "BriefDescription": "L1I L2I Sourced Writes", 63*e9c26fd6SThomas Richter "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from the Level-2 Instruction cache." 64bc17f949SThomas Richter }, 65bc17f949SThomas Richter { 669bacbcedSThomas Richter "Unit": "CPU-M-CF", 67bc17f949SThomas Richter "EventCode": "137", 68bc17f949SThomas Richter "EventName": "TLB2_PTE_WRITES", 69bc17f949SThomas Richter "BriefDescription": "TLB2 PTE Writes", 70*e9c26fd6SThomas Richter "PublicDescription": "A translation entry has been written to the Level-2 TLB Page Table Entry arrays." 71bc17f949SThomas Richter }, 72bc17f949SThomas Richter { 739bacbcedSThomas Richter "Unit": "CPU-M-CF", 74bc17f949SThomas Richter "EventCode": "138", 75bc17f949SThomas Richter "EventName": "TLB2_CRSTE_HPAGE_WRITES", 76bc17f949SThomas Richter "BriefDescription": "TLB2 CRSTE One-Megabyte Page Writes", 77*e9c26fd6SThomas Richter "PublicDescription": "A translation entry has been written to the Level-2 TLB Combined Region Segment Table Entry arrays for a one-megabyte large page translation." 78bc17f949SThomas Richter }, 79bc17f949SThomas Richter { 809bacbcedSThomas Richter "Unit": "CPU-M-CF", 81bc17f949SThomas Richter "EventCode": "139", 82bc17f949SThomas Richter "EventName": "TLB2_CRSTE_WRITES", 83bc17f949SThomas Richter "BriefDescription": "TLB2 CRSTE Writes", 84*e9c26fd6SThomas Richter "PublicDescription": "A translation entry has been written to the Level-2 TLB Combined Region Segment Table Entry arrays." 85bc17f949SThomas Richter }, 86bc17f949SThomas Richter { 879bacbcedSThomas Richter "Unit": "CPU-M-CF", 88bc17f949SThomas Richter "EventCode": "140", 89bc17f949SThomas Richter "EventName": "TX_C_TEND", 90bc17f949SThomas Richter "BriefDescription": "Completed TEND instructions in constrained TX mode", 91*e9c26fd6SThomas Richter "PublicDescription": "A TEND instruction has completed in a constrained transactional-execution mode." 92bc17f949SThomas Richter }, 93bc17f949SThomas Richter { 949bacbcedSThomas Richter "Unit": "CPU-M-CF", 95bc17f949SThomas Richter "EventCode": "141", 96bc17f949SThomas Richter "EventName": "TX_NC_TEND", 97bc17f949SThomas Richter "BriefDescription": "Completed TEND instructions in non-constrained TX mode", 98*e9c26fd6SThomas Richter "PublicDescription": "A TEND instruction has completed in a non-constrained transactional-execution mode." 99bc17f949SThomas Richter }, 100bc17f949SThomas Richter { 1019bacbcedSThomas Richter "Unit": "CPU-M-CF", 102bc17f949SThomas Richter "EventCode": "143", 103bc17f949SThomas Richter "EventName": "L1C_TLB1_MISSES", 104bc17f949SThomas Richter "BriefDescription": "L1C TLB1 Misses", 105bc17f949SThomas Richter "PublicDescription": "Increments by one for any cycle where a Level-1 cache or Level-1 TLB miss is in progress." 106bc17f949SThomas Richter }, 107bc17f949SThomas Richter { 1089bacbcedSThomas Richter "Unit": "CPU-M-CF", 109bc17f949SThomas Richter "EventCode": "144", 110bc17f949SThomas Richter "EventName": "L1D_ONCHIP_L3_SOURCED_WRITES", 111bc17f949SThomas Richter "BriefDescription": "L1D On-Chip L3 Sourced Writes", 112*e9c26fd6SThomas Richter "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Chip Level-3 cache without intervention." 113bc17f949SThomas Richter }, 114bc17f949SThomas Richter { 1159bacbcedSThomas Richter "Unit": "CPU-M-CF", 116bc17f949SThomas Richter "EventCode": "145", 117bc17f949SThomas Richter "EventName": "L1D_ONCHIP_L3_SOURCED_WRITES_IV", 118bc17f949SThomas Richter "BriefDescription": "L1D On-Chip L3 Sourced Writes with Intervention", 119*e9c26fd6SThomas Richter "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Chip Level-3 cache with intervention." 120bc17f949SThomas Richter }, 121bc17f949SThomas Richter { 1229bacbcedSThomas Richter "Unit": "CPU-M-CF", 123bc17f949SThomas Richter "EventCode": "146", 124bc17f949SThomas Richter "EventName": "L1D_ONNODE_L4_SOURCED_WRITES", 125bc17f949SThomas Richter "BriefDescription": "L1D On-Node L4 Sourced Writes", 126*e9c26fd6SThomas Richter "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Node Level-4 cache." 127bc17f949SThomas Richter }, 128bc17f949SThomas Richter { 1299bacbcedSThomas Richter "Unit": "CPU-M-CF", 130bc17f949SThomas Richter "EventCode": "147", 131bc17f949SThomas Richter "EventName": "L1D_ONNODE_L3_SOURCED_WRITES_IV", 132bc17f949SThomas Richter "BriefDescription": "L1D On-Node L3 Sourced Writes with Intervention", 133*e9c26fd6SThomas Richter "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Node Level-3 cache with intervention." 134bc17f949SThomas Richter }, 135bc17f949SThomas Richter { 1369bacbcedSThomas Richter "Unit": "CPU-M-CF", 137bc17f949SThomas Richter "EventCode": "148", 138bc17f949SThomas Richter "EventName": "L1D_ONNODE_L3_SOURCED_WRITES", 139bc17f949SThomas Richter "BriefDescription": "L1D On-Node L3 Sourced Writes", 140*e9c26fd6SThomas Richter "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Node Level-3 cache without intervention." 141bc17f949SThomas Richter }, 142bc17f949SThomas Richter { 1439bacbcedSThomas Richter "Unit": "CPU-M-CF", 144bc17f949SThomas Richter "EventCode": "149", 145bc17f949SThomas Richter "EventName": "L1D_ONDRAWER_L4_SOURCED_WRITES", 146bc17f949SThomas Richter "BriefDescription": "L1D On-Drawer L4 Sourced Writes", 147*e9c26fd6SThomas Richter "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Drawer Level-4 cache." 148bc17f949SThomas Richter }, 149bc17f949SThomas Richter { 1509bacbcedSThomas Richter "Unit": "CPU-M-CF", 151bc17f949SThomas Richter "EventCode": "150", 152bc17f949SThomas Richter "EventName": "L1D_ONDRAWER_L3_SOURCED_WRITES_IV", 153bc17f949SThomas Richter "BriefDescription": "L1D On-Drawer L3 Sourced Writes with Intervention", 154*e9c26fd6SThomas Richter "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Drawer Level-3 cache with intervention." 155bc17f949SThomas Richter }, 156bc17f949SThomas Richter { 1579bacbcedSThomas Richter "Unit": "CPU-M-CF", 158bc17f949SThomas Richter "EventCode": "151", 159bc17f949SThomas Richter "EventName": "L1D_ONDRAWER_L3_SOURCED_WRITES", 160bc17f949SThomas Richter "BriefDescription": "L1D On-Drawer L3 Sourced Writes", 161*e9c26fd6SThomas Richter "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Drawer Level-3 cache without intervention." 162bc17f949SThomas Richter }, 163bc17f949SThomas Richter { 1649bacbcedSThomas Richter "Unit": "CPU-M-CF", 165bc17f949SThomas Richter "EventCode": "152", 166bc17f949SThomas Richter "EventName": "L1D_OFFDRAWER_SCOL_L4_SOURCED_WRITES", 167bc17f949SThomas Richter "BriefDescription": "L1D Off-Drawer Same-Column L4 Sourced Writes", 168*e9c26fd6SThomas Richter "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off-Drawer Same-Column Level-4 cache." 169bc17f949SThomas Richter }, 170bc17f949SThomas Richter { 1719bacbcedSThomas Richter "Unit": "CPU-M-CF", 172bc17f949SThomas Richter "EventCode": "153", 173bc17f949SThomas Richter "EventName": "L1D_OFFDRAWER_SCOL_L3_SOURCED_WRITES_IV", 174bc17f949SThomas Richter "BriefDescription": "L1D Off-Drawer Same-Column L3 Sourced Writes with Intervention", 175*e9c26fd6SThomas Richter "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off-Drawer Same-Column Level-3 cache with intervention." 176bc17f949SThomas Richter }, 177bc17f949SThomas Richter { 1789bacbcedSThomas Richter "Unit": "CPU-M-CF", 179bc17f949SThomas Richter "EventCode": "154", 180bc17f949SThomas Richter "EventName": "L1D_OFFDRAWER_SCOL_L3_SOURCED_WRITES", 181bc17f949SThomas Richter "BriefDescription": "L1D Off-Drawer Same-Column L3 Sourced Writes", 182*e9c26fd6SThomas Richter "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off-Drawer Same-Column Level-3 cache without intervention." 183bc17f949SThomas Richter }, 184bc17f949SThomas Richter { 1859bacbcedSThomas Richter "Unit": "CPU-M-CF", 186bc17f949SThomas Richter "EventCode": "155", 187bc17f949SThomas Richter "EventName": "L1D_OFFDRAWER_FCOL_L4_SOURCED_WRITES", 188bc17f949SThomas Richter "BriefDescription": "L1D Off-Drawer Far-Column L3 Sourced Writes", 189*e9c26fd6SThomas Richter "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off-Drawer Far-Column Level-4 cache." 190bc17f949SThomas Richter }, 191bc17f949SThomas Richter { 1929bacbcedSThomas Richter "Unit": "CPU-M-CF", 193bc17f949SThomas Richter "EventCode": "156", 194bc17f949SThomas Richter "EventName": "L1D_OFFDRAWER_FCOL_L3_SOURCED_WRITES_IV", 195bc17f949SThomas Richter "BriefDescription": "L1D Off-Drawer Far-Column L3 Sourced Writes with Intervention", 196*e9c26fd6SThomas Richter "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off-Drawer Far-Column Level-3 cache with intervention." 197bc17f949SThomas Richter }, 198bc17f949SThomas Richter { 1999bacbcedSThomas Richter "Unit": "CPU-M-CF", 200bc17f949SThomas Richter "EventCode": "157", 201bc17f949SThomas Richter "EventName": "L1D_OFFDRAWER_FCOL_L3_SOURCED_WRITES", 202bc17f949SThomas Richter "BriefDescription": "L1D Off-Drawer Far-Column L3 Sourced Writes", 203*e9c26fd6SThomas Richter "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off-Drawer Far-Column Level-3 cache without intervention." 204bc17f949SThomas Richter }, 205bc17f949SThomas Richter { 2069bacbcedSThomas Richter "Unit": "CPU-M-CF", 207bc17f949SThomas Richter "EventCode": "158", 208bc17f949SThomas Richter "EventName": "L1D_ONNODE_MEM_SOURCED_WRITES", 209bc17f949SThomas Richter "BriefDescription": "L1D On-Node Memory Sourced Writes", 210*e9c26fd6SThomas Richter "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from On-Node memory." 211bc17f949SThomas Richter }, 212bc17f949SThomas Richter { 2139bacbcedSThomas Richter "Unit": "CPU-M-CF", 214bc17f949SThomas Richter "EventCode": "159", 215bc17f949SThomas Richter "EventName": "L1D_ONDRAWER_MEM_SOURCED_WRITES", 216bc17f949SThomas Richter "BriefDescription": "L1D On-Drawer Memory Sourced Writes", 217*e9c26fd6SThomas Richter "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from On-Drawer memory." 218bc17f949SThomas Richter }, 219bc17f949SThomas Richter { 2209bacbcedSThomas Richter "Unit": "CPU-M-CF", 221bc17f949SThomas Richter "EventCode": "160", 222bc17f949SThomas Richter "EventName": "L1D_OFFDRAWER_MEM_SOURCED_WRITES", 223bc17f949SThomas Richter "BriefDescription": "L1D Off-Drawer Memory Sourced Writes", 224*e9c26fd6SThomas Richter "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from Off-Drawer memory." 225bc17f949SThomas Richter }, 226bc17f949SThomas Richter { 2279bacbcedSThomas Richter "Unit": "CPU-M-CF", 228bc17f949SThomas Richter "EventCode": "161", 229bc17f949SThomas Richter "EventName": "L1D_ONCHIP_MEM_SOURCED_WRITES", 230bc17f949SThomas Richter "BriefDescription": "L1D On-Chip Memory Sourced Writes", 231*e9c26fd6SThomas Richter "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from On-Chip memory." 232bc17f949SThomas Richter }, 233bc17f949SThomas Richter { 2349bacbcedSThomas Richter "Unit": "CPU-M-CF", 235bc17f949SThomas Richter "EventCode": "162", 236bc17f949SThomas Richter "EventName": "L1I_ONCHIP_L3_SOURCED_WRITES", 237bc17f949SThomas Richter "BriefDescription": "L1I On-Chip L3 Sourced Writes", 238*e9c26fd6SThomas Richter "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Chip Level-3 cache without intervention." 239bc17f949SThomas Richter }, 240bc17f949SThomas Richter { 2419bacbcedSThomas Richter "Unit": "CPU-M-CF", 242bc17f949SThomas Richter "EventCode": "163", 243bc17f949SThomas Richter "EventName": "L1I_ONCHIP_L3_SOURCED_WRITES_IV", 244bc17f949SThomas Richter "BriefDescription": "L1I On-Chip L3 Sourced Writes with Intervention", 245*e9c26fd6SThomas Richter "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On Chip Level-3 cache with intervention." 246bc17f949SThomas Richter }, 247bc17f949SThomas Richter { 2489bacbcedSThomas Richter "Unit": "CPU-M-CF", 249bc17f949SThomas Richter "EventCode": "164", 250bc17f949SThomas Richter "EventName": "L1I_ONNODE_L4_SOURCED_WRITES", 251bc17f949SThomas Richter "BriefDescription": "L1I On-Chip L4 Sourced Writes", 252*e9c26fd6SThomas Richter "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Node Level-4 cache." 253bc17f949SThomas Richter }, 254bc17f949SThomas Richter { 2559bacbcedSThomas Richter "Unit": "CPU-M-CF", 256bc17f949SThomas Richter "EventCode": "165", 257bc17f949SThomas Richter "EventName": "L1I_ONNODE_L3_SOURCED_WRITES_IV", 258bc17f949SThomas Richter "BriefDescription": "L1I On-Node L3 Sourced Writes with Intervention", 259*e9c26fd6SThomas Richter "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Node Level-3 cache with intervention." 260bc17f949SThomas Richter }, 261bc17f949SThomas Richter { 2629bacbcedSThomas Richter "Unit": "CPU-M-CF", 263bc17f949SThomas Richter "EventCode": "166", 264bc17f949SThomas Richter "EventName": "L1I_ONNODE_L3_SOURCED_WRITES", 265bc17f949SThomas Richter "BriefDescription": "L1I On-Node L3 Sourced Writes", 266*e9c26fd6SThomas Richter "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Node Level-3 cache without intervention." 267bc17f949SThomas Richter }, 268bc17f949SThomas Richter { 2699bacbcedSThomas Richter "Unit": "CPU-M-CF", 270bc17f949SThomas Richter "EventCode": "167", 271bc17f949SThomas Richter "EventName": "L1I_ONDRAWER_L4_SOURCED_WRITES", 272bc17f949SThomas Richter "BriefDescription": "L1I On-Drawer L4 Sourced Writes", 273*e9c26fd6SThomas Richter "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Drawer Level-4 cache." 274bc17f949SThomas Richter }, 275bc17f949SThomas Richter { 2769bacbcedSThomas Richter "Unit": "CPU-M-CF", 277bc17f949SThomas Richter "EventCode": "168", 278bc17f949SThomas Richter "EventName": "L1I_ONDRAWER_L3_SOURCED_WRITES_IV", 279bc17f949SThomas Richter "BriefDescription": "L1I On-Drawer L3 Sourced Writes with Intervention", 280*e9c26fd6SThomas Richter "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Drawer Level-3 cache with intervention." 281bc17f949SThomas Richter }, 282bc17f949SThomas Richter { 2839bacbcedSThomas Richter "Unit": "CPU-M-CF", 284bc17f949SThomas Richter "EventCode": "169", 285bc17f949SThomas Richter "EventName": "L1I_ONDRAWER_L3_SOURCED_WRITES", 286bc17f949SThomas Richter "BriefDescription": "L1I On-Drawer L3 Sourced Writes", 287*e9c26fd6SThomas Richter "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Drawer Level-3 cache without intervention." 288bc17f949SThomas Richter }, 289bc17f949SThomas Richter { 2909bacbcedSThomas Richter "Unit": "CPU-M-CF", 291bc17f949SThomas Richter "EventCode": "170", 292bc17f949SThomas Richter "EventName": "L1I_OFFDRAWER_SCOL_L4_SOURCED_WRITES", 293bc17f949SThomas Richter "BriefDescription": "L1I Off-Drawer Same-Column L4 Sourced Writes", 294*e9c26fd6SThomas Richter "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off-Drawer Same-Column Level-4 cache." 295bc17f949SThomas Richter }, 296bc17f949SThomas Richter { 2979bacbcedSThomas Richter "Unit": "CPU-M-CF", 298bc17f949SThomas Richter "EventCode": "171", 299bc17f949SThomas Richter "EventName": "L1I_OFFDRAWER_SCOL_L3_SOURCED_WRITES_IV", 300bc17f949SThomas Richter "BriefDescription": "L1I Off-Drawer Same-Column L3 Sourced Writes with Intervention", 301*e9c26fd6SThomas Richter "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off-Drawer Same-Column Level-3 cache with intervention." 302bc17f949SThomas Richter }, 303bc17f949SThomas Richter { 3049bacbcedSThomas Richter "Unit": "CPU-M-CF", 305bc17f949SThomas Richter "EventCode": "172", 306bc17f949SThomas Richter "EventName": "L1I_OFFDRAWER_SCOL_L3_SOURCED_WRITES", 307bc17f949SThomas Richter "BriefDescription": "L1I Off-Drawer Same-Column L3 Sourced Writes", 308*e9c26fd6SThomas Richter "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off-Drawer Same-Column Level-3 cache without intervention." 309bc17f949SThomas Richter }, 310bc17f949SThomas Richter { 3119bacbcedSThomas Richter "Unit": "CPU-M-CF", 312bc17f949SThomas Richter "EventCode": "173", 313bc17f949SThomas Richter "EventName": "L1I_OFFDRAWER_FCOL_L4_SOURCED_WRITES", 314bc17f949SThomas Richter "BriefDescription": "L1I Off-Drawer Far-Column L4 Sourced Writes", 315*e9c26fd6SThomas Richter "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off-Drawer Far-Column Level-4 cache." 316bc17f949SThomas Richter }, 317bc17f949SThomas Richter { 3189bacbcedSThomas Richter "Unit": "CPU-M-CF", 319bc17f949SThomas Richter "EventCode": "174", 320bc17f949SThomas Richter "EventName": "L1I_OFFDRAWER_FCOL_L3_SOURCED_WRITES_IV", 321bc17f949SThomas Richter "BriefDescription": "L1I Off-Drawer Far-Column L3 Sourced Writes with Intervention", 322*e9c26fd6SThomas Richter "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off-Drawer Far-Column Level-3 cache with intervention." 323bc17f949SThomas Richter }, 324bc17f949SThomas Richter { 3259bacbcedSThomas Richter "Unit": "CPU-M-CF", 326bc17f949SThomas Richter "EventCode": "175", 327bc17f949SThomas Richter "EventName": "L1I_OFFDRAWER_FCOL_L3_SOURCED_WRITES", 328bc17f949SThomas Richter "BriefDescription": "L1I Off-Drawer Far-Column L3 Sourced Writes", 329*e9c26fd6SThomas Richter "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off-Drawer Far-Column Level-3 cache without intervention." 330bc17f949SThomas Richter }, 331bc17f949SThomas Richter { 3329bacbcedSThomas Richter "Unit": "CPU-M-CF", 333bc17f949SThomas Richter "EventCode": "176", 334bc17f949SThomas Richter "EventName": "L1I_ONNODE_MEM_SOURCED_WRITES", 335bc17f949SThomas Richter "BriefDescription": "L1I On-Node Memory Sourced Writes", 336*e9c26fd6SThomas Richter "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from On-Node memory." 337bc17f949SThomas Richter }, 338bc17f949SThomas Richter { 3399bacbcedSThomas Richter "Unit": "CPU-M-CF", 340bc17f949SThomas Richter "EventCode": "177", 341bc17f949SThomas Richter "EventName": "L1I_ONDRAWER_MEM_SOURCED_WRITES", 342bc17f949SThomas Richter "BriefDescription": "L1I On-Drawer Memory Sourced Writes", 343*e9c26fd6SThomas Richter "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from On-Drawer memory." 344bc17f949SThomas Richter }, 345bc17f949SThomas Richter { 3469bacbcedSThomas Richter "Unit": "CPU-M-CF", 347bc17f949SThomas Richter "EventCode": "178", 348bc17f949SThomas Richter "EventName": "L1I_OFFDRAWER_MEM_SOURCED_WRITES", 349bc17f949SThomas Richter "BriefDescription": "L1I Off-Drawer Memory Sourced Writes", 350*e9c26fd6SThomas Richter "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from On-Drawer memory." 351bc17f949SThomas Richter }, 352bc17f949SThomas Richter { 3539bacbcedSThomas Richter "Unit": "CPU-M-CF", 354bc17f949SThomas Richter "EventCode": "179", 355bc17f949SThomas Richter "EventName": "L1I_ONCHIP_MEM_SOURCED_WRITES", 356bc17f949SThomas Richter "BriefDescription": "L1I On-Chip Memory Sourced Writes", 357*e9c26fd6SThomas Richter "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from On-Chip memory." 358bc17f949SThomas Richter }, 359bc17f949SThomas Richter { 3609bacbcedSThomas Richter "Unit": "CPU-M-CF", 361bc17f949SThomas Richter "EventCode": "218", 362bc17f949SThomas Richter "EventName": "TX_NC_TABORT", 363bc17f949SThomas Richter "BriefDescription": "Aborted transactions in non-constrained TX mode", 364*e9c26fd6SThomas Richter "PublicDescription": "A transaction abort has occurred in a non-constrained transactional-execution mode." 365bc17f949SThomas Richter }, 366bc17f949SThomas Richter { 3679bacbcedSThomas Richter "Unit": "CPU-M-CF", 368bc17f949SThomas Richter "EventCode": "219", 369bc17f949SThomas Richter "EventName": "TX_C_TABORT_NO_SPECIAL", 370bc17f949SThomas Richter "BriefDescription": "Aborted transactions in constrained TX mode not using special completion logic", 371*e9c26fd6SThomas Richter "PublicDescription": "A transaction abort has occurred in a constrained transactional-execution mode and the CPU is not using any special logic to allow the transaction to complete." 372bc17f949SThomas Richter }, 373bc17f949SThomas Richter { 3749bacbcedSThomas Richter "Unit": "CPU-M-CF", 375bc17f949SThomas Richter "EventCode": "220", 376bc17f949SThomas Richter "EventName": "TX_C_TABORT_SPECIAL", 377bc17f949SThomas Richter "BriefDescription": "Aborted transactions in constrained TX mode using special completion logic", 378*e9c26fd6SThomas Richter "PublicDescription": "A transaction abort has occurred in a constrained transactional-execution mode and the CPU is using special logic to allow the transaction to complete." 379bc17f949SThomas Richter }, 380bc17f949SThomas Richter { 3819bacbcedSThomas Richter "Unit": "CPU-M-CF", 382bc17f949SThomas Richter "EventCode": "448", 383bc17f949SThomas Richter "EventName": "MT_DIAG_CYCLES_ONE_THR_ACTIVE", 384bc17f949SThomas Richter "BriefDescription": "Cycle count with one thread active", 385bc17f949SThomas Richter "PublicDescription": "Cycle count with one thread active" 386bc17f949SThomas Richter }, 387bc17f949SThomas Richter { 3889bacbcedSThomas Richter "Unit": "CPU-M-CF", 389bc17f949SThomas Richter "EventCode": "449", 390bc17f949SThomas Richter "EventName": "MT_DIAG_CYCLES_TWO_THR_ACTIVE", 391bc17f949SThomas Richter "BriefDescription": "Cycle count with two threads active", 392bc17f949SThomas Richter "PublicDescription": "Cycle count with two threads active" 39308f3e087SJames Clark } 394bc17f949SThomas Richter] 395