xref: /linux/tools/perf/pmu-events/arch/x86/amdzen6/load-store.json (revision c7decec2f2d2ab0366567f9e30c0e1418cece43f) 
1[
2  {
3    "EventName": "ls_bad_status2.stli_other",
4    "EventCode": "0x24",
5    "BriefDescription": "Store-to-load conflicts (loads unable to complete due to a non-forwardable conflict with an older store).",
6    "UMask": "0x02"
7  },
8  {
9    "EventName": "ls_locks.bus_lock",
10    "EventCode": "0x25",
11    "BriefDescription": "Retired lock instructions which caused a bus lock (non-cacheable or cache-misaligned lock).",
12    "UMask": "0x01"
13  },
14  {
15    "EventName": "ls_locks.all",
16    "EventCode": "0x25",
17    "BriefDescription": "Retired lock instructions of all types.",
18    "UMask": "0x1f"
19  },
20  {
21    "EventName": "ls_ret_cl_flush",
22    "EventCode": "0x26",
23    "BriefDescription": "Retired CLFLUSH instructions."
24  },
25  {
26    "EventName": "ls_ret_cpuid",
27    "EventCode": "0x27",
28    "BriefDescription": "Retired CPUID instructions."
29  },
30  {
31    "EventName": "ls_dispatch.pure_ld",
32    "EventCode": "0x29",
33    "BriefDescription": "Memory load operations dispatched to the load-store unit.",
34    "UMask": "0x01"
35  },
36  {
37    "EventName": "ls_dispatch.pure_st",
38    "EventCode": "0x29",
39    "BriefDescription": "Memory store operations dispatched to the load-store unit.",
40    "UMask": "0x02"
41  },
42  {
43    "EventName": "ls_dispatch.ld_st",
44    "EventCode": "0x29",
45    "BriefDescription": "Memory load-store operations (load from and store to the same memory address) dispatched to the load-store unit.",
46    "UMask": "0x04"
47  },
48  {
49    "EventName": "ls_dispatch.all",
50    "EventCode": "0x29",
51    "BriefDescription": "Memory operations dispatched to the load-store unit of all types.",
52    "UMask": "0x07"
53  },
54  {
55    "EventName": "ls_smi_rx",
56    "EventCode": "0x2b",
57    "BriefDescription": "System Management Interrupts (SMIs) received."
58  },
59  {
60    "EventName": "ls_int_taken",
61    "EventCode": "0x2c",
62    "BriefDescription": "Interrupts taken."
63  },
64  {
65    "EventName": "ls_stlf",
66    "EventCode": "0x35",
67    "BriefDescription": "Store-to-load-forward (STLF) hits."
68  },
69  {
70    "EventName": "ls_st_commit_cancel.older_st_vis_dep",
71    "EventCode": "0x37",
72    "BriefDescription": "Store commits cancelled due to an older store, that the thread was waiting on to become globally visible, was unable to become globally visible.",
73    "UMask": "0x01"
74  },
75  {
76    "EventName": "ls_mab_alloc.ls",
77    "EventCode": "0x41",
78    "BriefDescription": "Miss Address Buffer (MAB) entries allocated by a Load-Store (LS) pipe for load-store allocations.",
79    "UMask": "0x07"
80  },
81  {
82    "EventName": "ls_mab_alloc.hwpf",
83    "EventCode": "0x41",
84    "BriefDescription": "Miss Address Buffer (MAB) entries allocated by a Load-Store (LS) pipe for hardware prefetcher allocations.",
85    "UMask": "0x08"
86  },
87  {
88    "EventName": "ls_mab_alloc.all",
89    "EventCode": "0x41",
90    "BriefDescription": "Miss Address Buffer (MAB) entries allocated by a Load-Store (LS) pipe for all types of allocations.",
91    "UMask": "0x0f"
92  },
93  {
94    "EventName": "ls_dmnd_fills_from_sys.local_l2",
95    "EventCode": "0x43",
96    "BriefDescription": "Demand data cache fills where data is returned from local L2 cache.",
97    "UMask": "0x01"
98  },
99  {
100    "EventName": "ls_dmnd_fills_from_sys.local_ccx",
101    "EventCode": "0x43",
102    "BriefDescription": "Demand data cache fills where data is returned from L3 cache or different L2 cache in the same CCX.",
103    "UMask": "0x02"
104  },
105  {
106    "EventName": "ls_dmnd_fills_from_sys.local_all",
107    "EventCode": "0x43",
108    "BriefDescription": "Demand data cache fills where data is returned from local L2 cache, L3 cache or different L2 cache in the same CCX.",
109    "UMask": "0x03"
110  },
111  {
112    "EventName": "ls_dmnd_fills_from_sys.near_cache",
113    "EventCode": "0x43",
114    "BriefDescription": "Demand data cache fills where data is returned from cache of another CCX in the same NUMA node.",
115    "UMask": "0x04"
116  },
117  {
118    "EventName": "ls_dmnd_fills_from_sys.dram_io_near",
119    "EventCode": "0x43",
120    "BriefDescription": "Demand data cache fills where data is returned from either DRAM or MMIO in the same NUMA node.",
121    "UMask": "0x08"
122  },
123  {
124    "EventName": "ls_dmnd_fills_from_sys.far_cache",
125    "EventCode": "0x43",
126    "BriefDescription": "Demand data cache fills where data is returned from cache of another CCX in a different NUMA node.",
127    "UMask": "0x10"
128  },
129  {
130    "EventName": "ls_dmnd_fills_from_sys.remote_cache",
131    "EventCode": "0x43",
132    "BriefDescription": "Demand data cache fills where data is returned from cache of another CCX in the same or a different NUMA node.",
133    "UMask": "0x14"
134  },
135  {
136    "EventName": "ls_dmnd_fills_from_sys.dram_io_far",
137    "EventCode": "0x43",
138    "BriefDescription": "Demand data cache fills where data is returned from either DRAM or MMIO in a different NUMA node.",
139    "UMask": "0x40"
140  },
141  {
142    "EventName": "ls_dmnd_fills_from_sys.dram_io_all",
143    "EventCode": "0x43",
144    "BriefDescription": "Demand data cache fills where data is returned from either DRAM or MMIO in the same or a different NUMA node.",
145    "UMask": "0x48"
146  },
147  {
148    "EventName": "ls_dmnd_fills_from_sys.far_all",
149    "EventCode": "0x43",
150    "BriefDescription": "Demand data cache fills where data is returned from either cache of another CCX, DRAM or MMIO in a different NUMA node.",
151    "UMask": "0x50"
152  },
153  {
154    "EventName": "ls_dmnd_fills_from_sys.alt_mem",
155    "EventCode": "0x43",
156    "BriefDescription": "Demand data cache fills where data is returned from extension memory (CXL).",
157    "UMask": "0x80"
158  },
159  {
160    "EventName": "ls_dmnd_fills_from_sys.all",
161    "EventCode": "0x43",
162    "BriefDescription": "Demand data cache fills where data is returned from all types of sources.",
163    "UMask": "0xdf"
164  },
165  {
166    "EventName": "ls_any_fills_from_sys.local_l2",
167    "EventCode": "0x44",
168    "BriefDescription": "Any data cache fills where data is returned from local L2 cache.",
169    "UMask": "0x01"
170  },
171  {
172    "EventName": "ls_any_fills_from_sys.local_ccx",
173    "EventCode": "0x44",
174    "BriefDescription": "Any data cache fills where data is returned from L3 cache or different L2 cache in the same CCX.",
175    "UMask": "0x02"
176  },
177  {
178    "EventName": "ls_any_fills_from_sys.local_all",
179    "EventCode": "0x44",
180    "BriefDescription": "Any data cache fills where data is returned from local L2 cache, L3 cache or different L2 cache in the same CCX.",
181    "UMask": "0x03"
182  },
183  {
184    "EventName": "ls_any_fills_from_sys.near_cache",
185    "EventCode": "0x44",
186    "BriefDescription": "Any data cache fills where data is returned from cache of another CCX in the same NUMA node.",
187    "UMask": "0x04"
188  },
189  {
190    "EventName": "ls_any_fills_from_sys.dram_io_near",
191    "EventCode": "0x44",
192    "BriefDescription": "Any data cache fills where data is returned from either DRAM or MMIO in the same NUMA node.",
193    "UMask": "0x08"
194  },
195  {
196    "EventName": "ls_any_fills_from_sys.far_cache",
197    "EventCode": "0x44",
198    "BriefDescription": "Any data cache fills where data is returned from cache of another CCX in a different NUMA node.",
199    "UMask": "0x10"
200  },
201  {
202    "EventName": "ls_any_fills_from_sys.remote_cache",
203    "EventCode": "0x44",
204    "BriefDescription": "Any data cache fills where data is returned from cache of another CCX in the same or a different NUMA node.",
205    "UMask": "0x14"
206  },
207  {
208    "EventName": "ls_any_fills_from_sys.dram_io_far",
209    "EventCode": "0x44",
210    "BriefDescription": "Any data cache fills where data is returned from either DRAM or MMIO in a different NUMA node.",
211    "UMask": "0x40"
212  },
213  {
214    "EventName": "ls_any_fills_from_sys.dram_io_all",
215    "EventCode": "0x44",
216    "BriefDescription": "Any data cache fills where data is returned from either DRAM or MMIO in the same or a different NUMA node.",
217    "UMask": "0x48"
218  },
219  {
220    "EventName": "ls_any_fills_from_sys.far_all",
221    "EventCode": "0x44",
222    "BriefDescription": "Any data cache fills where data is returned from either cache of another CCX, DRAM or MMIO when the address was in a different NUMA node.",
223    "UMask": "0x50"
224  },
225  {
226    "EventName": "ls_any_fills_from_sys.alt_mem",
227    "EventCode": "0x44",
228    "BriefDescription": "Any data cache fills where data is returned from extension memory (CXL).",
229    "UMask": "0x80"
230  },
231  {
232    "EventName": "ls_any_fills_from_sys.all",
233    "EventCode": "0x44",
234    "BriefDescription": "Any data cache fills where data is returned from all types of data sources.",
235    "UMask": "0xff"
236  },
237  {
238    "EventName": "ls_l1_d_tlb_miss.tlb_reload_4k_l2_hit",
239    "EventCode": "0x45",
240    "BriefDescription": "L1 DTLB misses with L2 DTLB hits for 4k pages.",
241    "UMask": "0x01"
242  },
243  {
244    "EventName": "ls_l1_d_tlb_miss.tlb_reload_coalesced_page_hit",
245    "EventCode": "0x45",
246    "BriefDescription": "L1 DTLB misses with L2 DTLB hits for coalesced pages (16k pages created from four adjacent 4k pages).",
247    "UMask": "0x02"
248  },
249  {
250    "EventName": "ls_l1_d_tlb_miss.tlb_reload_2m_l2_hit",
251    "EventCode": "0x45",
252    "BriefDescription": "L1 DTLB misses with L2 DTLB hits for 2M pages.",
253    "UMask": "0x04"
254  },
255  {
256    "EventName": "ls_l1_d_tlb_miss.tlb_reload_1g_l2_hit",
257    "EventCode": "0x45",
258    "BriefDescription": "L1 DTLB misses with L2 DTLB hits for 1G pages.",
259    "UMask": "0x08"
260  },
261  {
262    "EventName": "ls_l1_d_tlb_miss.tlb_reload_4k_l2_miss",
263    "EventCode": "0x45",
264    "BriefDescription": "L1 DTLB misses with L2 DTLB misses (page-table walks requested) for 4k pages.",
265    "UMask": "0x10"
266  },
267  {
268    "EventName": "ls_l1_d_tlb_miss.tlb_reload_coalesced_page_miss",
269    "EventCode": "0x45",
270    "BriefDescription": "L1 DTLB misses with L2 DTLB misses (page-table walks requested) for coalesced pages (16k pages created from four adjacent 4k pages).",
271    "UMask": "0x20"
272  },
273  {
274    "EventName": "ls_l1_d_tlb_miss.tlb_reload_2m_l2_miss",
275    "EventCode": "0x45",
276    "BriefDescription": "L1 DTLB misses with L2 DTLB misses (page-table walks requested) for 2M pages.",
277    "UMask": "0x40"
278  },
279  {
280    "EventName": "ls_l1_d_tlb_miss.tlb_reload_1g_l2_miss",
281    "EventCode": "0x45",
282    "BriefDescription": "L1 DTLB misses with L2 DTLB misses (page-table walks requested) for 1G pages.",
283    "UMask": "0x80"
284  },
285  {
286    "EventName": "ls_l1_d_tlb_miss.l2_miss_all",
287    "EventCode": "0x45",
288    "BriefDescription": "L1 DTLB misses with L2 DTLB misses (page-table walks requested) for all page sizes.",
289    "UMask": "0xf0"
290  },
291  {
292    "EventName": "ls_l1_d_tlb_miss.all",
293    "EventCode": "0x45",
294    "BriefDescription": "L1 DTLB misses for all page sizes.",
295    "UMask": "0xff"
296  },
297  {
298    "EventName": "ls_misal_loads.ma64",
299    "EventCode": "0x47",
300    "BriefDescription": "64B misaligned (cacheline crossing) loads.",
301    "UMask": "0x01"
302  },
303  {
304    "EventName": "ls_misal_loads.ma4k",
305    "EventCode": "0x47",
306    "BriefDescription": "4kB misaligned (page crossing) loads.",
307    "UMask": "0x02"
308  },
309  {
310    "EventName": "ls_pref_instr_disp.prefetch",
311    "EventCode": "0x4b",
312    "BriefDescription": "Software prefetch instructions dispatched (speculative) of type PrefetchT0 (move data to all cache levels), T1 (move data to all cache levels except L1) and T2 (move data to all cache levels except L1 and L2).",
313    "UMask": "0x01"
314  },
315  {
316    "EventName": "ls_pref_instr_disp.prefetch_w",
317    "EventCode": "0x4b",
318    "BriefDescription": "Software prefetch instructions dispatched (speculative) of type PrefetchW (move data to L1 cache and mark it modifiable).",
319    "UMask": "0x02"
320  },
321  {
322    "EventName": "ls_pref_instr_disp.prefetch_nta",
323    "EventCode": "0x4b",
324    "BriefDescription": "Software prefetch instructions dispatched (speculative) of type PrefetchNTA (move data with minimum cache pollution i.e. non-temporal access).",
325    "UMask": "0x04"
326  },
327  {
328    "EventName": "ls_pref_instr_disp.all",
329    "EventCode": "0x4b",
330    "BriefDescription": "Software prefetch instructions dispatched (speculative) of all types.",
331    "UMask": "0x07"
332  },
333  {
334    "EventName": "wcb_close.full_line_64b",
335    "EventCode": "0x50",
336    "BriefDescription": "Events that caused a Write Combining Buffer (WCB) entry to close because all 64 bytes of the entry have been written to.",
337    "UMask": "0x01"
338  },
339  {
340    "EventName": "ls_inef_sw_pref.dc_hit",
341    "EventCode": "0x52",
342    "BriefDescription": "Software prefetches that did not fetch data outside of the processor core as the PREFETCH instruction saw a data cache hit.",
343    "UMask": "0x01"
344  },
345  {
346    "EventName": "ls_inef_sw_pref.mab_hit",
347    "EventCode": "0x52",
348    "BriefDescription": "Software prefetches that did not fetch data outside of the processor core as the PREFETCH instruction saw a match on an already allocated miss request (MAB).",
349    "UMask": "0x02"
350  },
351  {
352    "EventName": "ls_inef_sw_pref.all",
353    "EventCode": "0x52",
354    "BriefDescript6ion": "Software prefetches that did not fetch data outside of the processor core for any reason.",
355    "UMask": "0x03"
356  },
357  {
358    "EventName": "ls_sw_pf_dc_fills.local_l2",
359    "EventCode": "0x59",
360    "BriefDescription": "Software prefetch data cache fills where data is returned from local L2 cache.",
361    "UMask": "0x01"
362  },
363  {
364    "EventName": "ls_sw_pf_dc_fills.local_ccx",
365    "EventCode": "0x59",
366    "BriefDescription": "Software prefetch data cache fills where data is returned from L3 cache or different L2 cache in the same CCX.",
367    "UMask": "0x02"
368  },
369  {
370    "EventName": "ls_sw_pf_dc_fills.local_all",
371    "EventCode": "0x59",
372    "BriefDescription": "Software prefetch data cache fills where data is returned from local L2 cache, L3 cache or different L2 cache in the same CCX.",
373    "UMask": "0x03"
374  },
375  {
376    "EventName": "ls_sw_pf_dc_fills.near_cache",
377    "EventCode": "0x59",
378    "BriefDescription": "Software prefetch data cache fills where data is returned from cache of another CCX in the same NUMA node.",
379    "UMask": "0x04"
380  },
381  {
382    "EventName": "ls_sw_pf_dc_fills.dram_io_near",
383    "EventCode": "0x59",
384    "BriefDescription": "Software prefetch data cache fills where data is returned from either DRAM or MMIO in the same NUMA node.",
385    "UMask": "0x08"
386  },
387  {
388    "EventName": "ls_sw_pf_dc_fills.far_cache",
389    "EventCode": "0x59",
390    "BriefDescription": "Software prefetch data cache fills where data is returned from cache of another CCX in a different NUMA node.",
391    "UMask": "0x10"
392  },
393  {
394    "EventName": "ls_sw_pf_dc_fills.remote_cache",
395    "EventCode": "0x59",
396    "BriefDescription": "Software prefetch data cache fills where data is returned from cache of another CCX in the same or a different NUMA node.",
397    "UMask": "0x14"
398  },
399  {
400    "EventName": "ls_sw_pf_dc_fills.dram_io_far",
401    "EventCode": "0x59",
402    "BriefDescription": "Software prefetch data cache fills where data is returned from either DRAM or MMIO in a different NUMA node.",
403    "UMask": "0x40"
404  },
405  {
406    "EventName": "ls_sw_pf_dc_fills.dram_io_all",
407    "EventCode": "0x59",
408    "BriefDescription": "Software prefetch data cache fills where data is returned from either DRAM or MMIO in the same or a different NUMA node.",
409    "UMask": "0x48"
410  },
411  {
412    "EventName": "ls_sw_pf_dc_fills.far_all",
413    "EventCode": "0x59",
414    "BriefDescription": "Software prefetch data cache fills where data is returned from either cache of another CCX, DRAM or MMIO in a different NUMA node.",
415    "UMask": "0x50"
416  },
417  {
418    "EventName": "ls_sw_pf_dc_fills.alt_mem",
419    "EventCode": "0x59",
420    "BriefDescription": "Software prefetch data cache fills where data is returned from extension memory (CXL).",
421    "UMask": "0x80"
422  },
423  {
424    "EventName": "ls_sw_pf_dc_fills.all",
425    "EventCode": "0x59",
426    "BriefDescription": "Software prefetch data cache fills where data is returned from all types of data sources.",
427    "UMask": "0xdf"
428  },
429  {
430    "EventName": "ls_hw_pf_dc_fills.local_l2",
431    "EventCode": "0x5a",
432    "BriefDescription": "Hardware prefetch data cache fills where data is returned from local L2 cache.",
433    "UMask": "0x01"
434  },
435  {
436    "EventName": "ls_hw_pf_dc_fills.local_ccx",
437    "EventCode": "0x5a",
438    "BriefDescription": "Hardware prefetch data cache fills where data is returned from L3 cache or different L2 cache in the same CCX.",
439    "UMask": "0x02"
440  },
441  {
442    "EventName": "ls_hw_pf_dc_fills.local_all",
443    "EventCode": "0x5a",
444    "BriefDescription": "Hardware prefetch data cache fills where data is returned from local L2 cache, L3 cache or different L2 cache in the same CCX.",
445    "UMask": "0x03"
446  },
447  {
448    "EventName": "ls_hw_pf_dc_fills.near_cache",
449    "EventCode": "0x5a",
450    "BriefDescription": "Hardware prefetch data cache fills where data is returned from cache of another CCX in the same NUMA node.",
451    "UMask": "0x04"
452  },
453  {
454    "EventName": "ls_hw_pf_dc_fills.dram_io_near",
455    "EventCode": "0x5a",
456    "BriefDescription": "Hardware prefetch data cache fills where data is returned from either DRAM or MMIO in the same NUMA node.",
457    "UMask": "0x08"
458  },
459  {
460    "EventName": "ls_hw_pf_dc_fills.far_cache",
461    "EventCode": "0x5a",
462    "BriefDescription": "Hardware prefetch data cache fills where data is returned from cache of another CCX in a different NUMA node.",
463    "UMask": "0x10"
464  },
465  {
466    "EventName": "ls_hw_pf_dc_fills.remote_cache",
467    "EventCode": "0x5a",
468    "BriefDescription": "Hardware prefetch data cache fills where data is returned from cache of another CCX in the same or a different NUMA node.",
469    "UMask": "0x14"
470  },
471  {
472    "EventName": "ls_hw_pf_dc_fills.dram_io_far",
473    "EventCode": "0x5a",
474    "BriefDescription": "Hardware prefetch data cache fills where data is returned from either DRAM or MMIO in a different NUMA node.",
475    "UMask": "0x40"
476  },
477  {
478    "EventName": "ls_hw_pf_dc_fills.dram_io_all",
479    "EventCode": "0x5a",
480    "BriefDescription": "Hardware prefetch data cache fills where data is returned from either DRAM or MMIO in the same or a different NUMA node.",
481    "UMask": "0x48"
482  },
483  {
484    "EventName": "ls_hw_pf_dc_fills.far_all",
485    "EventCode": "0x5a",
486    "BriefDescription": "Hardware prefetch data cache fills where data is returned from either cache of another CCX, DRAM or MMIO in a different NUMA node.",
487    "UMask": "0x50"
488  },
489  {
490    "EventName": "ls_hw_pf_dc_fills.alt_mem",
491    "EventCode": "0x5a",
492    "BriefDescription": "Hardware prefetch data cache fills where data is returned from extension memory (CXL).",
493    "UMask": "0x80"
494  },
495  {
496    "EventName": "ls_hw_pf_dc_fills.all",
497    "EventCode": "0x5a",
498    "BriefDescription": "Hardware prefetch data cache fills where data is returned from all types of data sources.",
499    "UMask": "0xdf"
500  },
501  {
502    "EventName": "ls_alloc_mab_count",
503    "EventCode": "0x5f",
504    "BriefDescription": "In-flight L1 data cache misses i.e. Miss Address Buffer (MAB) allocations each cycle."
505  },
506  {
507    "EventName": "ls_not_halted_cyc",
508    "EventCode": "0x76",
509    "BriefDescription": "Core cycles where the thread is not in halted state."
510  },
511  {
512    "EventName": "ls_tlb_flush.all",
513    "EventCode": "0x78",
514    "BriefDescription": "All TLB flushes.",
515    "UMask": "0xff"
516  },
517  {
518    "EventName": "ls_not_halted_p0_cyc.p0_freq_cyc",
519    "EventCode": "0x120",
520    "BriefDescription": "Reference cycles (P0 frequency) where the thread is not in halted state.",
521    "UMask": "0x1"
522  }
523]
524