1109d59b9SThomas Richter[ 2109d59b9SThomas Richter { 39bacbcedSThomas Richter "Unit": "CPU-M-CF", 4109d59b9SThomas Richter "EventCode": "128", 5109d59b9SThomas Richter "EventName": "L1D_RO_EXCL_WRITES", 6109d59b9SThomas Richter "BriefDescription": "L1D Read-only Exclusive Writes", 7*d786bdf2SThomas Richter "PublicDescription": "A directory write to the Level-1 Data cache where the line was originally in a Read-Only state in the cache but has been updated to be in the Exclusive state that allows stores to the cache line." 8109d59b9SThomas Richter }, 9109d59b9SThomas Richter { 109bacbcedSThomas Richter "Unit": "CPU-M-CF", 11109d59b9SThomas Richter "EventCode": "129", 12109d59b9SThomas Richter "EventName": "DTLB2_WRITES", 13109d59b9SThomas Richter "BriefDescription": "DTLB2 Writes", 14*d786bdf2SThomas Richter "PublicDescription": "A translation has been written into The Translation Lookaside Buffer 2 (TLB2) and the request was made by the data cache. This is a replacement for what was provided for the DTLB on prior machines." 15109d59b9SThomas Richter }, 16109d59b9SThomas Richter { 179bacbcedSThomas Richter "Unit": "CPU-M-CF", 18109d59b9SThomas Richter "EventCode": "130", 19109d59b9SThomas Richter "EventName": "DTLB2_MISSES", 20109d59b9SThomas Richter "BriefDescription": "DTLB2 Misses", 21*d786bdf2SThomas Richter "PublicDescription": "A TLB2 miss is in progress for a request made by the data cache. Incremented by one for every TLB2 miss in progress for the Level-1 Data cache on this cycle. This is a replacement for what was provided for the DTLB on prior machines." 22109d59b9SThomas Richter }, 23109d59b9SThomas Richter { 249bacbcedSThomas Richter "Unit": "CPU-M-CF", 25109d59b9SThomas Richter "EventCode": "131", 26109d59b9SThomas Richter "EventName": "DTLB2_HPAGE_WRITES", 27109d59b9SThomas Richter "BriefDescription": "DTLB2 One-Megabyte Page Writes", 28*d786bdf2SThomas Richter "PublicDescription": "A translation entry was written into the Combined Region and Segment Table Entry array in the Level-2 TLB for a one-megabyte page or a Last Host Translation was done." 29109d59b9SThomas Richter }, 30109d59b9SThomas Richter { 319bacbcedSThomas Richter "Unit": "CPU-M-CF", 32109d59b9SThomas Richter "EventCode": "132", 33109d59b9SThomas Richter "EventName": "DTLB2_GPAGE_WRITES", 34109d59b9SThomas Richter "BriefDescription": "DTLB2 Two-Gigabyte Page Writes", 35*d786bdf2SThomas Richter "PublicDescription": "A translation entry for a two-gigabyte page was written into the Level-2 TLB." 36109d59b9SThomas Richter }, 37109d59b9SThomas Richter { 389bacbcedSThomas Richter "Unit": "CPU-M-CF", 39109d59b9SThomas Richter "EventCode": "133", 40109d59b9SThomas Richter "EventName": "L1D_L2D_SOURCED_WRITES", 41109d59b9SThomas Richter "BriefDescription": "L1D L2D Sourced Writes", 42*d786bdf2SThomas Richter "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from the Level-2 Data cache." 43109d59b9SThomas Richter }, 44109d59b9SThomas Richter { 459bacbcedSThomas Richter "Unit": "CPU-M-CF", 46109d59b9SThomas Richter "EventCode": "134", 47109d59b9SThomas Richter "EventName": "ITLB2_WRITES", 48109d59b9SThomas Richter "BriefDescription": "ITLB2 Writes", 49*d786bdf2SThomas Richter "PublicDescription": "A translation entry has been written into the Translation Lookaside Buffer 2 (TLB2) and the request was made by the instruction cache. This is a replacement for what was provided for the ITLB on prior machines." 50109d59b9SThomas Richter }, 51109d59b9SThomas Richter { 529bacbcedSThomas Richter "Unit": "CPU-M-CF", 53109d59b9SThomas Richter "EventCode": "135", 54109d59b9SThomas Richter "EventName": "ITLB2_MISSES", 55109d59b9SThomas Richter "BriefDescription": "ITLB2 Misses", 56*d786bdf2SThomas Richter "PublicDescription": "A TLB2 miss is in progress for a request made by the instruction cache. Incremented by one for every TLB2 miss in progress for the Level-1 Instruction cache in a cycle. This is a replacement for what was provided for the ITLB on prior machines." 57109d59b9SThomas Richter }, 58109d59b9SThomas Richter { 599bacbcedSThomas Richter "Unit": "CPU-M-CF", 60109d59b9SThomas Richter "EventCode": "136", 61109d59b9SThomas Richter "EventName": "L1I_L2I_SOURCED_WRITES", 62109d59b9SThomas Richter "BriefDescription": "L1I L2I Sourced Writes", 63*d786bdf2SThomas Richter "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from the Level-2 Instruction cache." 64109d59b9SThomas Richter }, 65109d59b9SThomas Richter { 669bacbcedSThomas Richter "Unit": "CPU-M-CF", 67109d59b9SThomas Richter "EventCode": "137", 68109d59b9SThomas Richter "EventName": "TLB2_PTE_WRITES", 69109d59b9SThomas Richter "BriefDescription": "TLB2 PTE Writes", 70*d786bdf2SThomas Richter "PublicDescription": "A translation entry was written into the Page Table Entry array in the Level-2 TLB." 71109d59b9SThomas Richter }, 72109d59b9SThomas Richter { 739bacbcedSThomas Richter "Unit": "CPU-M-CF", 74109d59b9SThomas Richter "EventCode": "138", 75109d59b9SThomas Richter "EventName": "TLB2_CRSTE_WRITES", 76109d59b9SThomas Richter "BriefDescription": "TLB2 CRSTE Writes", 77*d786bdf2SThomas Richter "PublicDescription": "Translation entries were written into the Combined Region and Segment Table Entry array and the Page Table Entry array in the Level-2 TLB." 78109d59b9SThomas Richter }, 79109d59b9SThomas Richter { 809bacbcedSThomas Richter "Unit": "CPU-M-CF", 81109d59b9SThomas Richter "EventCode": "139", 82109d59b9SThomas Richter "EventName": "TLB2_ENGINES_BUSY", 83109d59b9SThomas Richter "BriefDescription": "TLB2 Engines Busy", 84*d786bdf2SThomas Richter "PublicDescription": "The number of Level-2 TLB translation engines busy in a cycle." 85109d59b9SThomas Richter }, 86109d59b9SThomas Richter { 879bacbcedSThomas Richter "Unit": "CPU-M-CF", 88109d59b9SThomas Richter "EventCode": "140", 89109d59b9SThomas Richter "EventName": "TX_C_TEND", 90109d59b9SThomas Richter "BriefDescription": "Completed TEND instructions in constrained TX mode", 91*d786bdf2SThomas Richter "PublicDescription": "A TEND instruction has completed in a constrained transactional-execution mode." 92109d59b9SThomas Richter }, 93109d59b9SThomas Richter { 949bacbcedSThomas Richter "Unit": "CPU-M-CF", 95109d59b9SThomas Richter "EventCode": "141", 96109d59b9SThomas Richter "EventName": "TX_NC_TEND", 97109d59b9SThomas Richter "BriefDescription": "Completed TEND instructions in non-constrained TX mode", 98*d786bdf2SThomas Richter "PublicDescription": "A TEND instruction has completed in a non-constrained transactional-execution mode." 99109d59b9SThomas Richter }, 100109d59b9SThomas Richter { 1019bacbcedSThomas Richter "Unit": "CPU-M-CF", 102109d59b9SThomas Richter "EventCode": "143", 103109d59b9SThomas Richter "EventName": "L1C_TLB2_MISSES", 104109d59b9SThomas Richter "BriefDescription": "L1C TLB2 Misses", 105*d786bdf2SThomas Richter "PublicDescription": "Increments by one for any cycle where a level-1 cache or level-2 TLB miss is in progress." 106109d59b9SThomas Richter }, 107109d59b9SThomas Richter { 1089bacbcedSThomas Richter "Unit": "CPU-M-CF", 109109d59b9SThomas Richter "EventCode": "144", 110109d59b9SThomas Richter "EventName": "L1D_ONCHIP_L3_SOURCED_WRITES", 111109d59b9SThomas Richter "BriefDescription": "L1D On-Chip L3 Sourced Writes", 112*d786bdf2SThomas Richter "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Chip Level-3 cache without intervention." 113109d59b9SThomas Richter }, 114109d59b9SThomas Richter { 1159bacbcedSThomas Richter "Unit": "CPU-M-CF", 116109d59b9SThomas Richter "EventCode": "145", 117109d59b9SThomas Richter "EventName": "L1D_ONCHIP_MEMORY_SOURCED_WRITES", 118109d59b9SThomas Richter "BriefDescription": "L1D On-Chip Memory Sourced Writes", 119*d786bdf2SThomas Richter "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from On-Chip memory." 120109d59b9SThomas Richter }, 121109d59b9SThomas Richter { 1229bacbcedSThomas Richter "Unit": "CPU-M-CF", 123109d59b9SThomas Richter "EventCode": "146", 124109d59b9SThomas Richter "EventName": "L1D_ONCHIP_L3_SOURCED_WRITES_IV", 125109d59b9SThomas Richter "BriefDescription": "L1D On-Chip L3 Sourced Writes with Intervention", 126*d786bdf2SThomas Richter "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Chip Level-3 cache with intervention." 127109d59b9SThomas Richter }, 128109d59b9SThomas Richter { 1299bacbcedSThomas Richter "Unit": "CPU-M-CF", 130109d59b9SThomas Richter "EventCode": "147", 131109d59b9SThomas Richter "EventName": "L1D_ONCLUSTER_L3_SOURCED_WRITES", 132109d59b9SThomas Richter "BriefDescription": "L1D On-Cluster L3 Sourced Writes", 133*d786bdf2SThomas Richter "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from On-Cluster Level-3 cache without intervention." 134109d59b9SThomas Richter }, 135109d59b9SThomas Richter { 1369bacbcedSThomas Richter "Unit": "CPU-M-CF", 137109d59b9SThomas Richter "EventCode": "148", 138109d59b9SThomas Richter "EventName": "L1D_ONCLUSTER_MEMORY_SOURCED_WRITES", 139109d59b9SThomas Richter "BriefDescription": "L1D On-Cluster Memory Sourced Writes", 140*d786bdf2SThomas Richter "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Cluster memory." 141109d59b9SThomas Richter }, 142109d59b9SThomas Richter { 1439bacbcedSThomas Richter "Unit": "CPU-M-CF", 144109d59b9SThomas Richter "EventCode": "149", 145109d59b9SThomas Richter "EventName": "L1D_ONCLUSTER_L3_SOURCED_WRITES_IV", 146109d59b9SThomas Richter "BriefDescription": "L1D On-Cluster L3 Sourced Writes with Intervention", 147*d786bdf2SThomas Richter "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Cluster Level-3 cache with intervention." 148109d59b9SThomas Richter }, 149109d59b9SThomas Richter { 1509bacbcedSThomas Richter "Unit": "CPU-M-CF", 151109d59b9SThomas Richter "EventCode": "150", 152109d59b9SThomas Richter "EventName": "L1D_OFFCLUSTER_L3_SOURCED_WRITES", 153109d59b9SThomas Richter "BriefDescription": "L1D Off-Cluster L3 Sourced Writes", 154*d786bdf2SThomas Richter "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off-Cluster Level-3 cache without intervention." 155109d59b9SThomas Richter }, 156109d59b9SThomas Richter { 1579bacbcedSThomas Richter "Unit": "CPU-M-CF", 158109d59b9SThomas Richter "EventCode": "151", 159109d59b9SThomas Richter "EventName": "L1D_OFFCLUSTER_MEMORY_SOURCED_WRITES", 160109d59b9SThomas Richter "BriefDescription": "L1D Off-Cluster Memory Sourced Writes", 161*d786bdf2SThomas Richter "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from Off-Cluster memory." 162109d59b9SThomas Richter }, 163109d59b9SThomas Richter { 1649bacbcedSThomas Richter "Unit": "CPU-M-CF", 165109d59b9SThomas Richter "EventCode": "152", 166109d59b9SThomas Richter "EventName": "L1D_OFFCLUSTER_L3_SOURCED_WRITES_IV", 167109d59b9SThomas Richter "BriefDescription": "L1D Off-Cluster L3 Sourced Writes with Intervention", 168*d786bdf2SThomas Richter "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off-Cluster Level-3 cache with intervention." 169109d59b9SThomas Richter }, 170109d59b9SThomas Richter { 1719bacbcedSThomas Richter "Unit": "CPU-M-CF", 172109d59b9SThomas Richter "EventCode": "153", 173109d59b9SThomas Richter "EventName": "L1D_OFFDRAWER_L3_SOURCED_WRITES", 174109d59b9SThomas Richter "BriefDescription": "L1D Off-Drawer L3 Sourced Writes", 175*d786bdf2SThomas Richter "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off-Drawer Level-3 cache without intervention." 176109d59b9SThomas Richter }, 177109d59b9SThomas Richter { 1789bacbcedSThomas Richter "Unit": "CPU-M-CF", 179109d59b9SThomas Richter "EventCode": "154", 180109d59b9SThomas Richter "EventName": "L1D_OFFDRAWER_MEMORY_SOURCED_WRITES", 181109d59b9SThomas Richter "BriefDescription": "L1D Off-Drawer Memory Sourced Writes", 182*d786bdf2SThomas Richter "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from Off-Drawer memory." 183109d59b9SThomas Richter }, 184109d59b9SThomas Richter { 1859bacbcedSThomas Richter "Unit": "CPU-M-CF", 186109d59b9SThomas Richter "EventCode": "155", 187109d59b9SThomas Richter "EventName": "L1D_OFFDRAWER_L3_SOURCED_WRITES_IV", 188109d59b9SThomas Richter "BriefDescription": "L1D Off-Drawer L3 Sourced Writes with Intervention", 189*d786bdf2SThomas Richter "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off-Drawer Level-3 cache with intervention." 190109d59b9SThomas Richter }, 191109d59b9SThomas Richter { 1929bacbcedSThomas Richter "Unit": "CPU-M-CF", 193109d59b9SThomas Richter "EventCode": "156", 194109d59b9SThomas Richter "EventName": "L1D_ONDRAWER_L4_SOURCED_WRITES", 195109d59b9SThomas Richter "BriefDescription": "L1D On-Drawer L4 Sourced Writes", 196*d786bdf2SThomas Richter "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from On-Drawer Level-4 cache." 197109d59b9SThomas Richter }, 198109d59b9SThomas Richter { 1999bacbcedSThomas Richter "Unit": "CPU-M-CF", 200109d59b9SThomas Richter "EventCode": "157", 201109d59b9SThomas Richter "EventName": "L1D_OFFDRAWER_L4_SOURCED_WRITES", 202109d59b9SThomas Richter "BriefDescription": "L1D Off-Drawer L4 Sourced Writes", 203*d786bdf2SThomas Richter "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from Off-Drawer Level-4 cache." 204109d59b9SThomas Richter }, 205109d59b9SThomas Richter { 2069bacbcedSThomas Richter "Unit": "CPU-M-CF", 207109d59b9SThomas Richter "EventCode": "158", 208109d59b9SThomas Richter "EventName": "L1D_ONCHIP_L3_SOURCED_WRITES_RO", 209109d59b9SThomas Richter "BriefDescription": "L1D On-Chip L3 Sourced Writes read-only", 210*d786bdf2SThomas Richter "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from On-Chip L3 but a read-only invalidate was done to remove other copies of the cache line." 211109d59b9SThomas Richter }, 212109d59b9SThomas Richter { 2139bacbcedSThomas Richter "Unit": "CPU-M-CF", 214109d59b9SThomas Richter "EventCode": "162", 215109d59b9SThomas Richter "EventName": "L1I_ONCHIP_L3_SOURCED_WRITES", 216109d59b9SThomas Richter "BriefDescription": "L1I On-Chip L3 Sourced Writes", 217*d786bdf2SThomas Richter "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache ine was sourced from an On-Chip Level-3 cache without intervention." 218109d59b9SThomas Richter }, 219109d59b9SThomas Richter { 2209bacbcedSThomas Richter "Unit": "CPU-M-CF", 221109d59b9SThomas Richter "EventCode": "163", 222109d59b9SThomas Richter "EventName": "L1I_ONCHIP_MEMORY_SOURCED_WRITES", 223109d59b9SThomas Richter "BriefDescription": "L1I On-Chip Memory Sourced Writes", 224*d786bdf2SThomas Richter "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache ine was sourced from On-Chip memory." 225109d59b9SThomas Richter }, 226109d59b9SThomas Richter { 2279bacbcedSThomas Richter "Unit": "CPU-M-CF", 228109d59b9SThomas Richter "EventCode": "164", 229109d59b9SThomas Richter "EventName": "L1I_ONCHIP_L3_SOURCED_WRITES_IV", 230109d59b9SThomas Richter "BriefDescription": "L1I On-Chip L3 Sourced Writes with Intervention", 231*d786bdf2SThomas Richter "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache ine was sourced from an On-Chip Level-3 cache with intervention." 232109d59b9SThomas Richter }, 233109d59b9SThomas Richter { 2349bacbcedSThomas Richter "Unit": "CPU-M-CF", 235109d59b9SThomas Richter "EventCode": "165", 236109d59b9SThomas Richter "EventName": "L1I_ONCLUSTER_L3_SOURCED_WRITES", 237109d59b9SThomas Richter "BriefDescription": "L1I On-Cluster L3 Sourced Writes", 238*d786bdf2SThomas Richter "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Cluster Level-3 cache without intervention." 239109d59b9SThomas Richter }, 240109d59b9SThomas Richter { 2419bacbcedSThomas Richter "Unit": "CPU-M-CF", 242109d59b9SThomas Richter "EventCode": "166", 243109d59b9SThomas Richter "EventName": "L1I_ONCLUSTER_MEMORY_SOURCED_WRITES", 244109d59b9SThomas Richter "BriefDescription": "L1I On-Cluster Memory Sourced Writes", 245*d786bdf2SThomas Richter "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Cluster memory." 246109d59b9SThomas Richter }, 247109d59b9SThomas Richter { 2489bacbcedSThomas Richter "Unit": "CPU-M-CF", 249109d59b9SThomas Richter "EventCode": "167", 250109d59b9SThomas Richter "EventName": "L1I_ONCLUSTER_L3_SOURCED_WRITES_IV", 251109d59b9SThomas Richter "BriefDescription": "L1I On-Cluster L3 Sourced Writes with Intervention", 252*d786bdf2SThomas Richter "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from On-Cluster Level-3 cache with intervention." 253109d59b9SThomas Richter }, 254109d59b9SThomas Richter { 2559bacbcedSThomas Richter "Unit": "CPU-M-CF", 256109d59b9SThomas Richter "EventCode": "168", 257109d59b9SThomas Richter "EventName": "L1I_OFFCLUSTER_L3_SOURCED_WRITES", 258109d59b9SThomas Richter "BriefDescription": "L1I Off-Cluster L3 Sourced Writes", 259*d786bdf2SThomas Richter "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off-Cluster Level-3 cache without intervention." 260109d59b9SThomas Richter }, 261109d59b9SThomas Richter { 2629bacbcedSThomas Richter "Unit": "CPU-M-CF", 263109d59b9SThomas Richter "EventCode": "169", 264109d59b9SThomas Richter "EventName": "L1I_OFFCLUSTER_MEMORY_SOURCED_WRITES", 265109d59b9SThomas Richter "BriefDescription": "L1I Off-Cluster Memory Sourced Writes", 266*d786bdf2SThomas Richter "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from Off-Cluster memory." 267109d59b9SThomas Richter }, 268109d59b9SThomas Richter { 2699bacbcedSThomas Richter "Unit": "CPU-M-CF", 270109d59b9SThomas Richter "EventCode": "170", 271109d59b9SThomas Richter "EventName": "L1I_OFFCLUSTER_L3_SOURCED_WRITES_IV", 272109d59b9SThomas Richter "BriefDescription": "L1I Off-Cluster L3 Sourced Writes with Intervention", 273*d786bdf2SThomas Richter "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off-Cluster Level-3 cache with intervention." 274109d59b9SThomas Richter }, 275109d59b9SThomas Richter { 2769bacbcedSThomas Richter "Unit": "CPU-M-CF", 277109d59b9SThomas Richter "EventCode": "171", 278109d59b9SThomas Richter "EventName": "L1I_OFFDRAWER_L3_SOURCED_WRITES", 279109d59b9SThomas Richter "BriefDescription": "L1I Off-Drawer L3 Sourced Writes", 280*d786bdf2SThomas Richter "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off-Drawer Level-3 cache without intervention." 281109d59b9SThomas Richter }, 282109d59b9SThomas Richter { 2839bacbcedSThomas Richter "Unit": "CPU-M-CF", 284109d59b9SThomas Richter "EventCode": "172", 285109d59b9SThomas Richter "EventName": "L1I_OFFDRAWER_MEMORY_SOURCED_WRITES", 286109d59b9SThomas Richter "BriefDescription": "L1I Off-Drawer Memory Sourced Writes", 287*d786bdf2SThomas Richter "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from Off-Drawer memory." 288109d59b9SThomas Richter }, 289109d59b9SThomas Richter { 2909bacbcedSThomas Richter "Unit": "CPU-M-CF", 291109d59b9SThomas Richter "EventCode": "173", 292109d59b9SThomas Richter "EventName": "L1I_OFFDRAWER_L3_SOURCED_WRITES_IV", 293109d59b9SThomas Richter "BriefDescription": "L1I Off-Drawer L3 Sourced Writes with Intervention", 294*d786bdf2SThomas Richter "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off-Drawer Level-3 cache with intervention." 295109d59b9SThomas Richter }, 296109d59b9SThomas Richter { 2979bacbcedSThomas Richter "Unit": "CPU-M-CF", 298109d59b9SThomas Richter "EventCode": "174", 299109d59b9SThomas Richter "EventName": "L1I_ONDRAWER_L4_SOURCED_WRITES", 300109d59b9SThomas Richter "BriefDescription": "L1I On-Drawer L4 Sourced Writes", 301*d786bdf2SThomas Richter "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from On-Drawer Level-4 cache." 302109d59b9SThomas Richter }, 303109d59b9SThomas Richter { 3049bacbcedSThomas Richter "Unit": "CPU-M-CF", 305109d59b9SThomas Richter "EventCode": "175", 306109d59b9SThomas Richter "EventName": "L1I_OFFDRAWER_L4_SOURCED_WRITES", 307109d59b9SThomas Richter "BriefDescription": "L1I Off-Drawer L4 Sourced Writes", 308*d786bdf2SThomas Richter "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from Off-Drawer Level-4 cache." 309109d59b9SThomas Richter }, 310109d59b9SThomas Richter { 3119bacbcedSThomas Richter "Unit": "CPU-M-CF", 312109d59b9SThomas Richter "EventCode": "224", 313109d59b9SThomas Richter "EventName": "BCD_DFP_EXECUTION_SLOTS", 314109d59b9SThomas Richter "BriefDescription": "BCD DFP Execution Slots", 315*d786bdf2SThomas Richter "PublicDescription": "Count of floating point execution slots used for finished Binary Coded Decimal to Decimal Floating Point conversions. Instructions: CDZT, CXZT, CZDT, CZXT." 316109d59b9SThomas Richter }, 317109d59b9SThomas Richter { 3189bacbcedSThomas Richter "Unit": "CPU-M-CF", 319109d59b9SThomas Richter "EventCode": "225", 320109d59b9SThomas Richter "EventName": "VX_BCD_EXECUTION_SLOTS", 321109d59b9SThomas Richter "BriefDescription": "VX BCD Execution Slots", 322*d786bdf2SThomas Richter "PublicDescription": "Count of floating point execution slots used for finished vector arithmetic Binary Coded Decimal instructions. Instructions: VAP, VSP, VMPVMSP, VDP, VSDP, VRP, VLIP, VSRP, VPSOPVCP, VTP, VPKZ, VUPKZ, VCVB, VCVBG, VCVDVCVDG." 323109d59b9SThomas Richter }, 324109d59b9SThomas Richter { 3259bacbcedSThomas Richter "Unit": "CPU-M-CF", 326109d59b9SThomas Richter "EventCode": "226", 327109d59b9SThomas Richter "EventName": "DECIMAL_INSTRUCTIONS", 328109d59b9SThomas Richter "BriefDescription": "Decimal Instructions", 329*d786bdf2SThomas Richter "PublicDescription": "Decimal instructions dispatched. Instructions: CVB, CVD, AP, CP, DP, ED, EDMK, MP, SRP, SP, ZAP." 330109d59b9SThomas Richter }, 331109d59b9SThomas Richter { 3329bacbcedSThomas Richter "Unit": "CPU-M-CF", 333109d59b9SThomas Richter "EventCode": "232", 334109d59b9SThomas Richter "EventName": "LAST_HOST_TRANSLATIONS", 335109d59b9SThomas Richter "BriefDescription": "Last host translation done", 336*d786bdf2SThomas Richter "PublicDescription": "Last Host Translation done." 337109d59b9SThomas Richter }, 338109d59b9SThomas Richter { 3399bacbcedSThomas Richter "Unit": "CPU-M-CF", 340109d59b9SThomas Richter "EventCode": "243", 341109d59b9SThomas Richter "EventName": "TX_NC_TABORT", 342109d59b9SThomas Richter "BriefDescription": "Aborted transactions in non-constrained TX mode", 343*d786bdf2SThomas Richter "PublicDescription": "A transaction abort has occurred in a non-constrained transactional-execution mode." 344109d59b9SThomas Richter }, 345109d59b9SThomas Richter { 3469bacbcedSThomas Richter "Unit": "CPU-M-CF", 347109d59b9SThomas Richter "EventCode": "244", 348109d59b9SThomas Richter "EventName": "TX_C_TABORT_NO_SPECIAL", 349109d59b9SThomas Richter "BriefDescription": "Aborted transactions in constrained TX mode not using special completion logic", 350*d786bdf2SThomas Richter "PublicDescription": "A transaction abort has occurred in a constrained transactional-execution mode and the CPU is not using any special logic to allow the transaction to complete." 351109d59b9SThomas Richter }, 352109d59b9SThomas Richter { 3539bacbcedSThomas Richter "Unit": "CPU-M-CF", 354109d59b9SThomas Richter "EventCode": "245", 355109d59b9SThomas Richter "EventName": "TX_C_TABORT_SPECIAL", 356109d59b9SThomas Richter "BriefDescription": "Aborted transactions in constrained TX mode using special completion logic", 357*d786bdf2SThomas Richter "PublicDescription": "A transaction abort has occurred in a constrained transactional-execution mode and the CPU is using special logic to allow the transaction to complete." 358109d59b9SThomas Richter }, 359109d59b9SThomas Richter { 3609bacbcedSThomas Richter "Unit": "CPU-M-CF", 361109d59b9SThomas Richter "EventCode": "448", 362109d59b9SThomas Richter "EventName": "MT_DIAG_CYCLES_ONE_THR_ACTIVE", 363109d59b9SThomas Richter "BriefDescription": "Cycle count with one thread active", 364109d59b9SThomas Richter "PublicDescription": "Cycle count with one thread active" 365109d59b9SThomas Richter }, 366109d59b9SThomas Richter { 3679bacbcedSThomas Richter "Unit": "CPU-M-CF", 368109d59b9SThomas Richter "EventCode": "449", 369109d59b9SThomas Richter "EventName": "MT_DIAG_CYCLES_TWO_THR_ACTIVE", 370109d59b9SThomas Richter "BriefDescription": "Cycle count with two threads active", 371109d59b9SThomas Richter "PublicDescription": "Cycle count with two threads active" 37208f3e087SJames Clark } 373109d59b9SThomas Richter] 374