Lines Matching full:where

118 	int (*rp_read_cfg)(struct altera_pcie *pcie, int where,
121 int where, int size, u32 value);
123 unsigned int devfn, int where, int size, u32 *value);
125 unsigned int devfn, int where, int size, u32 value);
376 int where, u8 byte_en, bool read, u32 *headers) in get_tlp_header() argument
390 headers[2] = TLP_CFG_DW2(bus, devfn, where); in get_tlp_header()
394 int where, u8 byte_en, u32 *value) in tlp_cfg_dword_read() argument
398 get_tlp_header(pcie, bus, devfn, where, byte_en, true, in tlp_cfg_dword_read()
407 int where, u8 byte_en, u32 value) in tlp_cfg_dword_write() argument
412 get_tlp_header(pcie, bus, devfn, where, byte_en, false, in tlp_cfg_dword_write()
416 if ((where & 0x7) == 0) in tlp_cfg_dword_write()
431 if ((bus == pcie->root_bus_nr) && (where == PCI_PRIMARY_BUS)) in tlp_cfg_dword_write()
437 static int s10_rp_read_cfg(struct altera_pcie *pcie, int where, in s10_rp_read_cfg() argument
440 void __iomem *addr = S10_RP_CFG_ADDR(pcie, where); in s10_rp_read_cfg()
458 int where, int size, u32 value) in s10_rp_write_cfg() argument
460 void __iomem *addr = S10_RP_CFG_ADDR(pcie, where); in s10_rp_write_cfg()
478 if (busno == pcie->root_bus_nr && where == PCI_PRIMARY_BUS) in s10_rp_write_cfg()
484 static int aglx_rp_read_cfg(struct altera_pcie *pcie, int where, in aglx_rp_read_cfg() argument
487 void __iomem *addr = AGLX_RP_CFG_ADDR(pcie, where); in aglx_rp_read_cfg()
502 if (where == PCI_INTERRUPT_PIN && size == 1 && !(*value)) in aglx_rp_read_cfg()
504 else if (where == PCI_INTERRUPT_LINE && !(*value & 0xff00)) in aglx_rp_read_cfg()
511 int where, int size, u32 value) in aglx_rp_write_cfg() argument
513 void __iomem *addr = AGLX_RP_CFG_ADDR(pcie, where); in aglx_rp_write_cfg()
531 if (busno == pcie->root_bus_nr && where == PCI_PRIMARY_BUS) in aglx_rp_write_cfg()
538 unsigned int devfn, int where, int size, u32 value) in aglx_ep_write_cfg() argument
542 where |= FIELD_PREP(AGLX_CFG_TARGET, AGLX_CFG_TARGET_TYPE1); in aglx_ep_write_cfg()
546 cra_writeb(pcie, value, where); in aglx_ep_write_cfg()
549 cra_writew(pcie, value, where); in aglx_ep_write_cfg()
552 cra_writel(pcie, value, where); in aglx_ep_write_cfg()
560 unsigned int devfn, int where, int size, u32 *value) in aglx_ep_read_cfg() argument
564 where |= FIELD_PREP(AGLX_CFG_TARGET, AGLX_CFG_TARGET_TYPE1); in aglx_ep_read_cfg()
568 *value = cra_readb(pcie, where); in aglx_ep_read_cfg()
571 *value = cra_readw(pcie, where); in aglx_ep_read_cfg()
574 *value = cra_readl(pcie, where); in aglx_ep_read_cfg()
582 unsigned int devfn, int where, int size, in _altera_pcie_cfg_read() argument
590 return pcie->pcie_data->ops->rp_read_cfg(pcie, where, in _altera_pcie_cfg_read()
595 where, size, value); in _altera_pcie_cfg_read()
599 byte_en = 1 << (where & 3); in _altera_pcie_cfg_read()
602 byte_en = 3 << (where & 3); in _altera_pcie_cfg_read()
610 (where & ~DWORD_MASK), byte_en, &data); in _altera_pcie_cfg_read()
616 *value = (data >> (8 * (where & 0x3))) & 0xff; in _altera_pcie_cfg_read()
619 *value = (data >> (8 * (where & 0x2))) & 0xffff; in _altera_pcie_cfg_read()
630 unsigned int devfn, int where, int size, in _altera_pcie_cfg_write() argument
634 u32 shift = 8 * (where & 3); in _altera_pcie_cfg_write()
639 where, size, value); in _altera_pcie_cfg_write()
643 where, size, value); in _altera_pcie_cfg_write()
648 byte_en = 1 << (where & 3); in _altera_pcie_cfg_write()
652 byte_en = 3 << (where & 3); in _altera_pcie_cfg_write()
660 return tlp_cfg_dword_write(pcie, busno, devfn, (where & ~DWORD_MASK), in _altera_pcie_cfg_write()
665 int where, int size, u32 *value) in altera_pcie_cfg_read() argument
669 if (altera_pcie_hide_rc_bar(bus, devfn, where)) in altera_pcie_cfg_read()
675 return _altera_pcie_cfg_read(pcie, bus->number, devfn, where, size, in altera_pcie_cfg_read()
680 int where, int size, u32 value) in altera_pcie_cfg_write() argument
684 if (altera_pcie_hide_rc_bar(bus, devfn, where)) in altera_pcie_cfg_write()
690 return _altera_pcie_cfg_write(pcie, bus->number, devfn, where, size, in altera_pcie_cfg_write()