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/linux/drivers/crypto/hisilicon/
H A Dqm.c386 struct hisi_qm *qm; member
402 int (*get_vft)(struct hisi_qm *qm, u32 *base, u32 *number);
403 void (*qm_db)(struct hisi_qm *qm, u16 qn,
405 int (*debug_init)(struct hisi_qm *qm);
406 void (*hw_error_init)(struct hisi_qm *qm);
407 void (*hw_error_uninit)(struct hisi_qm *qm);
408 enum acc_err_result (*hw_error_handle)(struct hisi_qm *qm);
409 int (*set_msi)(struct hisi_qm *qm, bool set);
412 int (*set_ifc_begin)(struct hisi_qm *qm, enum qm_ifc_cmd cmd, u32 data, u32 fun_num);
413 void (*set_ifc_end)(struct hisi_qm *qm);
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H A Ddebugfs.c49 int (*dump_fn)(struct hisi_qm *qm, char *cmd, char *info_name);
117 /* define the QM's dfx regs region and region length */
153 static void dump_show(struct hisi_qm *qm, void *info, in dump_show() argument
156 struct device *dev = &qm->pdev->dev; in dump_show()
168 static int qm_sqc_dump(struct hisi_qm *qm, char *s, char *name) in qm_sqc_dump() argument
170 struct device *dev = &qm->pdev->dev; in qm_sqc_dump()
179 if (ret || qp_id >= qm->qp_num) { in qm_sqc_dump()
180 dev_err(dev, "Please input qp num (0-%u)", qm->qp_num - 1); in qm_sqc_dump()
184 ret = qm_set_and_get_xqc(qm, QM_MB_CMD_SQC, &sqc, qp_id, 1); in qm_sqc_dump()
188 dump_show(qm, &sqc, sizeof(struct qm_sqc), name); in qm_sqc_dump()
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H A Dqm_common.h75 int qm_set_and_get_xqc(struct hisi_qm *qm, u8 cmd, void *xqc, u32 qp_id, bool op);
76 void hisi_qm_show_last_dfx_regs(struct hisi_qm *qm);
77 void hisi_qm_set_algqos_init(struct hisi_qm *qm);
H A DMakefile6 hisi_qm-objs = qm.o sgl.o debugfs.o
/linux/drivers/crypto/hisilicon/sec2/
H A Dsec_main.c346 struct hisi_qm *qm = s->private; in sec_diff_regs_show() local
348 hisi_qm_acc_diff_regs_dump(qm, s, qm->debug.acc_diff_regs, in sec_diff_regs_show()
445 u64 sec_get_alg_bitmap(struct hisi_qm *qm, u32 high, u32 low) in sec_get_alg_bitmap() argument
449 cap_val_h = qm->cap_tables.dev_cap_table[high].cap_val; in sec_get_alg_bitmap()
450 cap_val_l = qm->cap_tables.dev_cap_table[low].cap_val; in sec_get_alg_bitmap()
475 static void sec_set_endian(struct hisi_qm *qm) in sec_set_endian() argument
479 reg = readl_relaxed(qm->io_base + SEC_CONTROL_REG); in sec_set_endian()
487 writel_relaxed(reg, qm->io_base + SEC_CONTROL_REG); in sec_set_endian()
490 static int sec_wait_sva_ready(struct hisi_qm *qm, __u32 offset, __u32 mask) in sec_wait_sva_ready() argument
500 val = readl(qm->io_base + offset); in sec_wait_sva_ready()
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H A Dsec_crypto.c669 sec = container_of(ctx->qps[0]->qm, struct sec_dev, qm); in sec_ctx_base_init()
671 ctx->dev = &sec->qm.pdev->dev; in sec_ctx_base_init()
2070 if (ctx->sec->qm.ver < QM_HW_V3) { in sec_skcipher_ctx_init()
2103 if (ctx->sec->qm.ver < QM_HW_V3) { in sec_aead_init()
2465 if (unlikely(ctx->sec->qm.ver == QM_HW_V2 && !sreq->c_req.c_len)) in sec_aead_spec_check()
2731 int sec_register_to_crypto(struct hisi_qm *qm) in sec_register_to_crypto() argument
2736 alg_mask = sec_get_alg_bitmap(qm, SEC_DRV_ALG_BITMAP_HIGH_TB, in sec_register_to_crypto()
2765 void sec_unregister_from_crypto(struct hisi_qm *qm) in sec_unregister_from_crypto() argument
2769 alg_mask = sec_get_alg_bitmap(qm, SEC_DRV_ALG_BITMAP_HIGH_TB, in sec_unregister_from_crypto()
/linux/drivers/vfio/pci/hisilicon/
H A Dhisi_acc_vfio_pci.c20 static int qm_wait_dev_not_ready(struct hisi_qm *qm) in qm_wait_dev_not_ready() argument
24 return readl_relaxed_poll_timeout(qm->io_base + QM_VF_STATE, in qm_wait_dev_not_ready()
33 static u32 qm_check_reg_state(struct hisi_qm *qm, u32 regs) in qm_check_reg_state() argument
38 state = readl(qm->io_base + regs); in qm_check_reg_state()
41 state = readl(qm->io_base + regs); in qm_check_reg_state()
48 static int qm_read_regs(struct hisi_qm *qm, u32 reg_addr, in qm_read_regs() argument
57 data[i] = readl(qm->io_base + reg_addr); in qm_read_regs()
64 static int qm_write_regs(struct hisi_qm *qm, u32 reg, in qm_write_regs() argument
73 writel(data[i], qm->io_base + reg + i * QM_REG_ADDR_OFFSET); in qm_write_regs()
78 static int qm_get_vft(struct hisi_qm *qm, u32 *base) in qm_get_vft() argument
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/linux/drivers/crypto/hisilicon/zip/
H A Dzip_crypto.c151 dev_dbg(&qp_ctx->qp->qm->pdev->dev, "req cache is full!\n"); in hisi_zip_create_req()
257 struct device *dev = &qp->qm->pdev->dev; in hisi_zip_do_work()
321 struct device *dev = &qp->qm->pdev->dev; in hisi_zip_acomp_cb()
358 dev = &qp_ctx->qp->qm->pdev->dev; in hisi_zip_acompress()
384 dev = &qp_ctx->qp->qm->pdev->dev; in hisi_zip_adecompress()
436 hisi_zip = container_of(qps[0]->qm, struct hisi_zip, qm); in hisi_zip_ctx_init()
522 dev = &tmp->qp->qm->pdev->dev; in hisi_zip_create_sgl_pool()
535 hisi_acc_free_sgl_pool(&ctx->qp_ctx[HZIP_QPC_COMP].qp->qm->pdev->dev, in hisi_zip_create_sgl_pool()
545 hisi_acc_free_sgl_pool(&ctx->qp_ctx[i].qp->qm->pdev->dev, in hisi_zip_release_sgl_pool()
571 dev = &ctx->qp_ctx[0].qp->qm->pdev->dev; in hisi_zip_acomp_init()
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/linux/drivers/net/ethernet/broadcom/bnx2x/
H A Dbnx2x_self_test.c871 "QM: Queue is not empty",
877 "QM: VOQ_0, VOQ credit is not equal to initial credit",
883 "QM: VOQ_1, VOQ credit is not equal to initial credit",
889 "QM: VOQ_4, VOQ credit is not equal to initial credit",
895 "QM: P0 Byte credit is not equal to initial credit",
901 "QM: P1 Byte credit is not equal to initial credit",
1165 "QM: Interrupt status is not 0",
1201 "QM: Credit error register is not 0 (byte or credit overflow/underflow)",
1861 "QM: XQM wrc_fifolvl is not 0",
1867 "QM: UQM wrc_fifolvl is not 0",
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H A Dbnx2x_init.h178 /* QM queue numbers */
193 /* QM Register addresses */
201 /* extracts the QM queue number for the specified port and vnic */
261 /* Configures the QM according to the specified per-traffic-type COSes */
308 /* number of bytes in single QM arbitration cycle -
597 BLOCK_PRTY_INFO(QM, 0, 0x1ff, 0xfff, 0xfff, 0xfff),
H A Dbnx2x_reg.h181 /* [RW 1] CM - QM Interface enable. If 0 - the acknowledge input is
185 /* [RW 1] If set the Q index; received from the QM is inserted to event ID.
235 /* [RW 28] The CM header value for QM request (primary). */
237 /* [RW 28] The CM header value for QM request (secondary). */
239 /* [RW 1] QM - CM Interface enable. If 0 - the valid input is disregarded;
243 /* [RW 6] QM output initial credit. Max credit available - 32. Write writes
247 /* [RW 3] The weight of the QM (primary) input in the WRR mechanism. 0
251 /* [RW 3] The weight of the QM (secondary) input in the WRR mechanism. 0
266 /* [RW 28] The CM header for QM formatting in case of an error in the QM
1063 follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; [2] QM
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/linux/lib/raid6/
H A Drecov_rvv.c40 * v14:p/qm[vx], v15:p/qm[vy] in __raid6_2data_recov_rvv()
54 "vrgather.vv v14, v6, v4\n" /* v14 = qm[vx] */ in __raid6_2data_recov_rvv()
55 "vrgather.vv v15, v7, v5\n" /* v15 = qm[vy] */ in __raid6_2data_recov_rvv()
/linux/drivers/net/ethernet/mediatek/
H A Dmtk_wed_debugfs.c208 DUMP_STR("WED Route QM"), in wed_rxinfo_show()
245 DUMP_STR("WED Route QM"), in wed_rxinfo_show()
502 DUMP_STR("WED Route QM IGRS0(N2H + Recycle)"), in wed_rtqm_show()
511 DUMP_STR("WED Route QM IGRS1(Legacy)"), in wed_rtqm_show()
520 DUMP_STR("WED Route QM IGRS2(RRO3.0)"), in wed_rtqm_show()
529 DUMP_STR("WED Route QM IGRS3(DEBUG)"), in wed_rtqm_show()
/linux/fs/xfs/
H A Dxfs_stats.c61 { "qm", xfsstats_offset(xs_gc_read_calls)}, in xfs_stats_format()
143 seq_puts(m, "qm"); in xqmstat_proc_show()
/linux/drivers/media/platform/nxp/imx-jpeg/
H A DKconfig11 This is a video4linux2 driver for the i.MX8 QXP/QM integrated
/linux/drivers/net/ethernet/qlogic/qed/
H A Dqed_dev.c1394 /******************** QM initialization *******************/
1440 /* Getters for resource amounts necessary for qm initialization */
1511 /* initialize the top level QM params */
1540 /* initialize qm vport params */
1551 /* initialize qm port params */
1554 /* Initialize qm port parameters */ in qed_init_qm_port_params()
1576 /* Reset the params which must be reset for qm init. QM init may be called as
1579 * values. The allocations made for QM init, ports, vports, pqs and vfqs are not
1660 /* qm params accounting */ in qed_init_qm_pq()
1722 /* save pq index in qm info */
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H A Dqed_cxt.h149 * qed_qm_init_pf(): Initailze the QM PF phase, per path.
161 * qed_qm_reconf(): Reconfigures QM pf on the fly.
H A Dqed_init_fw_funcs.c149 /* QM stop command constants */
165 /* QM command macros */
311 /* Set credit threshold for QM bypass flow */ in qed_enable_pf_rl()
324 /* Set credit threshold for QM bypass flow */ in qed_enable_pf_wfq()
345 /* Set credit threshold for QM bypass flow */ in qed_enable_global_rl()
359 /* Set credit threshold for QM bypass flow */ in qed_enable_vport_wfq()
895 "Timeout when waiting for QM SDM command ready signal\n"); in qed_poll_on_qm_cmd_ready()
/linux/drivers/soc/fsl/qbman/
H A Dqman.c1375 static void qman_destroy_portal(struct qman_portal *qm) in qman_destroy_portal() argument
1380 qm_dqrr_sdqcr_set(&qm->p, 0); in qman_destroy_portal()
1391 qm_eqcr_cce_update(&qm->p); in qman_destroy_portal()
1392 qm_eqcr_cce_update(&qm->p); in qman_destroy_portal()
1393 pcfg = qm->config; in qman_destroy_portal()
1395 free_irq(pcfg->irq, qm); in qman_destroy_portal()
1397 kfree(qm->cgrs); in qman_destroy_portal()
1398 qm_mc_finish(&qm->p); in qman_destroy_portal()
1399 qm_mr_finish(&qm->p); in qman_destroy_portal()
1400 qm_dqrr_finish(&qm->p); in qman_destroy_portal()
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/linux/drivers/media/v4l2-core/
H A Dv4l2-ctrls-api.c1205 int v4l2_querymenu(struct v4l2_ctrl_handler *hdl, struct v4l2_querymenu *qm) in v4l2_querymenu() argument
1208 u32 i = qm->index; in v4l2_querymenu()
1210 ctrl = v4l2_ctrl_find(hdl, qm->id); in v4l2_querymenu()
1214 qm->reserved = 0; in v4l2_querymenu()
1239 strscpy(qm->name, ctrl->qmenu[i], sizeof(qm->name)); in v4l2_querymenu()
1241 qm->value = ctrl->qmenu_int[i]; in v4l2_querymenu()
/linux/drivers/accel/habanalabs/gaudi2/
H A Dgaudi2_security.c2645 /* Unsecure all TPC QM tensors */ in gaudi2_init_pb_tpc()
2653 /* unsecure all 32 TPC QM SRF regs */ in gaudi2_init_pb_tpc()
3331 /* MME QM */ in gaudi2_init_protection_bits()
3348 /* MME QM ARC ACP ENG */ in gaudi2_init_protection_bits()
3499 /* NIC QM and QPC */ in gaudi2_init_protection_bits()
3507 /* NIC QM ARC */ in gaudi2_init_protection_bits()
3696 /* MME QM */ in gaudi2_ack_protection_bits_errors()
3709 /* MME QM ARC ACP ENG */ in gaudi2_ack_protection_bits_errors()
3805 /* NIC QM and QPC */ in gaudi2_ack_protection_bits_errors()
3810 /* NIC QM ARC */ in gaudi2_ack_protection_bits_errors()
H A Dgaudi2_masks.h66 /* QM_IDLE_MASK is valid for all engines QM idle check */
/linux/drivers/firmware/imx/
H A DKconfig21 (QM, QP), and i.MX8QX (QXP, DX).
/linux/Documentation/devicetree/bindings/soc/ti/
H A Dkeystone-navigator-qmss.txt21 : Must be "ti,66ak2g-navss-qm" for QMSS on K2G SoC.
44 For QMSS on K2G SoC, following QM reg indexes are used in that order
/linux/include/linux/qed/
H A Dcommon_hsi.h132 /* Traffic classes in network-facing blocks (PBF, BTB, NIG, BRB, PRS and QM) */
352 /* QM CONSTANTS */
355 /* Number of TX queues in the QM */
360 /* Number of Other queues in the QM */
380 /* QM registers data */

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