| /linux/Documentation/arch/arm/ |
| H A D | marvell.rst | 44 …s://web.archive.org/web/20111027032509/http://www.marvell.com/embedded-processors/armada-300/asset…
47 …s://web.archive.org/web/20111027032509/http://www.marvell.com/embedded-processors/armada-300/asset…
50 …s://web.archive.org/web/20130730072715/http://www.marvell.com/embedded-processors/kirkwood/assets/…
51 …s://web.archive.org/web/20121021182835/http://www.marvell.com/embedded-processors/kirkwood/assets/…
52 …s://web.archive.org/web/20130730091033/http://www.marvell.com/embedded-processors/kirkwood/assets/…
55 …s://web.archive.org/web/20131113121446/http://www.marvell.com/embedded-processors/kirkwood/assets/…
56 …s://web.archive.org/web/20121021182835/http://www.marvell.com/embedded-processors/kirkwood/assets/…
57 …s://web.archive.org/web/20130730091033/http://www.marvell.com/embedded-processors/kirkwood/assets/…
61 …s://web.archive.org/web/20120616201621/http://www.marvell.com/embedded-processors/kirkwood/assets/…
62 …s://web.archive.org/web/20130730091654/http://www.marvell.com/embedded-processors/kirkwood/assets/…
[all …]
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| /linux/Documentation/hwmon/ |
| H A D | k10temp.rst | 6 * AMD Family 10h processors:
16 * AMD Family 11h processors:
20 * AMD Family 12h processors: "Llano" (E2/A4/A6/A8-Series)
22 * AMD Family 14h processors: "Brazos" (C/E/G/Z-Series)
24 * AMD Family 15h processors: "Bulldozer" (FX-Series), "Trinity", "Kaveri",
27 * AMD Family 16h processors: "Kabini", "Mullins"
29 * AMD Family 17h processors: "Zen", "Zen 2"
31 * AMD Family 18h processors: "Hygon Dhyana"
33 * AMD Family 19h processors: "Zen 3"
41 BIOS and Kernel Developer's Guide (BKDG) For AMD Family 10h Processors:
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| H A D | fam15h_power.rst | 6 * AMD Family 15h Processors
8 * AMD Family 16h Processors
16 - BIOS and Kernel Developer's Guide (BKDG) For AMD Family 15h Processors
17 - BIOS and Kernel Developer's Guide (BKDG) For AMD Family 16h Processors
33 of AMD Family 15h and 16h processors via TDP algorithm.
35 For AMD Family 15h and 16h processors the following power values can
55 On multi-node processors the calculated value is for the entire
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| H A D | peci-dimmtemp.rst | 8 * Intel Xeon E5/E7 v3 server processors
16 * Intel Xeon E5/E7 v4 server processors
22 * Intel Xeon Scalable server processors
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| /linux/sound/soc/sof/intel/ |
| H A D | Kconfig | 50 using the Baytrail, Braswell or Cherrytrail processors.
70 using the Broadwell processors.
94 using the Tangier/Merrifield processors.
108 This adds support for the Intel(R) platforms using the SkyLake processors.
118 This adds support for the Intel(R) platforms using the KabyLake processors.
135 using the Apollolake processors.
145 using the Geminilake processors.
162 using the Cannonlake processors.
172 using the Coffeelake processors.
182 using the Cometlake processors
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| /linux/drivers/mailbox/ |
| H A D | Kconfig | 6 on-chip processors through queued messages and interrupt driven
44 can be used to send message between different processors in SoC.
53 can be used to send message between different processors in SoC. Any
140 to send message between processors. Say Y here if you want to use the
167 multiple processors within the SoC. Select this driver if your
177 between application processors and other processors/MCU/DSP. Select
187 between application processors and MCU. Say Y here if you want to
237 between different remote processors and host processors on Tegra186
276 between processors. Say Y here if you want to have this support.
284 between processors with ADSP. It will place the message to share
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| /linux/arch/x86/events/ |
| H A D | Kconfig | 10 available on NehalemEX and more modern processors.
18 monitoring on modern processors.
26 monitoring on modern processors.
32 Provide power reporting mechanism support for AMD processors.
35 average power consumption on Family 15h processors.
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| /linux/Documentation/admin-guide/hw-vuln/ |
| H A D | processor_mmio_stale_data.rst | 49 processors, MMIO primary reads will return 64 bytes of data to the core fill
61 processors affected by FBSDP, this may expose stale data from the fill buffers
67 into client core fill buffers, processors affected by MFBDS can leak data from
77 Affected Processors
80 processors for the server market (excluding Intel Xeon E3 processors) are
83 Below is the list of affected Intel processors [#f1]_:
115 Newer processors and microcode update on existing affected processors added new
130 values as part of MD_CLEAR operations. Processors that do not
135 IA32_MCU_OPT_CTRL[FB_CLEAR_DIS]. On such processors, the FB_CLEAR_DIS
137 FB_CLEAR action. Not all processors that support FB_CLEAR will support
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| H A D | cross-thread-rsb.rst | 7 Certain AMD and Hygon processors are subject to a cross-thread return address
18 Affected processors
23 - AMD Family 17h processors
24 - Hygon Family 18h processors
38 Affected SMT-capable processors support 1T and 2T modes of execution when SMT
46 In affected processors, the return address predictor (RAP) is partitioned
61 An attack can be mounted on affected processors by performing a series of CALL
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| H A D | special-register-buffer-data-sampling.rst | 17 Affected processors
23 in the following list, with the exception of the listed processors
25 latter class of processors are only affected when Intel TSX is enabled
70 accesses from other logical processors will be delayed until the special
78 #. Executing RDRAND at the same time on multiple logical processors will be
83 logical processors that miss their core caches, with an impact similar to
88 Software Guard Extensions (Intel SGX) enclaves. On logical processors that
91 processors memory accesses. The opt-out mechanism does not affect Intel SGX
106 for other logical processors.
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| H A D | vmscape.rst | 13 Affected processors
18 **Intel processors:**
26 **AMD processors:**
29 ** Hygon processors:**
109 Force vulnerability detection and mitigation even on processors that are
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| H A D | multihit.rst | 4 iTLB multihit is an erratum where some processors may incur a machine check
12 Affected processors
18 - non-Intel processors
22 - Intel processors that have the PSCHANGE_MC_NO bit set in the
41 of the page tables. Modern processors use virtual memory, a technique that creates
42 the illusion of a very large memory for processors. This virtual space is split
47 processors include a structure, called TLB, that caches recent translations.
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| /linux/tools/perf/pmu-events/arch/x86/goldmont/ |
| H A D | frontend.json | 39 … "References per ICache line. This event counts differently than Intel processors based on Silverm…
43 …h target is to a new line.\r\nThis event counts differently than Intel processors based on Silverm…
48 …vailable in the ICache (hit). This event counts differently than Intel processors based on Silverm…
52 … cache line is in the ICache. This event counts differently than Intel processors based on Silverm…
57 …ailable in the ICache (miss). This event counts differently than Intel processors based on Silverm…
61 …he line is not in the ICache. This event counts differently than Intel processors based on Silverm…
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| /linux/tools/perf/pmu-events/arch/x86/goldmontplus/ |
| H A D | frontend.json | 39 … "References per ICache line. This event counts differently than Intel processors based on Silverm…
43 …h target is to a new line.\r\nThis event counts differently than Intel processors based on Silverm…
48 …vailable in the ICache (hit). This event counts differently than Intel processors based on Silverm…
52 … cache line is in the ICache. This event counts differently than Intel processors based on Silverm…
57 …ailable in the ICache (miss). This event counts differently than Intel processors based on Silverm…
61 …he line is not in the ICache. This event counts differently than Intel processors based on Silverm…
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| /linux/drivers/spmi/ |
| H A D | Kconfig | 9 serial interface between baseband and application processors
30 processors.
41 processors.
52 processors.
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| /linux/Documentation/arch/powerpc/ |
| H A D | ptrace.rst | 6 processors:
14 that's extendable and that covers both BookE and server processors, so
23 BookE processors don't have restrictions here, but server processors have
87 that the BookE supports. COMEFROM breakpoints available in server processors
137 - set a watchpoint in server processors (BookS)::
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| H A D | elf_hwcaps.rst | 147 The processor supports the v2.05 userlevel architecture. Processors
160 The processor supports the v2.06 userlevel architecture. Processors
182 The processor supports the v2.07 userlevel architecture. Processors
209 The processor supports the v3.0B / v3.0C userlevel architecture. Processors
228 The processor supports the v3.1 userlevel architecture. Processors
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| /linux/Documentation/devicetree/bindings/mailbox/ |
| H A D | aspeed,ast2700-mailbox.yaml | 13 ASPEED AST2700 has multiple processors that need to communicate with each
14 other. The mailbox controller provides a way for these processors to send
16 mechanism that allows processors to send and receive messages through
26 processors to notify each other when a message is available or when an event
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| /linux/arch/sh/ |
| H A D | Kconfig.cpu | 24 Selecting this option will enable support for SH processors that
43 Selecting this option will enable support for SH processors that
63 the store queues integrated in the SH-4 processors.
84 This will enable the use of SR.RB register bank usage. Processors
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| /linux/drivers/video/fbdev/geode/ |
| H A D | Kconfig | 11 the AMD Geode family of processors.
19 AMD Geode LX processors.
32 AMD Geode GX processors.
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| /linux/Documentation/devicetree/bindings/interrupt-controller/ |
| H A D | intel,ixp4xx-interrupt.yaml | 8 title: Intel IXP4xx XScale Networking Processors Interrupt Controller
14 This interrupt controller is found in the Intel IXP4xx processors.
15 Some processors have 32 interrupts, some have up to 64 interrupts.
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| /linux/Documentation/admin-guide/pm/ |
| H A D | intel_pstate.rst | 19 generations of Intel processors. Note, however, that some of those processors
24 For the processors supported by ``intel_pstate``, the P-state concept is broader
71 This is the default operation mode of ``intel_pstate`` for processors with
152 This operation mode is optional for processors that do not support the HWP
156 In this mode ``intel_pstate`` may refuse to work with processors that are not
205 This is the default operation mode of ``intel_pstate`` for processors without
212 processors that are not recognized by it if HWP is prevented from being enabled
259 processors will never use any P-states above the last one set by software for
263 processors setting any P-state from the turbo range will enable the processor
279 Some processors allow multiple cores to be in turbo P-states at the same time,
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| /linux/drivers/rpmsg/ |
| H A D | Kconfig | 40 remote processors in MediaTek platforms.
41 This use IPI and IPC to communicate with remote processors.
74 providing communication channels to remote processors in Qualcomm
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| /linux/arch/mips/include/asm/ |
| H A D | cpu.h | 23 I don't have docs for all the previous processors, but my impression is
24 that bits 16-23 have been 0 for all MIPS processors before the MIPS32/64
232 * Definitions for 7:0 on legacy processors
267 * Older processors used to encode processor version and revision in two
296 * R2000 class processors
302 * R4000 class processors
311 * MIPS32 class processors
320 * MIPS64 class processors
397 #define MIPS_CPU_VP BIT_ULL(40) /* MIPSr6 Virtual Processors (multi-threading) */
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| /linux/Documentation/arch/x86/ |
| H A D | topology.rst | 175 and efficiency rankings, and about the core type on AMD processors with
237 On processors of Family 0x17 and above that do not support CPUID leaf
243 On Processors of Family 0x15, the Core ID from `EBX[7:0]` is used as the
247 All AMD processors that support the `TopologyExtensions` feature store the
249 (Core::X86::Cpuid::NodeId) as the per-CPU `node_id`. On older processors,
301 On Intel processors that support neither CPUID leaf 0x1F, nor CPUID leaf
305 Processors that feature Hyper-Threading is detected using `EDX[28]` of
308 The order of `Maximum number of addressable IDs for logical processors
320 processors in this physical package` from `EBX[23:16]` of CPUID leaf
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