1493a2c2dSTom Lendacky 2493a2c2dSTom Lendacky.. SPDX-License-Identifier: GPL-2.0 3493a2c2dSTom Lendacky 4493a2c2dSTom LendackyCross-Thread Return Address Predictions 5493a2c2dSTom Lendacky======================================= 6493a2c2dSTom Lendacky 7493a2c2dSTom LendackyCertain AMD and Hygon processors are subject to a cross-thread return address 8493a2c2dSTom Lendackypredictions vulnerability. When running in SMT mode and one sibling thread 9493a2c2dSTom Lendackytransitions out of C0 state, the other sibling thread could use return target 10493a2c2dSTom Lendackypredictions from the sibling thread that transitioned out of C0. 11493a2c2dSTom Lendacky 12493a2c2dSTom LendackyThe Spectre v2 mitigations protect the Linux kernel, as it fills the return 13493a2c2dSTom Lendackyaddress prediction entries with safe targets when context switching to the idle 14493a2c2dSTom Lendackythread. However, KVM does allow a VMM to prevent exiting guest mode when 15493a2c2dSTom Lendackytransitioning out of C0. This could result in a guest-controlled return target 16493a2c2dSTom Lendackybeing consumed by the sibling thread. 17493a2c2dSTom Lendacky 18493a2c2dSTom LendackyAffected processors 19493a2c2dSTom Lendacky------------------- 20493a2c2dSTom Lendacky 21493a2c2dSTom LendackyThe following CPUs are vulnerable: 22493a2c2dSTom Lendacky 23493a2c2dSTom Lendacky - AMD Family 17h processors 24493a2c2dSTom Lendacky - Hygon Family 18h processors 25493a2c2dSTom Lendacky 26493a2c2dSTom LendackyRelated CVEs 27493a2c2dSTom Lendacky------------ 28493a2c2dSTom Lendacky 29493a2c2dSTom LendackyThe following CVE entry is related to this issue: 30493a2c2dSTom Lendacky 31493a2c2dSTom Lendacky ============== ======================================= 32493a2c2dSTom Lendacky CVE-2022-27672 Cross-Thread Return Address Predictions 33493a2c2dSTom Lendacky ============== ======================================= 34493a2c2dSTom Lendacky 35493a2c2dSTom LendackyProblem 36493a2c2dSTom Lendacky------- 37493a2c2dSTom Lendacky 38493a2c2dSTom LendackyAffected SMT-capable processors support 1T and 2T modes of execution when SMT 39493a2c2dSTom Lendackyis enabled. In 2T mode, both threads in a core are executing code. For the 40493a2c2dSTom Lendackyprocessor core to enter 1T mode, it is required that one of the threads 41493a2c2dSTom Lendackyrequests to transition out of the C0 state. This can be communicated with the 42493a2c2dSTom LendackyHLT instruction or with an MWAIT instruction that requests non-C0. 43493a2c2dSTom LendackyWhen the thread re-enters the C0 state, the processor transitions back 44493a2c2dSTom Lendackyto 2T mode, assuming the other thread is also still in C0 state. 45493a2c2dSTom Lendacky 46493a2c2dSTom LendackyIn affected processors, the return address predictor (RAP) is partitioned 47493a2c2dSTom Lendackydepending on the SMT mode. For instance, in 2T mode each thread uses a private 48493a2c2dSTom Lendacky16-entry RAP, but in 1T mode, the active thread uses a 32-entry RAP. Upon 49493a2c2dSTom Lendackytransition between 1T/2T mode, the RAP contents are not modified but the RAP 50493a2c2dSTom Lendackypointers (which control the next return target to use for predictions) may 51493a2c2dSTom Lendackychange. This behavior may result in return targets from one SMT thread being 52493a2c2dSTom Lendackyused by RET predictions in the sibling thread following a 1T/2T switch. In 53493a2c2dSTom Lendackyparticular, a RET instruction executed immediately after a transition to 1T may 54493a2c2dSTom Lendackyuse a return target from the thread that just became idle. In theory, this 55493a2c2dSTom Lendackycould lead to information disclosure if the return targets used do not come 56493a2c2dSTom Lendackyfrom trustworthy code. 57493a2c2dSTom Lendacky 58493a2c2dSTom LendackyAttack scenarios 59493a2c2dSTom Lendacky---------------- 60493a2c2dSTom Lendacky 61493a2c2dSTom LendackyAn attack can be mounted on affected processors by performing a series of CALL 62493a2c2dSTom Lendackyinstructions with targeted return locations and then transitioning out of C0 63493a2c2dSTom Lendackystate. 64493a2c2dSTom Lendacky 65493a2c2dSTom LendackyMitigation mechanism 66493a2c2dSTom Lendacky-------------------- 67493a2c2dSTom Lendacky 68493a2c2dSTom LendackyBefore entering idle state, the kernel context switches to the idle thread. The 69493a2c2dSTom Lendackycontext switch fills the RAP entries (referred to as the RSB in Linux) with safe 70493a2c2dSTom Lendackytargets by performing a sequence of CALL instructions. 71493a2c2dSTom Lendacky 72493a2c2dSTom LendackyPrevent a guest VM from directly putting the processor into an idle state by 73493a2c2dSTom Lendackyintercepting HLT and MWAIT instructions. 74493a2c2dSTom Lendacky 75493a2c2dSTom LendackyBoth mitigations are required to fully address this issue. 76493a2c2dSTom Lendacky 77493a2c2dSTom LendackyMitigation control on the kernel command line 78493a2c2dSTom Lendacky--------------------------------------------- 79493a2c2dSTom Lendacky 80493a2c2dSTom LendackyUse existing Spectre v2 mitigations that will fill the RSB on context switch. 81493a2c2dSTom Lendacky 82493a2c2dSTom LendackyMitigation control for KVM - module parameter 83493a2c2dSTom Lendacky--------------------------------------------- 84493a2c2dSTom Lendacky 85493a2c2dSTom LendackyBy default, the KVM hypervisor mitigates this issue by intercepting guest 86493a2c2dSTom Lendackyattempts to transition out of C0. A VMM can use the KVM_CAP_X86_DISABLE_EXITS 87493a2c2dSTom Lendackycapability to override those interceptions, but since this is not common, the 88493a2c2dSTom Lendackymitigation that covers this path is not enabled by default. 89493a2c2dSTom Lendacky 90493a2c2dSTom LendackyThe mitigation for the KVM_CAP_X86_DISABLE_EXITS capability can be turned on 91*971cecb9SPaolo Bonziniusing the boolean module parameter mitigate_smt_rsb, e.g. ``kvm.mitigate_smt_rsb=1``. 92