| /linux/drivers/pci/controller/ |
| H A D | pcie-altera.c | 6 * Description: Altera PCIe host controller driver
45 #define S10_RP_CFG_ADDR(pcie, reg) \ argument
46 (((pcie)->hip_base) + (reg) + (1 << 20))
47 #define S10_RP_SECONDARY(pcie) \ argument
48 readb(S10_RP_CFG_ADDR(pcie, PCI_SECONDARY_BUS))
59 #define TLP_CFG_DW0(pcie, cfg) \ argument
62 #define TLP_CFG_DW1(pcie, tag, be) \ argument
63 (((PCI_DEVID(pcie->root_bus_nr, RP_DEVFN)) << 16) | (tag << 8) | (be))
81 #define AGLX_RP_CFG_ADDR(pcie, reg) (((pcie)->hip_base) + (reg)) argument
82 #define AGLX_RP_SECONDARY(pcie) \ argument
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| H A D | pcie-xilinx-nwl.c | 3 * PCIe host controller driver for NWL PCIe Bridge
4 * Based on pcie-xilinx.c, pci-tegra.c
163 phys_addr_t phys_pcie_reg_base; /* Physical PCIe Controller Base */
176 static inline u32 nwl_bridge_readl(struct nwl_pcie *pcie, u32 off) in nwl_bridge_readl() argument
178 return readl(pcie->breg_base + off); in nwl_bridge_readl()
181 static inline void nwl_bridge_writel(struct nwl_pcie *pcie, u32 val, u32 off) in nwl_bridge_writel() argument
183 writel(val, pcie->breg_base + off); in nwl_bridge_writel()
186 static bool nwl_pcie_link_up(struct nwl_pcie *pcie) in nwl_pcie_link_up() argument
188 if (readl(pcie->pcireg_base + PS_LINKUP_OFFSET) & PCIE_PHY_LINKUP_BIT) in nwl_pcie_link_up()
193 static bool nwl_phy_link_up(struct nwl_pcie *pcie) in nwl_phy_link_up() argument
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| H A D | pci-aardvark.c | 3 * Driver for the Aardvark PCIe controller, used on Marvell Armada
32 /* PCIe core registers */
125 /* PCIe window configuration */
216 /* PCIe core controller registers */
224 /* PCIe Central Interrupts Registers */
292 static inline void advk_writel(struct advk_pcie *pcie, u32 val, u64 reg) in advk_writel() argument
294 writel(val, pcie->base + reg); in advk_writel()
297 static inline u32 advk_readl(struct advk_pcie *pcie, u64 reg) in advk_readl() argument
299 return readl(pcie->base + reg); in advk_readl()
302 static u8 advk_pcie_ltssm_state(struct advk_pcie *pcie) in advk_pcie_ltssm_state() argument
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| H A D | pcie-mediatek-gen3.c | 3 * MediaTek PCIe host controller driver.
137 /* Time in ms needed to complete PCIe reset on EN7581 SoC */
154 * @power_up: pcie power_up callback
157 * @flags: pcie device flags.
160 int (*power_up)(struct mtk_gen3_pcie *pcie);
182 * struct mtk_gen3_pcie - PCIe port information
183 * @dev: pointer to PCIe device
189 * @clks: PCIe clocks
190 * @num_clks: PCIe clocks count for this port
191 * @max_link_speed: Maximum link speed (PCIe Ge
269 struct mtk_gen3_pcie *pcie = bus->sysdata; mtk_pcie_config_tlp_header() local
284 struct mtk_gen3_pcie *pcie = bus->sysdata; mtk_pcie_map_bus() local
314 mtk_pcie_set_trans_table(struct mtk_gen3_pcie * pcie,resource_size_t cpu_addr,resource_size_t pci_addr,resource_size_t size,unsigned long type,int * num) mtk_pcie_set_trans_table() argument
377 mtk_pcie_enable_msi(struct mtk_gen3_pcie * pcie) mtk_pcie_enable_msi() argument
406 mtk_pcie_startup_port(struct mtk_gen3_pcie * pcie) mtk_pcie_startup_port() argument
562 struct mtk_gen3_pcie *pcie = data->domain->host_data; mtk_compose_msi_msg() local
587 struct mtk_gen3_pcie *pcie = data->domain->host_data; mtk_msi_bottom_irq_mask() local
603 struct mtk_gen3_pcie *pcie = data->domain->host_data; mtk_msi_bottom_irq_unmask() local
628 struct mtk_gen3_pcie *pcie = domain->host_data; mtk_msi_bottom_domain_alloc() local
656 struct mtk_gen3_pcie *pcie = domain->host_data; mtk_msi_bottom_domain_free() local
676 struct mtk_gen3_pcie *pcie = irq_data_get_irq_chip_data(data); mtk_intx_mask() local
689 struct mtk_gen3_pcie *pcie = irq_data_get_irq_chip_data(data); mtk_intx_unmask() local
710 struct mtk_gen3_pcie *pcie = irq_data_get_irq_chip_data(data); mtk_intx_eoi() local
737 mtk_pcie_init_irq_domains(struct mtk_gen3_pcie * pcie) mtk_pcie_init_irq_domains() argument
787 mtk_pcie_irq_teardown(struct mtk_gen3_pcie * pcie) mtk_pcie_irq_teardown() argument
800 mtk_pcie_msi_handler(struct mtk_gen3_pcie * pcie,int set_idx) mtk_pcie_msi_handler() argument
824 struct mtk_gen3_pcie *pcie = irq_desc_get_handler_data(desc); mtk_pcie_irq_handler() local
848 mtk_pcie_setup_irq(struct mtk_gen3_pcie * pcie) mtk_pcie_setup_irq() argument
867 mtk_pcie_parse_port(struct mtk_gen3_pcie * pcie) mtk_pcie_parse_port() argument
932 mtk_pcie_en7581_power_up(struct mtk_gen3_pcie * pcie) mtk_pcie_en7581_power_up() argument
1044 mtk_pcie_power_up(struct mtk_gen3_pcie * pcie) mtk_pcie_power_up() argument
1106 mtk_pcie_power_down(struct mtk_gen3_pcie * pcie) mtk_pcie_power_down() argument
1120 mtk_pcie_get_controller_max_link_speed(struct mtk_gen3_pcie * pcie) mtk_pcie_get_controller_max_link_speed() argument
1132 mtk_pcie_setup(struct mtk_gen3_pcie * pcie) mtk_pcie_setup() argument
1186 struct mtk_gen3_pcie *pcie; mtk_pcie_probe() local
1219 struct mtk_gen3_pcie *pcie = platform_get_drvdata(pdev); mtk_pcie_remove() local
1231 mtk_pcie_irq_save(struct mtk_gen3_pcie * pcie) mtk_pcie_irq_save() argument
1249 mtk_pcie_irq_restore(struct mtk_gen3_pcie * pcie) mtk_pcie_irq_restore() argument
1267 mtk_pcie_turn_off_link(struct mtk_gen3_pcie * pcie) mtk_pcie_turn_off_link() argument
1284 struct mtk_gen3_pcie *pcie = dev_get_drvdata(dev); mtk_pcie_suspend_noirq() local
1312 struct mtk_gen3_pcie *pcie = dev_get_drvdata(dev); mtk_pcie_resume_noirq() local
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| H A D | pcie-rcar-host.c | 3 * PCIe driver for Renesas R-Car SoCs
7 * arch/sh/drivers/pci/pcie-sh7786.c
36 #include "pcie-rcar.h"
47 /* Structure representing the PCIe interface */
49 struct rcar_pcie pcie; member
67 * Test if the PCIe controller received PM_ENTER_L1 DLLP and in rcar_pcie_wakeup()
68 * the PCIe controller is not in L1 link state. If true, apply in rcar_pcie_wakeup()
92 static u32 rcar_read_conf(struct rcar_pcie *pcie, int where) in rcar_read_conf() argument
95 u32 val = rcar_pci_read_reg(pcie, where & ~3); in rcar_read_conf()
117 static int rcar_pci_write_reg_workaround(struct rcar_pcie *pcie, u32 val, in rcar_pci_write_reg_workaround() argument
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| H A D | pcie-rcar-ep.c | 3 * PCIe endpoint driver for Renesas R-Car SoCs
17 #include "pcie-rcar.h"
21 /* Structure representing the PCIe interface */
23 struct rcar_pcie pcie; member
33 static void rcar_pcie_ep_hw_init(struct rcar_pcie *pcie) in rcar_pcie_ep_hw_init() argument
37 rcar_pci_write_reg(pcie, 0, PCIETCTLR); in rcar_pcie_ep_hw_init()
40 rcar_pci_write_reg(pcie, 0, PCIEMSR); in rcar_pcie_ep_hw_init()
43 rcar_rmw32(pcie, REXPCAP(0), 0xff, PCI_CAP_ID_EXP); in rcar_pcie_ep_hw_init()
44 rcar_rmw32(pcie, REXPCAP(PCI_EXP_FLAGS), in rcar_pcie_ep_hw_init()
46 rcar_rmw32(pcie, RCON in rcar_pcie_ep_hw_init()
93 struct rcar_pcie *pcie = &ep->pcie; rcar_pcie_parse_outbound_ranges() local
131 struct rcar_pcie *pcie = &ep->pcie; rcar_pcie_ep_get_pdata() local
163 struct rcar_pcie *pcie = &ep->pcie; rcar_pcie_ep_write_header() local
203 struct rcar_pcie *pcie = &ep->pcie; rcar_pcie_ep_set_bar() local
262 struct rcar_pcie *pcie = &ep->pcie; rcar_pcie_ep_set_msi() local
276 struct rcar_pcie *pcie = &ep->pcie; rcar_pcie_ep_get_msi() local
290 struct rcar_pcie *pcie = &ep->pcie; rcar_pcie_ep_map_addr() local
349 struct rcar_pcie *pcie = &ep->pcie; rcar_pcie_ep_assert_intx() local
380 rcar_pcie_ep_assert_msi(struct rcar_pcie * pcie,u8 fn,u8 interrupt_num) rcar_pcie_ep_assert_msi() argument
482 struct rcar_pcie *pcie; rcar_pcie_ep_probe() local
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| H A D | pcie-rcar.c | 3 * PCIe driver for Renesas R-Car SoCs
12 #include "pcie-rcar.h"
14 void rcar_pci_write_reg(struct rcar_pcie *pcie, u32 val, unsigned int reg) in rcar_pci_write_reg() argument
16 writel(val, pcie->base + reg); in rcar_pci_write_reg()
19 u32 rcar_pci_read_reg(struct rcar_pcie *pcie, unsigned int reg) in rcar_pci_read_reg() argument
21 return readl(pcie->base + reg); in rcar_pci_read_reg()
24 void rcar_rmw32(struct rcar_pcie *pcie, int where, u32 mask, u32 data) in rcar_rmw32() argument
27 u32 val = rcar_pci_read_reg(pcie, where & ~3); in rcar_rmw32()
31 rcar_pci_write_reg(pcie, val, where & ~3); in rcar_rmw32()
34 int rcar_pcie_wait_for_phyrdy(struct rcar_pcie *pcie) in rcar_pcie_wait_for_phyrdy() argument
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| H A D | pcie-iproc-bcma.c | 15 #include "pcie-iproc.h"
28 struct iproc_pcie *pcie = dev->sysdata; in iproc_bcma_pcie_map_irq() local
29 struct bcma_device *bdev = container_of(pcie->dev, struct bcma_device, dev); in iproc_bcma_pcie_map_irq()
37 struct iproc_pcie *pcie; in iproc_bcma_pcie_probe() local
41 bridge = devm_pci_alloc_host_bridge(dev, sizeof(*pcie)); in iproc_bcma_pcie_probe()
45 pcie = pci_host_bridge_priv(bridge); in iproc_bcma_pcie_probe()
47 pcie->dev = dev; in iproc_bcma_pcie_probe()
49 pcie->type = IPROC_PCIE_PAXB_BCMA; in iproc_bcma_pcie_probe()
50 pcie->base = bdev->io_addr; in iproc_bcma_pcie_probe()
51 if (!pcie->base) { in iproc_bcma_pcie_probe()
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| /linux/Documentation/devicetree/bindings/phy/ |
| H A D | qcom,sc8280xp-qmp-pcie-phy.yaml | 4 $id: http://devicetree.org/schemas/phy/qcom,sc8280xp-qmp-pcie-phy.yaml#
7 title: Qualcomm QMP PHY controller (PCIe, SC8280XP)
14 controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB.
19 - qcom,glymur-qmp-gen4x2-pcie-phy
20 - qcom,glymur-qmp-gen5x4-pcie-phy
21 - qcom,kaanapali-qmp-gen3x2-pcie-phy
22 - qcom,qcs615-qmp-gen3x1-pcie-phy
23 - qcom,qcs8300-qmp-gen4x2-pcie-phy
24 - qcom,sa8775p-qmp-gen4x2-pcie-phy
25 - qcom,sa8775p-qmp-gen4x4-pcie-phy
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| /linux/drivers/pci/controller/dwc/ |
| H A D | pcie-qcom.c | 3 * Qualcomm PCIe root complex driver
31 #include <linux/phy/pcie.h>
41 #include "pcie-designware.h"
42 #include "pcie-qcom-common.h"
241 int (*get_resources)(struct qcom_pcie *pcie);
242 int (*init)(struct qcom_pcie *pcie);
243 int (*post_init)(struct qcom_pcie *pcie);
244 void (*host_post_init)(struct qcom_pcie *pcie);
245 void (*deinit)(struct qcom_pcie *pcie);
246 void (*ltssm_enable)(struct qcom_pcie *pcie);
291 __qcom_pcie_perst_assert(struct qcom_pcie * pcie,bool assert) __qcom_pcie_perst_assert() argument
305 qcom_pcie_perst_assert(struct qcom_pcie * pcie) qcom_pcie_perst_assert() argument
310 qcom_pcie_perst_deassert(struct qcom_pcie * pcie) qcom_pcie_perst_deassert() argument
319 struct qcom_pcie *pcie = to_qcom_pcie(pci); qcom_pcie_start_link() local
335 struct qcom_pcie *pcie = to_qcom_pcie(pci); qcom_pcie_clear_aspm_l0s() local
367 qcom_pcie_configure_dbi_base(struct qcom_pcie * pcie) qcom_pcie_configure_dbi_base() argument
383 qcom_pcie_configure_dbi_atu_base(struct qcom_pcie * pcie) qcom_pcie_configure_dbi_atu_base() argument
411 qcom_pcie_2_1_0_ltssm_enable(struct qcom_pcie * pcie) qcom_pcie_2_1_0_ltssm_enable() argument
426 qcom_pcie_get_resources_2_1_0(struct qcom_pcie * pcie) qcom_pcie_get_resources_2_1_0() argument
464 qcom_pcie_deinit_2_1_0(struct qcom_pcie * pcie) qcom_pcie_deinit_2_1_0() argument
476 qcom_pcie_init_2_1_0(struct qcom_pcie * pcie) qcom_pcie_init_2_1_0() argument
506 qcom_pcie_post_init_2_1_0(struct qcom_pcie * pcie) qcom_pcie_post_init_2_1_0() argument
566 qcom_pcie_get_resources_1_0_0(struct qcom_pcie * pcie) qcom_pcie_get_resources_1_0_0() argument
586 qcom_pcie_deinit_1_0_0(struct qcom_pcie * pcie) qcom_pcie_deinit_1_0_0() argument
595 qcom_pcie_init_1_0_0(struct qcom_pcie * pcie) qcom_pcie_init_1_0_0() argument
630 qcom_pcie_post_init_1_0_0(struct qcom_pcie * pcie) qcom_pcie_post_init_1_0_0() argument
646 qcom_pcie_2_3_2_ltssm_enable(struct qcom_pcie * pcie) qcom_pcie_2_3_2_ltssm_enable() argument
656 qcom_pcie_get_resources_2_3_2(struct qcom_pcie * pcie) qcom_pcie_get_resources_2_3_2() argument
679 qcom_pcie_deinit_2_3_2(struct qcom_pcie * pcie) qcom_pcie_deinit_2_3_2() argument
687 qcom_pcie_init_2_3_2(struct qcom_pcie * pcie) qcom_pcie_init_2_3_2() argument
710 qcom_pcie_post_init_2_3_2(struct qcom_pcie * pcie) qcom_pcie_post_init_2_3_2() argument
739 qcom_pcie_get_resources_2_4_0(struct qcom_pcie * pcie) qcom_pcie_get_resources_2_4_0() argument
775 qcom_pcie_deinit_2_4_0(struct qcom_pcie * pcie) qcom_pcie_deinit_2_4_0() argument
783 qcom_pcie_init_2_4_0(struct qcom_pcie * pcie) qcom_pcie_init_2_4_0() argument
815 qcom_pcie_get_resources_2_3_3(struct qcom_pcie * pcie) qcom_pcie_get_resources_2_3_3() argument
843 qcom_pcie_deinit_2_3_3(struct qcom_pcie * pcie) qcom_pcie_deinit_2_3_3() argument
850 qcom_pcie_init_2_3_3(struct qcom_pcie * pcie) qcom_pcie_init_2_3_3() argument
895 qcom_pcie_post_init_2_3_3(struct qcom_pcie * pcie) qcom_pcie_post_init_2_3_3() argument
931 qcom_pcie_get_resources_2_7_0(struct qcom_pcie * pcie) qcom_pcie_get_resources_2_7_0() argument
958 qcom_pcie_init_2_7_0(struct qcom_pcie * pcie) qcom_pcie_init_2_7_0() argument
1032 qcom_pcie_post_init_2_7_0(struct qcom_pcie * pcie) qcom_pcie_post_init_2_7_0() argument
1057 qcom_pcie_host_post_init_2_7_0(struct qcom_pcie * pcie) qcom_pcie_host_post_init_2_7_0() argument
1064 qcom_pcie_deinit_2_7_0(struct qcom_pcie * pcie) qcom_pcie_deinit_2_7_0() argument
1073 qcom_pcie_config_sid_1_9_0(struct qcom_pcie * pcie) qcom_pcie_config_sid_1_9_0() argument
1149 qcom_pcie_get_resources_2_9_0(struct qcom_pcie * pcie) qcom_pcie_get_resources_2_9_0() argument
1168 qcom_pcie_deinit_2_9_0(struct qcom_pcie * pcie) qcom_pcie_deinit_2_9_0() argument
1175 qcom_pcie_init_2_9_0(struct qcom_pcie * pcie) qcom_pcie_init_2_9_0() argument
1204 qcom_pcie_post_init_2_9_0(struct qcom_pcie * pcie) qcom_pcie_post_init_2_9_0() argument
1258 qcom_pcie_phy_power_off(struct qcom_pcie * pcie) qcom_pcie_phy_power_off() argument
1266 qcom_pcie_phy_power_on(struct qcom_pcie * pcie) qcom_pcie_phy_power_on() argument
1289 struct qcom_pcie *pcie = to_qcom_pcie(pci); qcom_pcie_host_init() local
1348 struct qcom_pcie *pcie = to_qcom_pcie(pci); qcom_pcie_host_deinit() local
1364 struct qcom_pcie *pcie = to_qcom_pcie(pci); qcom_pcie_host_post_init() local
1512 qcom_pcie_icc_init(struct qcom_pcie * pcie) qcom_pcie_icc_init() argument
1555 qcom_pcie_icc_opp_update(struct qcom_pcie * pcie) qcom_pcie_icc_opp_update() argument
1613 struct qcom_pcie *pcie = (struct qcom_pcie *)dev_get_drvdata(s->private); qcom_pcie_link_transition_count() local
1633 qcom_pcie_init_debugfs(struct qcom_pcie * pcie) qcom_pcie_init_debugfs() argument
1692 qcom_pcie_parse_perst(struct qcom_pcie * pcie,struct qcom_pcie_port * port,struct device_node * np) qcom_pcie_parse_perst() argument
1737 qcom_pcie_parse_port(struct qcom_pcie * pcie,struct device_node * node) qcom_pcie_parse_port() argument
1769 qcom_pcie_parse_ports(struct qcom_pcie * pcie) qcom_pcie_parse_ports() argument
1797 qcom_pcie_parse_legacy_binding(struct qcom_pcie * pcie) qcom_pcie_parse_legacy_binding() argument
1846 struct qcom_pcie *pcie; qcom_pcie_probe() local
2030 struct qcom_pcie *pcie; qcom_pcie_suspend_noirq() local
2090 struct qcom_pcie *pcie; qcom_pcie_resume_noirq() local
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| H A D | pcie-visconti.c | 3 * DWC PCIe RC driver for Toshiba Visconti ARM SoC
24 #include "pcie-designware.h"
96 /* Access registers in PCIe ulreg */
97 static void visconti_ulreg_writel(struct visconti_pcie *pcie, u32 val, u32 reg) in visconti_ulreg_writel() argument
99 writel_relaxed(val, pcie->ulreg_base + reg); in visconti_ulreg_writel()
102 static u32 visconti_ulreg_readl(struct visconti_pcie *pcie, u32 reg) in visconti_ulreg_readl() argument
104 return readl_relaxed(pcie->ulreg_base + reg); in visconti_ulreg_readl()
107 /* Access registers in PCIe smu */
108 static void visconti_smu_writel(struct visconti_pcie *pcie, u32 val, u32 reg) in visconti_smu_writel() argument
110 writel_relaxed(val, pcie->smu_base + reg); in visconti_smu_writel()
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| H A D | pcie-uniphier.c | 3 * PCIe host controller driver for UniPhier SoCs
23 #include "pcie-designware.h"
75 static void uniphier_pcie_ltssm_enable(struct uniphier_pcie *pcie, in uniphier_pcie_ltssm_enable() argument
80 val = readl(pcie->base + PCL_APP_READY_CTRL); in uniphier_pcie_ltssm_enable()
85 writel(val, pcie->base + PCL_APP_READY_CTRL); in uniphier_pcie_ltssm_enable()
88 static void uniphier_pcie_init_rc(struct uniphier_pcie *pcie) in uniphier_pcie_init_rc() argument
93 val = readl(pcie->base + PCL_MODE); in uniphier_pcie_init_rc()
96 writel(val, pcie->base + PCL_MODE); in uniphier_pcie_init_rc()
99 val = readl(pcie->base + PCL_APP_PM0); in uniphier_pcie_init_rc()
101 writel(val, pcie->base + PCL_APP_PM0); in uniphier_pcie_init_rc()
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| H A D | pcie-amd-mdb.c | 3 * PCIe host controller driver for AMD MDB PCIe Bridge
22 #include "pcie-designware.h"
55 * struct amd_mdb_pcie - PCIe port information
56 * @pci: DesignWare PCIe controller structure
77 struct amd_mdb_pcie *pcie = irq_data_get_irq_chip_data(data); in amd_mdb_intx_irq_mask() local
78 struct dw_pcie *pci = &pcie->pci; in amd_mdb_intx_irq_mask()
91 writel_relaxed(val, pcie->slcr + AMD_MDB_TLP_IR_DISABLE_MISC); in amd_mdb_intx_irq_mask()
97 struct amd_mdb_pcie *pcie = irq_data_get_irq_chip_data(data); in amd_mdb_intx_irq_unmask() local
98 struct dw_pcie *pci = &pcie in amd_mdb_intx_irq_unmask()
147 struct amd_mdb_pcie *pcie = args; dw_pcie_rp_intx() local
178 struct amd_mdb_pcie *pcie = irq_data_get_irq_chip_data(d); amd_mdb_event_irq_mask() local
192 struct amd_mdb_pcie *pcie = irq_data_get_irq_chip_data(d); amd_mdb_event_irq_unmask() local
227 struct amd_mdb_pcie *pcie = args; amd_mdb_pcie_event() local
240 amd_mdb_pcie_free_irq_domains(struct amd_mdb_pcie * pcie) amd_mdb_pcie_free_irq_domains() argument
253 amd_mdb_pcie_init_port(struct amd_mdb_pcie * pcie) amd_mdb_pcie_init_port() argument
280 amd_mdb_pcie_init_irq_domains(struct amd_mdb_pcie * pcie,struct platform_device * pdev) amd_mdb_pcie_init_irq_domains() argument
329 struct amd_mdb_pcie *pcie = args; amd_mdb_pcie_intr_handler() local
348 amd_mdb_setup_irq(struct amd_mdb_pcie * pcie,struct platform_device * pdev) amd_mdb_setup_irq() argument
408 amd_mdb_parse_pcie_port(struct amd_mdb_pcie * pcie) amd_mdb_parse_pcie_port() argument
430 amd_mdb_add_pcie_port(struct amd_mdb_pcie * pcie,struct platform_device * pdev) amd_mdb_add_pcie_port() argument
476 struct amd_mdb_pcie *pcie; amd_mdb_pcie_probe() local
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| H A D | pcie-armada8k.c | 3 * PCIe host controller driver for Marvell Armada-8K SoCs
5 * Armada-8K PCIe Glue Layer Source Code
25 #include "pcie-designware.h"
73 static void armada8k_pcie_disable_phys(struct armada8k_pcie *pcie) in armada8k_pcie_disable_phys() argument
78 phy_power_off(pcie->phy[i]); in armada8k_pcie_disable_phys()
79 phy_exit(pcie->phy[i]); in armada8k_pcie_disable_phys()
83 static int armada8k_pcie_enable_phys(struct armada8k_pcie *pcie) in armada8k_pcie_enable_phys() argument
89 ret = phy_init(pcie->phy[i]); in armada8k_pcie_enable_phys()
93 ret = phy_set_mode_ext(pcie->phy[i], PHY_MODE_PCIE, in armada8k_pcie_enable_phys()
94 pcie->phy_count); in armada8k_pcie_enable_phys()
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| H A D | pci-layerscape-ep.c | 3 * PCIe controller EP driver for Freescale Layerscape SoCs
19 #include "pcie-designware.h"
24 /* PEX PFa PCIE PME and message interrupt registers*/
52 static u32 ls_pcie_pf_lut_readl(struct ls_pcie_ep *pcie, u32 offset) in ls_pcie_pf_lut_readl() argument
54 struct dw_pcie *pci = pcie->pci; in ls_pcie_pf_lut_readl()
56 if (pcie->big_endian) in ls_pcie_pf_lut_readl()
62 static void ls_pcie_pf_lut_writel(struct ls_pcie_ep *pcie, u32 offset, u32 value) in ls_pcie_pf_lut_writel() argument
64 struct dw_pcie *pci = pcie->pci; in ls_pcie_pf_lut_writel()
66 if (pcie->big_endian) in ls_pcie_pf_lut_writel()
74 struct ls_pcie_ep *pcie in ls_pcie_ep_event_handler() local
115 ls_pcie_ep_interrupt_init(struct ls_pcie_ep * pcie,struct platform_device * pdev) ls_pcie_ep_interrupt_init() argument
145 struct ls_pcie_ep *pcie = to_ls_pcie_ep(pci); ls_pcie_ep_get_features() local
153 struct ls_pcie_ep *pcie = to_ls_pcie_ep(pci); ls_pcie_ep_init() local
190 struct ls_pcie_ep *pcie = to_ls_pcie_ep(pci); ls_pcie_ep_get_dbi_offset() local
230 struct ls_pcie_ep *pcie; ls_pcie_ep_probe() local
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| H A D | pcie-al.c | 3 * PCIe host controller driver for Amazon's Annapurna Labs IP (used in chips
26 struct al_pcie_acpi *pcie = cfg->priv; in al_pcie_map_bus() local
27 void __iomem *dbi_base = pcie->dbi_base; in al_pcie_map_bus()
31 * The DW PCIe core doesn't filter out transactions to other in al_pcie_map_bus()
92 #include "pcie-designware.h"
132 void __iomem *controller_base; /* base of PCIe unit (not DW core) */
142 static inline u32 al_pcie_controller_readl(struct al_pcie *pcie, u32 offset) in al_pcie_controller_readl() argument
144 return readl_relaxed(pcie->controller_base + offset); in al_pcie_controller_readl()
147 static inline void al_pcie_controller_writel(struct al_pcie *pcie, u32 offset, in al_pcie_controller_writel() argument
150 writel_relaxed(val, pcie->controller_base + offset); in al_pcie_controller_writel()
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| /linux/drivers/pci/controller/mobiveil/ |
| H A D | pcie-mobiveil-host.c | 3 * PCIe host controller driver for Mobiveil PCIe Host controller
26 #include "pcie-mobiveil.h"
51 struct mobiveil_pcie *pcie = bus->sysdata; in mobiveil_pcie_map_bus() local
52 struct mobiveil_root_port *rp = &pcie->rp; in mobiveil_pcie_map_bus()
60 return pcie->csr_axi_slave_base + where; in mobiveil_pcie_map_bus()
72 mobiveil_csr_writel(pcie, value, PAB_AXI_AMAP_PEX_WIN_L(WIN_NUM_0)); in mobiveil_pcie_map_bus()
86 struct mobiveil_pcie *pcie = irq_desc_get_handler_data(desc); in mobiveil_pcie_isr() local
87 struct device *dev = &pcie->pdev->dev; in mobiveil_pcie_isr()
88 struct mobiveil_root_port *rp = &pcie->rp; in mobiveil_pcie_isr()
103 val = mobiveil_csr_readl(pcie, PAB_INTP_AMBA_MISC_STAT); in mobiveil_pcie_isr()
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| H A D | pcie-mobiveil.c | 3 * PCIe host controller driver for Mobiveil PCIe Host controller
18 #include "pcie-mobiveil.h"
28 static void mobiveil_pcie_sel_page(struct mobiveil_pcie *pcie, u8 pg_idx) in mobiveil_pcie_sel_page() argument
32 val = readl(pcie->csr_axi_slave_base + PAB_CTRL); in mobiveil_pcie_sel_page()
36 writel(val, pcie->csr_axi_slave_base + PAB_CTRL); in mobiveil_pcie_sel_page()
39 static void __iomem *mobiveil_pcie_comp_addr(struct mobiveil_pcie *pcie, in mobiveil_pcie_comp_addr() argument
44 mobiveil_pcie_sel_page(pcie, 0); in mobiveil_pcie_comp_addr()
45 return pcie->csr_axi_slave_base + off; in mobiveil_pcie_comp_addr()
48 mobiveil_pcie_sel_page(pcie, OFFSET_TO_PAGE_IDX(off)); in mobiveil_pcie_comp_addr()
49 return pcie->csr_axi_slave_base + OFFSET_TO_PAGE_ADDR(off); in mobiveil_pcie_comp_addr()
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| H A D | pcie-layerscape-gen4.c | 3 * PCIe Gen4 host controller driver for NXP Layerscape SoCs
23 #include "pcie-mobiveil.h"
45 static inline u32 ls_g4_pcie_pf_readl(struct ls_g4_pcie *pcie, u32 off) in ls_g4_pcie_pf_readl() argument
47 return ioread32(pcie->pci.csr_axi_slave_base + PCIE_PF_OFF + off); in ls_g4_pcie_pf_readl()
50 static inline void ls_g4_pcie_pf_writel(struct ls_g4_pcie *pcie, in ls_g4_pcie_pf_writel() argument
53 iowrite32(val, pcie->pci.csr_axi_slave_base + PCIE_PF_OFF + off); in ls_g4_pcie_pf_writel()
58 struct ls_g4_pcie *pcie = to_ls_g4_pcie(pci); in ls_g4_pcie_link_up() local
61 state = ls_g4_pcie_pf_readl(pcie, PCIE_PF_DBG); in ls_g4_pcie_link_up()
65 static void ls_g4_pcie_disable_interrupt(struct ls_g4_pcie *pcie) in ls_g4_pcie_disable_interrupt() argument
67 struct mobiveil_pcie *mv_pci = &pcie->pci; in ls_g4_pcie_disable_interrupt()
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| /linux/drivers/pci/controller/cadence/ |
| H A D | pcie-cadence-ep.c | 3 // Cadence PCIe endpoint controller driver.
15 #include "pcie-cadence.h"
22 static u8 cdns_pcie_get_fn_from_vfn(struct cdns_pcie *pcie, u8 fn, u8 vfn) in cdns_pcie_get_fn_from_vfn() argument
30 cap = cdns_pcie_find_ext_capability(pcie, PCI_EXT_CAP_ID_SRIOV); in cdns_pcie_get_fn_from_vfn()
31 first_vf_offset = cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_SRIOV_VF_OFFSET); in cdns_pcie_get_fn_from_vfn()
32 stride = cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_SRIOV_VF_STRIDE); in cdns_pcie_get_fn_from_vfn()
42 struct cdns_pcie *pcie = &ep->pcie; in cdns_pcie_ep_write_header() local
46 cap = cdns_pcie_find_ext_capability(pcie, PCI_EXT_CAP_ID_SRIOV); in cdns_pcie_ep_write_header()
52 cdns_pcie_ep_fn_writew(pcie, fn, reg, hdr->deviceid); in cdns_pcie_ep_write_header()
56 cdns_pcie_ep_fn_writew(pcie, fn, PCI_DEVICE_ID, hdr->deviceid); in cdns_pcie_ep_write_header()
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| /linux/Documentation/devicetree/bindings/pci/ |
| H A D | rcar-pci-host.yaml | 8 title: Renesas R-Car PCIe Host
20 - const: renesas,pcie-r8a7779 # R-Car H1
23 - renesas,pcie-r8a7742 # RZ/G1H
24 - renesas,pcie-r8a7743 # RZ/G1M
25 - renesas,pcie-r8a7744 # RZ/G1N
26 - renesas,pcie-r8a7790 # R-Car H2
27 - renesas,pcie-r8a7791 # R-Car M2-W
28 - renesas,pcie-r8a7793 # R-Car M2-N
29 - const: renesas,pcie-rcar-gen2 # R-Car Gen2 and RZ/G1
32 - renesas,pcie-r8a774a1 # RZ/G2M
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| H A D | fsl,layerscape-pcie.yaml | 4 $id: http://devicetree.org/schemas/pci/fsl,layerscape-pcie.yaml#
7 title: Freescale Layerscape PCIe Root Complex(RC) controller
13 This PCIe RC controller is based on the Synopsys DesignWare PCIe IP
19 register available in the Freescale PCIe controller register set,
20 which can allow determining the underlying DesignWare PCIe controller version
27 - fsl,ls1012a-pcie
28 - fsl,ls1021a-pcie
29 - fsl,ls1028a-pcie
30 - fsl,ls1043a-pcie
31 - fsl,ls1046a-pcie
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| H A D | ti,j721e-pci-ep.yaml | 8 title: TI J721E PCI EP (PCIe Wrapper)
16 - const: ti,j721e-pcie-ep
17 - const: ti,j784s4-pcie-ep
18 - description: PCIe EP controller in AM64
20 - const: ti,am64-pcie-ep
21 - const: ti,j721e-pcie-ep
22 - description: PCIe EP controller in J7200
24 - const: ti,j7200-pcie-ep
25 - const: ti,j721e-pcie-ep
37 ti,syscon-pcie-ctrl:
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| H A D | axis,artpec6-pcie.yaml | 5 $id: http://devicetree.org/schemas/pci/axis,artpec6-pcie.yaml#
8 title: Axis ARTPEC-6 PCIe host controller
14 This PCIe host controller is based on the Synopsys DesignWare PCIe IP.
21 - axis,artpec6-pcie
22 - axis,artpec6-pcie-ep
23 - axis,artpec7-pcie
24 - axis,artpec7-pcie-ep
32 - axis,artpec6-pcie
33 - axis,artpec6-pcie-ep
34 - axis,artpec7-pcie
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| H A D | nvidia,tegra20-pcie.txt | 1 NVIDIA Tegra PCIe controller
5 - "nvidia,tegra20-pcie": for Tegra20
6 - "nvidia,tegra30-pcie": for Tegra30
7 - "nvidia,tegra124-pcie": for Tegra124 and Tegra132
8 - "nvidia,tegra210-pcie": for Tegra210
9 - "nvidia,tegra186-pcie": for Tegra186
11 contain BPMP phandle and PCIe power partition ID. This is required only
71 - "default": active state, puts PCIe I/O out of deep power down state
72 - "idle": puts PCIe I/O into deep power down state
79 - pcie
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