Lines Matching full:pcie
3 * PCIe host controller driver for Mobiveil PCIe Host controller
26 #include "pcie-mobiveil.h"
51 struct mobiveil_pcie *pcie = bus->sysdata; in mobiveil_pcie_map_bus() local
52 struct mobiveil_root_port *rp = &pcie->rp; in mobiveil_pcie_map_bus()
60 return pcie->csr_axi_slave_base + where; in mobiveil_pcie_map_bus()
72 mobiveil_csr_writel(pcie, value, PAB_AXI_AMAP_PEX_WIN_L(WIN_NUM_0)); in mobiveil_pcie_map_bus()
86 struct mobiveil_pcie *pcie = irq_desc_get_handler_data(desc); in mobiveil_pcie_isr() local
87 struct device *dev = &pcie->pdev->dev; in mobiveil_pcie_isr()
88 struct mobiveil_root_port *rp = &pcie->rp; in mobiveil_pcie_isr()
103 val = mobiveil_csr_readl(pcie, PAB_INTP_AMBA_MISC_STAT); in mobiveil_pcie_isr()
104 mask = mobiveil_csr_readl(pcie, PAB_INTP_AMBA_MISC_ENB); in mobiveil_pcie_isr()
109 shifted_status = mobiveil_csr_readl(pcie, in mobiveil_pcie_isr()
123 mobiveil_csr_writel(pcie, in mobiveil_pcie_isr()
128 shifted_status = mobiveil_csr_readl(pcie, in mobiveil_pcie_isr()
136 msi_status = readl_relaxed(pcie->apb_csr_base + MSI_STATUS_OFFSET); in mobiveil_pcie_isr()
140 msi_data = readl_relaxed(pcie->apb_csr_base + MSI_DATA_OFFSET); in mobiveil_pcie_isr()
148 msi_addr_lo = readl_relaxed(pcie->apb_csr_base + in mobiveil_pcie_isr()
150 msi_addr_hi = readl_relaxed(pcie->apb_csr_base + in mobiveil_pcie_isr()
157 msi_status = readl_relaxed(pcie->apb_csr_base + in mobiveil_pcie_isr()
162 mobiveil_csr_writel(pcie, intr_status, PAB_INTP_AMBA_MISC_STAT); in mobiveil_pcie_isr()
166 static int mobiveil_pcie_parse_dt(struct mobiveil_pcie *pcie) in mobiveil_pcie_parse_dt() argument
168 struct device *dev = &pcie->pdev->dev; in mobiveil_pcie_parse_dt()
169 struct platform_device *pdev = pcie->pdev; in mobiveil_pcie_parse_dt()
171 struct mobiveil_root_port *rp = &pcie->rp; in mobiveil_pcie_parse_dt()
185 pcie->csr_axi_slave_base = devm_pci_remap_cfg_resource(dev, res); in mobiveil_pcie_parse_dt()
186 if (IS_ERR(pcie->csr_axi_slave_base)) in mobiveil_pcie_parse_dt()
187 return PTR_ERR(pcie->csr_axi_slave_base); in mobiveil_pcie_parse_dt()
188 pcie->pcie_reg_base = res->start; in mobiveil_pcie_parse_dt()
191 if (of_property_read_u32(node, "apio-wins", &pcie->apio_wins)) in mobiveil_pcie_parse_dt()
192 pcie->apio_wins = MAX_PIO_WINDOWS; in mobiveil_pcie_parse_dt()
194 if (of_property_read_u32(node, "ppio-wins", &pcie->ppio_wins)) in mobiveil_pcie_parse_dt()
195 pcie->ppio_wins = MAX_PIO_WINDOWS; in mobiveil_pcie_parse_dt()
200 static void mobiveil_pcie_enable_msi(struct mobiveil_pcie *pcie) in mobiveil_pcie_enable_msi() argument
202 phys_addr_t msg_addr = pcie->pcie_reg_base; in mobiveil_pcie_enable_msi()
203 struct mobiveil_msi *msi = &pcie->rp.msi; in mobiveil_pcie_enable_msi()
209 pcie->apb_csr_base + MSI_BASE_LO_OFFSET); in mobiveil_pcie_enable_msi()
211 pcie->apb_csr_base + MSI_BASE_HI_OFFSET); in mobiveil_pcie_enable_msi()
212 writel_relaxed(4096, pcie->apb_csr_base + MSI_SIZE_OFFSET); in mobiveil_pcie_enable_msi()
213 writel_relaxed(1, pcie->apb_csr_base + MSI_ENABLE_OFFSET); in mobiveil_pcie_enable_msi()
216 int mobiveil_host_init(struct mobiveil_pcie *pcie, bool reinit) in mobiveil_host_init() argument
218 struct mobiveil_root_port *rp = &pcie->rp; in mobiveil_host_init()
223 pcie->ib_wins_configured = 0; in mobiveil_host_init()
224 pcie->ob_wins_configured = 0; in mobiveil_host_init()
228 value = mobiveil_csr_readl(pcie, PCI_PRIMARY_BUS); in mobiveil_host_init()
231 mobiveil_csr_writel(pcie, value, PCI_PRIMARY_BUS); in mobiveil_host_init()
238 value = mobiveil_csr_readl(pcie, PCI_COMMAND); in mobiveil_host_init()
240 mobiveil_csr_writel(pcie, value, PCI_COMMAND); in mobiveil_host_init()
246 pab_ctrl = mobiveil_csr_readl(pcie, PAB_CTRL); in mobiveil_host_init()
248 mobiveil_csr_writel(pcie, pab_ctrl, PAB_CTRL); in mobiveil_host_init()
254 value = mobiveil_csr_readl(pcie, PAB_AXI_PIO_CTRL); in mobiveil_host_init()
256 mobiveil_csr_writel(pcie, value, PAB_AXI_PIO_CTRL); in mobiveil_host_init()
258 /* Enable PCIe PIO master */ in mobiveil_host_init()
259 value = mobiveil_csr_readl(pcie, PAB_PEX_PIO_CTRL); in mobiveil_host_init()
261 mobiveil_csr_writel(pcie, value, PAB_PEX_PIO_CTRL); in mobiveil_host_init()
271 program_ob_windows(pcie, WIN_NUM_0, rp->ob_io_res->start, 0, in mobiveil_host_init()
275 program_ib_windows(pcie, WIN_NUM_0, 0, 0, MEM_WINDOW_TYPE, IB_WIN_SIZE); in mobiveil_host_init()
287 program_ob_windows(pcie, pcie->ob_wins_configured, in mobiveil_host_init()
293 /* fixup for PCIe class register */ in mobiveil_host_init()
294 value = mobiveil_csr_readl(pcie, PAB_INTP_AXI_PIO_CLASS); in mobiveil_host_init()
297 mobiveil_csr_writel(pcie, value, PAB_INTP_AXI_PIO_CLASS); in mobiveil_host_init()
304 struct mobiveil_pcie *pcie = irq_data_get_irq_chip_data(data); in mobiveil_mask_intx_irq() local
309 rp = &pcie->rp; in mobiveil_mask_intx_irq()
312 shifted_val = mobiveil_csr_readl(pcie, PAB_INTP_AMBA_MISC_ENB); in mobiveil_mask_intx_irq()
314 mobiveil_csr_writel(pcie, shifted_val, PAB_INTP_AMBA_MISC_ENB); in mobiveil_mask_intx_irq()
320 struct mobiveil_pcie *pcie = irq_data_get_irq_chip_data(data); in mobiveil_unmask_intx_irq() local
325 rp = &pcie->rp; in mobiveil_unmask_intx_irq()
328 shifted_val = mobiveil_csr_readl(pcie, PAB_INTP_AMBA_MISC_ENB); in mobiveil_unmask_intx_irq()
330 mobiveil_csr_writel(pcie, shifted_val, PAB_INTP_AMBA_MISC_ENB); in mobiveil_unmask_intx_irq()
374 struct mobiveil_pcie *pcie = irq_data_get_irq_chip_data(data); in mobiveil_compose_msi_msg() local
375 phys_addr_t addr = pcie->pcie_reg_base + (data->hwirq * sizeof(int)); in mobiveil_compose_msi_msg()
381 dev_dbg(&pcie->pdev->dev, "msi#%d address_hi %#x address_lo %#x\n", in mobiveil_compose_msi_msg()
394 struct mobiveil_pcie *pcie = domain->host_data; in mobiveil_irq_msi_domain_alloc() local
395 struct mobiveil_msi *msi = &pcie->rp.msi; in mobiveil_irq_msi_domain_alloc()
421 struct mobiveil_pcie *pcie = irq_data_get_irq_chip_data(d); in mobiveil_irq_msi_domain_free() local
422 struct mobiveil_msi *msi = &pcie->rp.msi; in mobiveil_irq_msi_domain_free()
427 dev_err(&pcie->pdev->dev, "trying to free unused MSI#%lu\n", in mobiveil_irq_msi_domain_free()
439 static int mobiveil_allocate_msi_domains(struct mobiveil_pcie *pcie) in mobiveil_allocate_msi_domains() argument
441 struct device *dev = &pcie->pdev->dev; in mobiveil_allocate_msi_domains()
442 struct mobiveil_msi *msi = &pcie->rp.msi; in mobiveil_allocate_msi_domains()
449 .host_data = pcie, in mobiveil_allocate_msi_domains()
462 static int mobiveil_pcie_init_irq_domain(struct mobiveil_pcie *pcie) in mobiveil_pcie_init_irq_domain() argument
464 struct device *dev = &pcie->pdev->dev; in mobiveil_pcie_init_irq_domain()
465 struct mobiveil_root_port *rp = &pcie->rp; in mobiveil_pcie_init_irq_domain()
469 pcie); in mobiveil_pcie_init_irq_domain()
478 return mobiveil_allocate_msi_domains(pcie); in mobiveil_pcie_init_irq_domain()
481 static int mobiveil_pcie_integrated_interrupt_init(struct mobiveil_pcie *pcie) in mobiveil_pcie_integrated_interrupt_init() argument
483 struct platform_device *pdev = pcie->pdev; in mobiveil_pcie_integrated_interrupt_init()
485 struct mobiveil_root_port *rp = &pcie->rp; in mobiveil_pcie_integrated_interrupt_init()
491 pcie->apb_csr_base = devm_pci_remap_cfg_resource(dev, res); in mobiveil_pcie_integrated_interrupt_init()
492 if (IS_ERR(pcie->apb_csr_base)) in mobiveil_pcie_integrated_interrupt_init()
493 return PTR_ERR(pcie->apb_csr_base); in mobiveil_pcie_integrated_interrupt_init()
496 mobiveil_pcie_enable_msi(pcie); in mobiveil_pcie_integrated_interrupt_init()
503 ret = mobiveil_pcie_init_irq_domain(pcie); in mobiveil_pcie_integrated_interrupt_init()
509 irq_set_chained_handler_and_data(rp->irq, mobiveil_pcie_isr, pcie); in mobiveil_pcie_integrated_interrupt_init()
512 mobiveil_csr_writel(pcie, (PAB_INTP_INTX_MASK | PAB_INTP_MSI_MASK), in mobiveil_pcie_integrated_interrupt_init()
519 static int mobiveil_pcie_interrupt_init(struct mobiveil_pcie *pcie) in mobiveil_pcie_interrupt_init() argument
521 struct mobiveil_root_port *rp = &pcie->rp; in mobiveil_pcie_interrupt_init()
524 return rp->ops->interrupt_init(pcie); in mobiveil_pcie_interrupt_init()
526 return mobiveil_pcie_integrated_interrupt_init(pcie); in mobiveil_pcie_interrupt_init()
529 static bool mobiveil_pcie_is_bridge(struct mobiveil_pcie *pcie) in mobiveil_pcie_is_bridge() argument
533 header_type = mobiveil_csr_readb(pcie, PCI_HEADER_TYPE); in mobiveil_pcie_is_bridge()
539 int mobiveil_pcie_host_probe(struct mobiveil_pcie *pcie) in mobiveil_pcie_host_probe() argument
541 struct mobiveil_root_port *rp = &pcie->rp; in mobiveil_pcie_host_probe()
543 struct device *dev = &pcie->pdev->dev; in mobiveil_pcie_host_probe()
546 ret = mobiveil_pcie_parse_dt(pcie); in mobiveil_pcie_host_probe()
552 if (!mobiveil_pcie_is_bridge(pcie)) in mobiveil_pcie_host_probe()
559 ret = mobiveil_host_init(pcie, false); in mobiveil_pcie_host_probe()
565 ret = mobiveil_pcie_interrupt_init(pcie); in mobiveil_pcie_host_probe()
572 bridge->sysdata = pcie; in mobiveil_pcie_host_probe()
575 ret = mobiveil_bringup_link(pcie); in mobiveil_pcie_host_probe()