Lines Matching full:pcie
3 * PCIe driver for Renesas R-Car SoCs
7 * arch/sh/drivers/pci/pcie-sh7786.c
35 #include "pcie-rcar.h"
46 /* Structure representing the PCIe interface */
48 struct rcar_pcie pcie; member
73 * Test if the PCIe controller received PM_ENTER_L1 DLLP and in rcar_pcie_wakeup()
74 * the PCIe controller is not in L1 link state. If true, apply in rcar_pcie_wakeup()
100 static u32 rcar_read_conf(struct rcar_pcie *pcie, int where) in rcar_read_conf() argument
103 u32 val = rcar_pci_read_reg(pcie, where & ~3); in rcar_read_conf()
125 static int rcar_pci_write_reg_workaround(struct rcar_pcie *pcie, u32 val, in rcar_pci_write_reg_workaround() argument
132 : "+r"(error):"r"(val), "r"(pcie->base + reg) : "memory"); in rcar_pci_write_reg_workaround()
134 rcar_pci_write_reg(pcie, val, reg); in rcar_pci_write_reg_workaround()
139 static int rcar_pci_read_reg_workaround(struct rcar_pcie *pcie, u32 *val, in rcar_pci_read_reg_workaround() argument
146 : "+r"(error), "=r"(*val) : "r"(pcie->base + reg) : "memory"); in rcar_pci_read_reg_workaround()
151 *val = rcar_pci_read_reg(pcie, reg); in rcar_pci_read_reg_workaround()
161 struct rcar_pcie *pcie = &host->pcie; in rcar_pcie_config_access() local
166 ret = rcar_pcie_wakeup(pcie->dev, pcie->base); in rcar_pcie_config_access()
197 *data = rcar_pci_read_reg(pcie, PCICONF(index)); in rcar_pcie_config_access()
199 rcar_pci_write_reg(pcie, *data, PCICONF(index)); in rcar_pcie_config_access()
205 rcar_pci_write_reg(pcie, rcar_pci_read_reg(pcie, PCIEERRFR), PCIEERRFR); in rcar_pcie_config_access()
208 rcar_pci_write_reg(pcie, PCIE_CONF_BUS(bus->number) | in rcar_pcie_config_access()
213 rcar_pci_write_reg(pcie, PCIECCTLR_CCIE | TYPE0, PCIECCTLR); in rcar_pcie_config_access()
215 rcar_pci_write_reg(pcie, PCIECCTLR_CCIE | TYPE1, PCIECCTLR); in rcar_pcie_config_access()
218 if (rcar_pci_read_reg(pcie, PCIEERRFR) & UNSUPPORTED_REQUEST) in rcar_pcie_config_access()
222 if (rcar_read_conf(pcie, RCONF(PCI_STATUS)) & in rcar_pcie_config_access()
227 ret = rcar_pci_read_reg_workaround(pcie, data, PCIECDR); in rcar_pcie_config_access()
229 ret = rcar_pci_write_reg_workaround(pcie, *data, PCIECDR); in rcar_pcie_config_access()
232 rcar_pci_write_reg(pcie, 0, PCIECCTLR); in rcar_pcie_config_access()
253 dev_dbg(&bus->dev, "pcie-config-read: bus=%3d devfn=0x%04x where=0x%04x size=%d val=0x%08x\n", in rcar_pcie_read_conf()
273 dev_dbg(&bus->dev, "pcie-config-write: bus=%3d devfn=0x%04x where=0x%04x size=%d val=0x%08x\n", in rcar_pcie_write_conf()
298 static void rcar_pcie_force_speedup(struct rcar_pcie *pcie) in rcar_pcie_force_speedup() argument
300 struct device *dev = pcie->dev; in rcar_pcie_force_speedup()
304 if ((rcar_pci_read_reg(pcie, MACS2R) & LINK_SPEED) != LINK_SPEED_5_0GTS) in rcar_pcie_force_speedup()
307 if (rcar_pci_read_reg(pcie, MACCTLR) & SPEED_CHANGE) { in rcar_pcie_force_speedup()
312 macsr = rcar_pci_read_reg(pcie, MACSR); in rcar_pcie_force_speedup()
317 rcar_rmw32(pcie, EXPCAP(12), PCI_EXP_LNKSTA_CLS, in rcar_pcie_force_speedup()
321 rcar_rmw32(pcie, MACCGSPSETR, SPCNGRSN, 0); in rcar_pcie_force_speedup()
325 rcar_pci_write_reg(pcie, macsr, MACSR); in rcar_pcie_force_speedup()
328 rcar_rmw32(pcie, MACCTLR, SPEED_CHANGE, SPEED_CHANGE); in rcar_pcie_force_speedup()
331 macsr = rcar_pci_read_reg(pcie, MACSR); in rcar_pcie_force_speedup()
334 rcar_pci_write_reg(pcie, macsr, MACSR); in rcar_pcie_force_speedup()
354 struct rcar_pcie *pcie = &host->pcie; in rcar_pcie_hw_enable() local
361 rcar_pcie_force_speedup(pcie); in rcar_pcie_hw_enable()
373 rcar_pcie_set_outbound(pcie, i, win); in rcar_pcie_hw_enable()
394 static int phy_wait_for_ack(struct rcar_pcie *pcie) in phy_wait_for_ack() argument
396 struct device *dev = pcie->dev; in phy_wait_for_ack()
400 if (rcar_pci_read_reg(pcie, H1_PCIEPHYADRR) & PHY_ACK) in phy_wait_for_ack()
406 dev_err(dev, "Access to PCIe phy timed out\n"); in phy_wait_for_ack()
411 static void phy_write_reg(struct rcar_pcie *pcie, in phy_write_reg() argument
423 rcar_pci_write_reg(pcie, data, H1_PCIEPHYDOUTR); in phy_write_reg()
424 rcar_pci_write_reg(pcie, phyaddr, H1_PCIEPHYADRR); in phy_write_reg()
427 phy_wait_for_ack(pcie); in phy_write_reg()
430 rcar_pci_write_reg(pcie, 0, H1_PCIEPHYDOUTR); in phy_write_reg()
431 rcar_pci_write_reg(pcie, 0, H1_PCIEPHYADRR); in phy_write_reg()
434 phy_wait_for_ack(pcie); in phy_write_reg()
437 static int rcar_pcie_hw_init(struct rcar_pcie *pcie) in rcar_pcie_hw_init() argument
442 rcar_pci_write_reg(pcie, 0, PCIETCTLR); in rcar_pcie_hw_init()
445 rcar_pci_write_reg(pcie, 1, PCIEMSR); in rcar_pcie_hw_init()
447 err = rcar_pcie_wait_for_phyrdy(pcie); in rcar_pcie_hw_init()
456 rcar_pci_write_reg(pcie, PCI_CLASS_BRIDGE_PCI_NORMAL << 8, IDSETR1); in rcar_pcie_hw_init()
462 rcar_rmw32(pcie, RCONF(PCI_SECONDARY_BUS), 0xff, 1); in rcar_pcie_hw_init()
463 rcar_rmw32(pcie, RCONF(PCI_SUBORDINATE_BUS), 0xff, 1); in rcar_pcie_hw_init()
466 rcar_rmw32(pcie, REXPCAP(0), 0xff, PCI_CAP_ID_EXP); in rcar_pcie_hw_init()
467 rcar_rmw32(pcie, REXPCAP(PCI_EXP_FLAGS), in rcar_pcie_hw_init()
469 rcar_rmw32(pcie, RCONF(PCI_HEADER_TYPE), PCI_HEADER_TYPE_MASK, in rcar_pcie_hw_init()
473 rcar_rmw32(pcie, REXPCAP(PCI_EXP_LNKCAP), PCI_EXP_LNKCAP_DLLLARC, in rcar_pcie_hw_init()
477 rcar_rmw32(pcie, REXPCAP(PCI_EXP_SLTCAP), PCI_EXP_SLTCAP_PSN, 0); in rcar_pcie_hw_init()
480 rcar_rmw32(pcie, TLCTLR + 1, 0x3f, 50); in rcar_pcie_hw_init()
483 rcar_rmw32(pcie, RVCCAP(0), 0xfff00000, 0); in rcar_pcie_hw_init()
487 rcar_pci_write_reg(pcie, 0x801f0000, PCIEMSITXR); in rcar_pcie_hw_init()
489 rcar_pci_write_reg(pcie, MACCTLR_INIT_VAL, MACCTLR); in rcar_pcie_hw_init()
492 rcar_pci_write_reg(pcie, CFINIT, PCIETCTLR); in rcar_pcie_hw_init()
495 err = rcar_pcie_wait_for_dl(pcie); in rcar_pcie_hw_init()
500 rcar_rmw32(pcie, PCIEINTXR, 0, 0xF << 8); in rcar_pcie_hw_init()
509 struct rcar_pcie *pcie = &host->pcie; in rcar_pcie_phy_init_h1() local
512 phy_write_reg(pcie, 0, 0x42, 0x1, 0x0EC34191); in rcar_pcie_phy_init_h1()
513 phy_write_reg(pcie, 1, 0x42, 0x1, 0x0EC34180); in rcar_pcie_phy_init_h1()
514 phy_write_reg(pcie, 0, 0x43, 0x1, 0x00210188); in rcar_pcie_phy_init_h1()
515 phy_write_reg(pcie, 1, 0x43, 0x1, 0x00210188); in rcar_pcie_phy_init_h1()
516 phy_write_reg(pcie, 0, 0x44, 0x1, 0x015C0014); in rcar_pcie_phy_init_h1()
517 phy_write_reg(pcie, 1, 0x44, 0x1, 0x015C0014); in rcar_pcie_phy_init_h1()
518 phy_write_reg(pcie, 1, 0x4C, 0x1, 0x786174A0); in rcar_pcie_phy_init_h1()
519 phy_write_reg(pcie, 1, 0x4D, 0x1, 0x048000BB); in rcar_pcie_phy_init_h1()
520 phy_write_reg(pcie, 0, 0x51, 0x1, 0x079EC062); in rcar_pcie_phy_init_h1()
521 phy_write_reg(pcie, 0, 0x52, 0x1, 0x20000000); in rcar_pcie_phy_init_h1()
522 phy_write_reg(pcie, 1, 0x52, 0x1, 0x20000000); in rcar_pcie_phy_init_h1()
523 phy_write_reg(pcie, 1, 0x56, 0x1, 0x00003806); in rcar_pcie_phy_init_h1()
525 phy_write_reg(pcie, 0, 0x60, 0x1, 0x004B03A5); in rcar_pcie_phy_init_h1()
526 phy_write_reg(pcie, 0, 0x64, 0x1, 0x3F0F1F0F); in rcar_pcie_phy_init_h1()
527 phy_write_reg(pcie, 0, 0x66, 0x1, 0x00008000); in rcar_pcie_phy_init_h1()
534 struct rcar_pcie *pcie = &host->pcie; in rcar_pcie_phy_init_gen2() local
540 rcar_pci_write_reg(pcie, 0x000f0030, GEN2_PCIEPHYADDR); in rcar_pcie_phy_init_gen2()
541 rcar_pci_write_reg(pcie, 0x00381203, GEN2_PCIEPHYDATA); in rcar_pcie_phy_init_gen2()
542 rcar_pci_write_reg(pcie, 0x00000001, GEN2_PCIEPHYCTRL); in rcar_pcie_phy_init_gen2()
543 rcar_pci_write_reg(pcie, 0x00000006, GEN2_PCIEPHYCTRL); in rcar_pcie_phy_init_gen2()
545 rcar_pci_write_reg(pcie, 0x000f0054, GEN2_PCIEPHYADDR); in rcar_pcie_phy_init_gen2()
547 rcar_pci_write_reg(pcie, 0x13802007, GEN2_PCIEPHYDATA); in rcar_pcie_phy_init_gen2()
548 rcar_pci_write_reg(pcie, 0x00000001, GEN2_PCIEPHYCTRL); in rcar_pcie_phy_init_gen2()
549 rcar_pci_write_reg(pcie, 0x00000006, GEN2_PCIEPHYCTRL); in rcar_pcie_phy_init_gen2()
572 struct rcar_pcie *pcie = &host->pcie; in rcar_pcie_msi_irq() local
574 struct device *dev = pcie->dev; in rcar_pcie_msi_irq()
577 reg = rcar_pci_read_reg(pcie, PCIEMSIFR); in rcar_pcie_msi_irq()
591 rcar_pci_write_reg(pcie, BIT(index), PCIEMSIFR); in rcar_pcie_msi_irq()
595 reg = rcar_pci_read_reg(pcie, PCIEMSIFR); in rcar_pcie_msi_irq()
604 struct rcar_pcie *pcie = &msi_to_host(msi)->pcie; in rcar_msi_irq_ack() local
607 rcar_pci_write_reg(pcie, BIT(d->hwirq), PCIEMSIFR); in rcar_msi_irq_ack()
613 struct rcar_pcie *pcie = &msi_to_host(msi)->pcie; in rcar_msi_irq_mask() local
618 value = rcar_pci_read_reg(pcie, PCIEMSIIER); in rcar_msi_irq_mask()
620 rcar_pci_write_reg(pcie, value, PCIEMSIIER); in rcar_msi_irq_mask()
627 struct rcar_pcie *pcie = &msi_to_host(msi)->pcie; in rcar_msi_irq_unmask() local
632 value = rcar_pci_read_reg(pcie, PCIEMSIIER); in rcar_msi_irq_unmask()
634 rcar_pci_write_reg(pcie, value, PCIEMSIIER); in rcar_msi_irq_unmask()
641 struct rcar_pcie *pcie = &msi_to_host(msi)->pcie; in rcar_compose_msi_msg() local
643 msg->address_lo = rcar_pci_read_reg(pcie, PCIEMSIALR) & ~MSIFE; in rcar_compose_msi_msg()
644 msg->address_hi = rcar_pci_read_reg(pcie, PCIEMSIAUR); in rcar_compose_msi_msg()
717 struct rcar_pcie *pcie = &msi_to_host(msi)->pcie; in rcar_allocate_domains() local
719 .fwnode = dev_fwnode(pcie->dev), in rcar_allocate_domains()
727 dev_err(pcie->dev, "failed to create IRQ domain\n"); in rcar_allocate_domains()
741 struct rcar_pcie *pcie = &host->pcie; in rcar_pcie_enable_msi() local
742 struct device *dev = pcie->dev; in rcar_pcie_enable_msi()
776 rcar_pci_write_reg(pcie, 0, PCIEMSIIER); in rcar_pcie_enable_msi()
782 rcar_pci_write_reg(pcie, lower_32_bits(res.start) | MSIFE, PCIEMSIALR); in rcar_pcie_enable_msi()
783 rcar_pci_write_reg(pcie, upper_32_bits(res.start), PCIEMSIAUR); in rcar_pcie_enable_msi()
794 struct rcar_pcie *pcie = &host->pcie; in rcar_pcie_teardown_msi() local
797 rcar_pci_write_reg(pcie, 0, PCIEMSIIER); in rcar_pcie_teardown_msi()
800 rcar_pci_write_reg(pcie, 0, PCIEMSIALR); in rcar_pcie_teardown_msi()
807 struct rcar_pcie *pcie = &host->pcie; in rcar_pcie_get_resources() local
808 struct device *dev = pcie->dev; in rcar_pcie_get_resources()
812 host->phy = devm_phy_optional_get(dev, "pcie"); in rcar_pcie_get_resources()
820 pcie->base = devm_ioremap_resource(dev, &res); in rcar_pcie_get_resources()
821 if (IS_ERR(pcie->base)) in rcar_pcie_get_resources()
822 return PTR_ERR(pcie->base); in rcar_pcie_get_resources()
826 dev_err(dev, "cannot get pcie bus clock\n"); in rcar_pcie_get_resources()
854 static int rcar_pcie_inbound_ranges(struct rcar_pcie *pcie, in rcar_pcie_inbound_ranges() argument
872 dev_err(pcie->dev, "Failed to map inbound regions!\n"); in rcar_pcie_inbound_ranges()
894 rcar_pcie_set_inbound(pcie, cpu_addr, pci_addr, in rcar_pcie_inbound_ranges()
913 err = rcar_pcie_inbound_ranges(&host->pcie, entry, &index); in rcar_pcie_parse_map_dma_ranges()
922 { .compatible = "renesas,pcie-r8a7779",
924 { .compatible = "renesas,pcie-r8a7790",
926 { .compatible = "renesas,pcie-r8a7791",
928 { .compatible = "renesas,pcie-rcar-gen2",
930 { .compatible = "renesas,pcie-r8a7795",
932 { .compatible = "renesas,pcie-rcar-gen3",
949 struct rcar_pcie *pcie; in rcar_pcie_probe() local
959 pcie = &host->pcie; in rcar_pcie_probe()
960 pcie->dev = dev; in rcar_pcie_probe()
970 pm_runtime_enable(pcie->dev); in rcar_pcie_probe()
971 err = pm_runtime_get_sync(pcie->dev); in rcar_pcie_probe()
973 dev_err(pcie->dev, "pm_runtime_get_sync failed\n"); in rcar_pcie_probe()
996 dev_err(dev, "failed to init PCIe PHY\n"); in rcar_pcie_probe()
1001 if (rcar_pcie_hw_init(pcie)) { in rcar_pcie_probe()
1002 dev_info(dev, "PCIe link down\n"); in rcar_pcie_probe()
1007 data = rcar_pci_read_reg(pcie, MACSR); in rcar_pcie_probe()
1008 dev_info(dev, "PCIe x%d: link up\n", (data >> 20) & 0x3f); in rcar_pcie_probe()
1053 struct rcar_pcie *pcie = &host->pcie; in rcar_pcie_resume() local
1064 dev_info(dev, "PCIe link down\n"); in rcar_pcie_resume()
1068 data = rcar_pci_read_reg(pcie, MACSR); in rcar_pcie_resume()
1069 dev_info(dev, "PCIe x%d: link up\n", (data >> 20) & 0x3f); in rcar_pcie_resume()
1077 rcar_pci_write_reg(pcie, upper_32_bits(res.start), PCIEMSIAUR); in rcar_pcie_resume()
1078 rcar_pci_write_reg(pcie, lower_32_bits(res.start) | MSIFE, PCIEMSIALR); in rcar_pcie_resume()
1081 rcar_pci_write_reg(pcie, val, PCIEMSIIER); in rcar_pcie_resume()
1092 struct rcar_pcie *pcie = &host->pcie; in rcar_pcie_resume_noirq() local
1094 if (rcar_pci_read_reg(pcie, PMSR) && in rcar_pcie_resume_noirq()
1095 !(rcar_pci_read_reg(pcie, PCIETCTLR) & DL_DOWN)) in rcar_pcie_resume_noirq()
1098 /* Re-establish the PCIe link */ in rcar_pcie_resume_noirq()
1099 rcar_pci_write_reg(pcie, MACCTLR_INIT_VAL, MACCTLR); in rcar_pcie_resume_noirq()
1100 rcar_pci_write_reg(pcie, CFINIT, PCIETCTLR); in rcar_pcie_resume_noirq()
1101 return rcar_pcie_wait_for_dl(pcie); in rcar_pcie_resume_noirq()
1111 .name = "rcar-pcie",
1127 { .compatible = "renesas,pcie-r8a7779" },
1128 { .compatible = "renesas,pcie-r8a7790" },
1129 { .compatible = "renesas,pcie-r8a7791" },
1130 { .compatible = "renesas,pcie-rcar-gen2" },