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/linux/drivers/eisa/
H A Deisa.ids6 # Marc Zyngier <maz@wild-wind.fr.eu.org>
10 ABP0510 "Advansys ABP-510 ISA SCSI Host Adapter"
11 ABP0540 "Advansys ABP-540/542 ISA SCSI Host Adapter"
12 ABP7401 "AdvanSys ABP-740/742 EISA Single Channel SCSI Host Adapter"
13 ABP7501 "AdvanSys ABP-750/752 EISA Dual Channel SCSI Host Adapter"
14 ACC1200 "ACCTON EtherCombo-32 Ethernet Adapter"
15 ACC120A "ACCTON EtherCombo-32 Ethernet Adapter"
25 ACE7010 "ACME Multi-Function Board"
39 ACR1711 "AcerFrame 1000 486/33 SYSTEM-2"
41 ACR3211 "AcerFrame 3000MP 486 SYSTEM-1"
[all …]
/linux/arch/arm/mach-imx/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
14 Support for Freescale MXC/iMX-based family of processors
47 This enables support for Freescale i.MX31 processor
53 This enables support for Freescale i.MX35 processor
64 This enables support for Freescale i.MX1 processor
75 This enables support for Freescale i.MX25 processor
82 This enables support for Freescale i.MX27 processor
88 comment "Cortex-A platforms"
100 This enables support for Freescale i.MX50 processor.
106 This enables support for Freescale i.MX51 processor
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/linux/Documentation/arch/arm/
H A Dmarvell.rst13 ------------
16 - 88F5082
17 - 88F5181 a.k.a Orion-1
18 - 88F5181L a.k.a Orion-VoIP
19 - 88F5182 a.k.a Orion-NAS
21 …- Datasheet: https://web.archive.org/web/20210124231420/http://csclub.uwaterloo.ca/~board/ts7800/M…
22 …- Programmer's User Guide: https://web.archive.org/web/20210124231536/http://csclub.uwaterloo.ca/~…
23 …- User Manual: https://web.archive.org/web/20210124231631/http://csclub.uwaterloo.ca/~board/ts7800…
24 …- Functional Errata: https://web.archive.org/web/20210704165540/https://www.digriz.org.uk/ts78xx/8…
25 - 88F5281 a.k.a Orion-2
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H A Dixp4xx.rst2 Release Notes for Linux on Intel's IXP4xx Network Processor
6 -------------------------------------------------------------------------
10 Intel's IXP4xx network processor is a highly integrated SOC that
17 integration such as an on-chip I2C controller.
30 - Dual serial ports
31 - PCI interface
32 - Flash access (MTD/JFFS)
33 - I2C through GPIO on IXP42x
34 - GPIO for input/output/interrupts
35 See arch/arm/mach-ixp4xx/include/mach/platform.h for access functions.
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/linux/Documentation/devicetree/bindings/remoteproc/
H A Dmtk,scp.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Tinghan Shen <tinghan.shen@mediatek.com>
13 This binding provides support for ARM Cortex M4 Co-processor found on some
19 - mediatek,mt8183-scp
20 - mediatek,mt8186-scp
21 - mediatek,mt8188-scp
22 - mediatek,mt8188-scp-dual
23 - mediatek,mt8192-scp
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H A Dti,k3-r5f-rproc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/ti,k3-r5f-rproc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: TI K3 R5F processor subsystems
10 - Suman Anna <s-anna@ti.com>
13 The TI K3 family of SoCs usually have one or more dual-core Arm Cortex R5F
14 processor subsystems/clusters (R5FSS). The dual core cluster can be used
20 AM64x SoCs do not support LockStep mode, but rather a new non-safety mode
21 called "Single-CPU" mode, where only Core0 is used, but with ability to use
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H A Dti,omap-remoteproc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/ti,omap-remoteproc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Suman Anna <s-anna@ti.com>
13 The OMAP family of SoCs usually have one or more slave processor sub-systems
14 that are used to offload some of the processor-intensive tasks, or to manage
17 The processor cores in the sub-system are usually behind an IOMMU, and may
18 contain additional sub-modules like Internal RAM and/or ROMs, L1 and/or L2
21 The OMAP SoCs usually have a DSP processor sub-system and/or an IPU processor
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H A Dxlnx,zynqmp-r5fss.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/xlnx,zynqmp-r5fss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx R5F processor subsystem
10 - Ben Levinsky <ben.levinsky@amd.com>
11 - Tanmay Shah <tanmay.shah@amd.com>
14 The Xilinx platforms include a pair of Cortex-R5F processors (RPU) for
15 real-time processing based on the Cortex-R5F processor core from ARM.
16 The Cortex-R5F processor implements the Arm v7-R architecture and includes a
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/linux/Documentation/staging/
H A Dremoteproc.rst2 Remote Processor Framework
8 Modern SoCs typically have heterogeneous remote processor devices in asymmetric
10 of operating system, whether it's Linux or any other flavor of real-time OS.
12 OMAP4, for example, has dual Cortex-A9, dual Cortex-M3 and a C64x+ DSP.
13 In a typical configuration, the dual cortex-A9 is running Linux in a SMP
22 platform-specific remoteproc drivers only need to provide a few low-level
24 (for more information about the virtio-based rpmsg bus and its drivers,
29 existing virtio drivers with remote processor backends at a minimal development
39 Boot a remote processor (i.e. load its firmware, power it on, ...).
41 If the remote processor is already powered on, this function immediately
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/linux/Documentation/hwmon/
H A Dcoretemp.rst11 - 0xe (Pentium M DC), 0xf (Core 2 DC 65nm),
12 - 0x16 (Core 2 SC 65nm), 0x17 (Penryn 45nm),
13 - 0x1a (Nehalem), 0x1c (Atom), 0x1e (Lynnfield),
14 - 0x26 (Tunnel Creek Atom), 0x27 (Medfield Atom),
15 - 0x36 (Cedar Trail Atom)
19 Intel 64 and IA-32 Architectures Software Developer's Manual
27 -----------
30 inside Intel CPUs. This driver can read both the per-core and per-package
31 temperature using the appropriate sensors. The per-package sensor is new;
40 Temperature known as TjMax is the maximum junction temperature of processor,
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/linux/drivers/misc/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
27 See Documentation/misc-devices/ad525x_dpot.rst for the
40 module will be called ad525x_dpot-i2c.
51 module will be called ad525x_dpot-spi.
61 tristate "Device driver for IBM RSA service processor"
65 This option enables device driver support for in-band access to the
66 IBM RSA (Condor) service processor in eServer xSeries systems.
69 processor. The driver is meant to be used in conjunction with
72 service processor board as a regular serial port. To make use of
78 website <https://www-03.ibm.com/systems/info/x86servers/serverproven/compat/us/>
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/linux/Documentation/gpu/
H A Dkomeda-kms.rst1 .. SPDX-License-Identifier: GPL-2.0
7 The drm/komeda driver supports the Arm display processor D71 and later products,
23 -----
30 ------
39 -------------------
41 frame. its output frame can be fed into post image processor for showing it on
47 --------------------------
51 Post image processor (improc)
52 -----------------------------
53 Post image processor adjusts frame data like gamma and color space to fit the
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/linux/drivers/edac/
H A Die31200_edac.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Intel E3-1200
6 * Support for the E3-1200 processor family. Heavily based on previous
12 * PCI DRAM controller device ids (Taken from The PCI ID Repository - https://pci-ids.ucw.cz/)
14 * 0108: Xeon E3-1200 Processor Family DRAM Controller
15 * 010c: Xeon E3-1200/2nd Generation Core Processor Family DRAM Controller
16 * 0150: Xeon E3-1200 v2/3rd Gen Core processor DRAM Controller
17 * 0158: Xeon E3-1200 v2/Ivy Bridge DRAM Controller
18 * 015c: Xeon E3-1200 v2/3rd Gen Core processor DRAM Controller
19 * 0c04: Xeon E3-1200 v3/4th Gen Core Processor DRAM Controller
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H A Dcpc925_edac.c1 // SPDX-License-Identifier: GPL-2.0-only
34 #define CPC925_BIT(nr) (1UL << (CPC925_BITS_PER_REG - 1 - nr))
50 * "CPC925 Bridge and Memory Controller User Manual, SA14-2761-02".
57 * Processor Interface Exception Mask Register (APIMASK)
83 * Processor Interface Exception Register (APIEXCP)
139 #define MSCR_SCRUB_MOD_MASK 0xC0000000 /* scrub_mod - bit0:1*/
141 #define MSCR_SI_SHIFT 16 /* si - bit8:15*/
217 ERRCTRL_EOC_NF = CPC925_BIT(3), /* End-Of-Chain error */
246 LINKERR_EOC_ERR = CPC925_BIT(17), /* End-Of-Chain error */
300 pdata->total_mem = 0; in get_total_mem()
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/linux/sound/soc/sof/xtensa/
H A Dcore.c1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
3 // This file is provided under a dual BSD/GPLv2 license. When using or
14 #include "../sof-priv.h"
23 * From 4.4.1.5 table 4-64 Exception Causes of Xtensa
30 "Processor internal physical address or data error during instruction fetch"},
32 "Processor internal physical address or data error during load or store"},
34 "Level-1 interrupt as indicated by set level-1 bits in the INTERRUPT register"},
89 dev_printk(level, sdev->dev, "error: DSP Firmware Oops\n"); in xtensa_dsp_oops()
91 if (xtensa_exception_causes[i].id == xoops->exccause) { in xtensa_dsp_oops()
92 dev_printk(level, sdev->dev, in xtensa_dsp_oops()
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/linux/arch/powerpc/platforms/powermac/
H A Dsmp.c1 // SPDX-License-Identifier: GPL-2.0-or-later
12 * code to detect this card though and disable SMP. --BenH.
18 * Copyright (C) XLR8, Inc. 1994-2000
38 #include <asm/text-patching.h>
81 /* register for interrupting the primary processor on the powersurge */
85 /* register for storing the start address for the secondary processor */
89 /* Daystar/XLR8 4-CPU card */
115 #define PSURGE_NONE -1
162 * -- paulus.
191 int rc = -ENOMEM; in psurge_secondary_ipi_init()
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/linux/arch/powerpc/include/asm/
H A D8xx_immap.h6 * and the dual port ram for the Communication Processor Module.
10 * functional files.....but anyone else is welcome to try. -- Dan
95 /*-----------------------------------------------------------------------
96 * BR - Memory Controller: Base Register 16-9
112 /*-----------------------------------------------------------------------
113 * OR - Memory Controller: Option Register 16-11
227 /* The key to unlock registers maintained by keep-alive power.
300 /* Communication Processor Module Interrupt Controller.
333 /* Communication Processor Module Timers
361 /* Finally, the Communication Processor stuff.....
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/linux/Documentation/devicetree/bindings/sound/
H A Dnvidia,tegra210-mbdrc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/nvidia,tegra210-mbdrc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
13 single full band or a dual band or a multi band dynamic processor.
16 - Jon Hunter <jonathanh@nvidia.com>
17 - Mohan Kumar <mkumard@nvidia.com>
18 - Sameer Pujar <spujar@nvidia.com>
23 - const: nvidia,tegra210-mbdrc
24 - items:
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/linux/Documentation/devicetree/bindings/arm/freescale/
H A Dfsl,vf610-mscm-ir.txt1 Freescale Vybrid Miscellaneous System Control - Interrupt Router
6 it controls the directed processor interrupts. The module is available in all
7 Vybrid SoC's but is only really useful in dual core configurations (VF6xx
8 which comes with a Cortex-A5/Cortex-M4 combination).
11 - compatible: "fsl,vf610-mscm-ir"
12 - reg: the register range of the MSCM Interrupt Router
13 - fsl,cpucfg: The handle to the MSCM CPU configuration node, required
15 - interrupt-controller: Identifies the node as an interrupt controller
16 - #interrupt-cells: Two cells, interrupt number and cells.
23 mscm_ir: interrupt-controller@40001800 {
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/linux/drivers/macintosh/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
38 The I/O Processor (IOP) is an Apple custom IC designed to provide
67 the keyboard and mouse on some machines, as well as the non-volatile
172 If you have an Apple machine with a 1-button mouse, say Y here.
233 which are the recent dual and quad G5 machines using the
234 970MP dual-core processor.
253 blue LEDs "vu-meter" of the XServer macs.
/linux/drivers/gpu/drm/sti/
H A DNOTES2 ---------------------------
4 - The High Quality Video Display Processor (HQVDP) gets video frames from a
7 - The Compositor is a multiplane, dual-mixer (Main & Aux) digital processor. It
9 - The graphics planes are internally processed by the Generic Display
11 - The video plug (VID) connects to the HQVDP output.
12 - The cursor handles ... a cursor.
13 - The TV OUT pre-formats (convert, clip, round) the compositor output data
14 - The HDMI / DVO / HD Analog / SD analog IP builds the video signals
15 - DVO (Digital Video Output) handles a 24bits parallel signal
16 - The HD analog signal is typically driven by a YCbCr cable, supporting up to
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/linux/arch/alpha/kernel/
H A Derr_titan.c1 // SPDX-License-Identifier: GPL-2.0
58 nxs -= 4; in titan_parse_c_misc()
66 printk("%s Non-existent memory access from: %s %d\n", in titan_parse_c_misc()
119 " Source: %-6s Command: %-8s Syndrome: 0x%08x\n" in titan_parse_p_serror()
155 "Memory Read Multiple", "Dual Address Cycle", in titan_parse_p_perror()
206 * (0xA0000 - 0xC0000) and legacy BIOS space (0xC0000 - 0x100000) in titan_parse_p_perror()
236 printk("%s Invalid Peer-to-Peer Write\n", err_print_prefix); in titan_parse_p_perror()
238 printk("%s Invalid Peer-to-Peer Read\n", err_print_prefix); in titan_parse_p_perror()
249 printk("%s Scatter-Gather Error, Invalid PTE\n", in titan_parse_p_perror()
252 printk("%s Delayed-Completion Retry Timeout\n", in titan_parse_p_perror()
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/linux/Documentation/devicetree/bindings/soc/fsl/cpm_qe/
H A Dcpm.txt1 * Freescale Communications Processor Module
10 - compatible : "fsl,cpm1", "fsl,cpm2", or "fsl,qe".
11 - reg : A 48-byte region beginning with CPCR.
15 #address-cells = <1>;
16 #size-cells = <1>;
17 #interrupt-cells = <2>;
18 compatible = "fsl,mpc8272-cpm", "fsl,cpm2";
24 - fsl,cpm-command : This value is ORed with the opcode and command flag
27 - fsl,cpm-brg : Indicates which baud rate generator the device
32 - reg : Unless otherwise specified, the first resource represents the
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/linux/arch/x86/
H A DKconfig.cpu1 # SPDX-License-Identifier: GPL-2.0
4 prompt "x86-32 Processor family"
8 This is the processor type of your CPU. This information is
15 UMC 486SX-S and the NexGen Nx586.
22 - "486" for the AMD/Cyrix/IBM/Intel 486DX/DX2/DX4 or
24 - "586" for generic Pentium CPUs lacking the TSC
26 - "Pentium-Classic" for the Intel Pentium.
27 - "Pentium-MMX" for the Intel Pentium MMX.
28 - "Pentium-Pro" for the Intel Pentium Pro.
29 - "Pentium-II" for the Intel Pentium II or pre-Coppermine Celeron.
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/linux/arch/powerpc/sysdev/
H A Dcpm2.c3 * 8260 Communication Processor Module.
4 * Copyright (c) 1999-2001 Dan Malek <dan@embeddedalley.com>
21 * communication processor.
23 * Buffer descriptors must be allocated from the dual ported memory
46 cpm_cpm2_t __iomem *cpmp; /* Pointer to comm processor space */
49 * the communication processor devices.
54 #define CPM_MAP_SIZE (0x40000) /* 256k - the PQ3 reserve this amount
66 /* Tell everyone where the comm processor resides. in cpm2_reset()
68 cpmp = &cpm2_immr->im_cpm; in cpm2_reset()
89 out_be32(&cpmp->cp_cpcr, command | opcode | CPM_CR_FLG); in cpm_command()
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