1e149ca29SPierre-Louis Bossart // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) 2e657c18aSPierre-Louis Bossart // 3e657c18aSPierre-Louis Bossart // This file is provided under a dual BSD/GPLv2 license. When using or 4e657c18aSPierre-Louis Bossart // redistributing this file, you may do so under either license. 5e657c18aSPierre-Louis Bossart // 6293ad281SPierre-Louis Bossart // Copyright(c) 2018 Intel Corporation 7e657c18aSPierre-Louis Bossart // 8e657c18aSPierre-Louis Bossart // Author: Pan Xiuli <xiuli.pan@linux.intel.com> 9e657c18aSPierre-Louis Bossart // 10e657c18aSPierre-Louis Bossart 11e657c18aSPierre-Louis Bossart #include <linux/module.h> 12e657c18aSPierre-Louis Bossart #include <sound/sof.h> 13e657c18aSPierre-Louis Bossart #include <sound/sof/xtensa.h> 14e657c18aSPierre-Louis Bossart #include "../sof-priv.h" 15e657c18aSPierre-Louis Bossart 16e657c18aSPierre-Louis Bossart struct xtensa_exception_cause { 17e657c18aSPierre-Louis Bossart u32 id; 18e657c18aSPierre-Louis Bossart const char *msg; 19e657c18aSPierre-Louis Bossart const char *description; 20e657c18aSPierre-Louis Bossart }; 21e657c18aSPierre-Louis Bossart 22e657c18aSPierre-Louis Bossart /* 23e657c18aSPierre-Louis Bossart * From 4.4.1.5 table 4-64 Exception Causes of Xtensa 24e657c18aSPierre-Louis Bossart * Instruction Set Architecture (ISA) Reference Manual 25e657c18aSPierre-Louis Bossart */ 26e657c18aSPierre-Louis Bossart static const struct xtensa_exception_cause xtensa_exception_causes[] = { 27e657c18aSPierre-Louis Bossart {0, "IllegalInstructionCause", "Illegal instruction"}, 28e657c18aSPierre-Louis Bossart {1, "SyscallCause", "SYSCALL instruction"}, 29e657c18aSPierre-Louis Bossart {2, "InstructionFetchErrorCause", 30e657c18aSPierre-Louis Bossart "Processor internal physical address or data error during instruction fetch"}, 31e657c18aSPierre-Louis Bossart {3, "LoadStoreErrorCause", 32e657c18aSPierre-Louis Bossart "Processor internal physical address or data error during load or store"}, 33e657c18aSPierre-Louis Bossart {4, "Level1InterruptCause", 34e657c18aSPierre-Louis Bossart "Level-1 interrupt as indicated by set level-1 bits in the INTERRUPT register"}, 35e657c18aSPierre-Louis Bossart {5, "AllocaCause", 36e657c18aSPierre-Louis Bossart "MOVSP instruction, if caller’s registers are not in the register file"}, 37e657c18aSPierre-Louis Bossart {6, "IntegerDivideByZeroCause", 38e657c18aSPierre-Louis Bossart "QUOS, QUOU, REMS, or REMU divisor operand is zero"}, 39e657c18aSPierre-Louis Bossart {8, "PrivilegedCause", 40e657c18aSPierre-Louis Bossart "Attempt to execute a privileged operation when CRING ? 0"}, 41e657c18aSPierre-Louis Bossart {9, "LoadStoreAlignmentCause", "Load or store to an unaligned address"}, 42e657c18aSPierre-Louis Bossart {12, "InstrPIFDataErrorCause", 43e657c18aSPierre-Louis Bossart "PIF data error during instruction fetch"}, 44e657c18aSPierre-Louis Bossart {13, "LoadStorePIFDataErrorCause", 45e657c18aSPierre-Louis Bossart "Synchronous PIF data error during LoadStore access"}, 46e657c18aSPierre-Louis Bossart {14, "InstrPIFAddrErrorCause", 47e657c18aSPierre-Louis Bossart "PIF address error during instruction fetch"}, 48e657c18aSPierre-Louis Bossart {15, "LoadStorePIFAddrErrorCause", 49e657c18aSPierre-Louis Bossart "Synchronous PIF address error during LoadStore access"}, 50e657c18aSPierre-Louis Bossart {16, "InstTLBMissCause", "Error during Instruction TLB refill"}, 51e657c18aSPierre-Louis Bossart {17, "InstTLBMultiHitCause", 52e657c18aSPierre-Louis Bossart "Multiple instruction TLB entries matched"}, 53e657c18aSPierre-Louis Bossart {18, "InstFetchPrivilegeCause", 54e657c18aSPierre-Louis Bossart "An instruction fetch referenced a virtual address at a ring level less than CRING"}, 55e657c18aSPierre-Louis Bossart {20, "InstFetchProhibitedCause", 56e657c18aSPierre-Louis Bossart "An instruction fetch referenced a page mapped with an attribute that does not permit instruction fetch"}, 57e657c18aSPierre-Louis Bossart {24, "LoadStoreTLBMissCause", 58e657c18aSPierre-Louis Bossart "Error during TLB refill for a load or store"}, 59e657c18aSPierre-Louis Bossart {25, "LoadStoreTLBMultiHitCause", 60e657c18aSPierre-Louis Bossart "Multiple TLB entries matched for a load or store"}, 61e657c18aSPierre-Louis Bossart {26, "LoadStorePrivilegeCause", 62e657c18aSPierre-Louis Bossart "A load or store referenced a virtual address at a ring level less than CRING"}, 63e657c18aSPierre-Louis Bossart {28, "LoadProhibitedCause", 64e657c18aSPierre-Louis Bossart "A load referenced a page mapped with an attribute that does not permit loads"}, 65e657c18aSPierre-Louis Bossart {32, "Coprocessor0Disabled", 66e657c18aSPierre-Louis Bossart "Coprocessor 0 instruction when cp0 disabled"}, 67e657c18aSPierre-Louis Bossart {33, "Coprocessor1Disabled", 68e657c18aSPierre-Louis Bossart "Coprocessor 1 instruction when cp1 disabled"}, 69e657c18aSPierre-Louis Bossart {34, "Coprocessor2Disabled", 70e657c18aSPierre-Louis Bossart "Coprocessor 2 instruction when cp2 disabled"}, 71e657c18aSPierre-Louis Bossart {35, "Coprocessor3Disabled", 72e657c18aSPierre-Louis Bossart "Coprocessor 3 instruction when cp3 disabled"}, 73e657c18aSPierre-Louis Bossart {36, "Coprocessor4Disabled", 74e657c18aSPierre-Louis Bossart "Coprocessor 4 instruction when cp4 disabled"}, 75e657c18aSPierre-Louis Bossart {37, "Coprocessor5Disabled", 76e657c18aSPierre-Louis Bossart "Coprocessor 5 instruction when cp5 disabled"}, 77e657c18aSPierre-Louis Bossart {38, "Coprocessor6Disabled", 78e657c18aSPierre-Louis Bossart "Coprocessor 6 instruction when cp6 disabled"}, 79e657c18aSPierre-Louis Bossart {39, "Coprocessor7Disabled", 80e657c18aSPierre-Louis Bossart "Coprocessor 7 instruction when cp7 disabled"}, 81e657c18aSPierre-Louis Bossart }; 82e657c18aSPierre-Louis Bossart 83e657c18aSPierre-Louis Bossart /* only need xtensa atm */ 84b9f0bfd1SPeter Ujfalusi static void xtensa_dsp_oops(struct snd_sof_dev *sdev, const char *level, void *oops) 85e657c18aSPierre-Louis Bossart { 86e657c18aSPierre-Louis Bossart struct sof_ipc_dsp_oops_xtensa *xoops = oops; 87e657c18aSPierre-Louis Bossart int i; 88e657c18aSPierre-Louis Bossart 89b9f0bfd1SPeter Ujfalusi dev_printk(level, sdev->dev, "error: DSP Firmware Oops\n"); 90e657c18aSPierre-Louis Bossart for (i = 0; i < ARRAY_SIZE(xtensa_exception_causes); i++) { 91e657c18aSPierre-Louis Bossart if (xtensa_exception_causes[i].id == xoops->exccause) { 92b9f0bfd1SPeter Ujfalusi dev_printk(level, sdev->dev, 93b9f0bfd1SPeter Ujfalusi "error: Exception Cause: %s, %s\n", 94e657c18aSPierre-Louis Bossart xtensa_exception_causes[i].msg, 95e657c18aSPierre-Louis Bossart xtensa_exception_causes[i].description); 96e657c18aSPierre-Louis Bossart } 97e657c18aSPierre-Louis Bossart } 98b9f0bfd1SPeter Ujfalusi dev_printk(level, sdev->dev, 99b9f0bfd1SPeter Ujfalusi "EXCCAUSE 0x%8.8x EXCVADDR 0x%8.8x PS 0x%8.8x SAR 0x%8.8x\n", 100e657c18aSPierre-Louis Bossart xoops->exccause, xoops->excvaddr, xoops->ps, xoops->sar); 101b9f0bfd1SPeter Ujfalusi dev_printk(level, sdev->dev, 102b9f0bfd1SPeter Ujfalusi "EPC1 0x%8.8x EPC2 0x%8.8x EPC3 0x%8.8x EPC4 0x%8.8x", 103e657c18aSPierre-Louis Bossart xoops->epc1, xoops->epc2, xoops->epc3, xoops->epc4); 104b9f0bfd1SPeter Ujfalusi dev_printk(level, sdev->dev, 105b9f0bfd1SPeter Ujfalusi "EPC5 0x%8.8x EPC6 0x%8.8x EPC7 0x%8.8x DEPC 0x%8.8x", 106e657c18aSPierre-Louis Bossart xoops->epc5, xoops->epc6, xoops->epc7, xoops->depc); 107b9f0bfd1SPeter Ujfalusi dev_printk(level, sdev->dev, 108b9f0bfd1SPeter Ujfalusi "EPS2 0x%8.8x EPS3 0x%8.8x EPS4 0x%8.8x EPS5 0x%8.8x", 109e657c18aSPierre-Louis Bossart xoops->eps2, xoops->eps3, xoops->eps4, xoops->eps5); 110b9f0bfd1SPeter Ujfalusi dev_printk(level, sdev->dev, 111b9f0bfd1SPeter Ujfalusi "EPS6 0x%8.8x EPS7 0x%8.8x INTENABL 0x%8.8x INTERRU 0x%8.8x", 112e657c18aSPierre-Louis Bossart xoops->eps6, xoops->eps7, xoops->intenable, xoops->interrupt); 113e657c18aSPierre-Louis Bossart } 114e657c18aSPierre-Louis Bossart 115b9f0bfd1SPeter Ujfalusi static void xtensa_stack(struct snd_sof_dev *sdev, const char *level, void *oops, 116b9f0bfd1SPeter Ujfalusi u32 *stack, u32 stack_words) 117e657c18aSPierre-Louis Bossart { 118e657c18aSPierre-Louis Bossart struct sof_ipc_dsp_oops_xtensa *xoops = oops; 11914104eb6SKai Vehmanen u32 stack_ptr = xoops->plat_hdr.stackptr; 120e657c18aSPierre-Louis Bossart /* 4 * 8chars + 3 ws + 1 terminating NUL */ 121e657c18aSPierre-Louis Bossart unsigned char buf[4 * 8 + 3 + 1]; 122e657c18aSPierre-Louis Bossart int i; 123e657c18aSPierre-Louis Bossart 124b9f0bfd1SPeter Ujfalusi dev_printk(level, sdev->dev, "stack dump from 0x%8.8x\n", stack_ptr); 125e657c18aSPierre-Louis Bossart 126e657c18aSPierre-Louis Bossart /* 127e657c18aSPierre-Louis Bossart * example output: 128e657c18aSPierre-Louis Bossart * 0x0049fbb0: 8000f2d0 0049fc00 6f6c6c61 00632e63 129e657c18aSPierre-Louis Bossart */ 130e657c18aSPierre-Louis Bossart for (i = 0; i < stack_words; i += 4) { 131ac4dfccbSYong Zhi hex_dump_to_buffer(stack + i, 16, 16, 4, 132e657c18aSPierre-Louis Bossart buf, sizeof(buf), false); 133b9f0bfd1SPeter Ujfalusi dev_printk(level, sdev->dev, "0x%08x: %s\n", stack_ptr + i * 4, buf); 134e657c18aSPierre-Louis Bossart } 13558bb5081SRander Wang 13658bb5081SRander Wang if (!xoops->plat_hdr.numaregs) 13758bb5081SRander Wang return; 13858bb5081SRander Wang 13958bb5081SRander Wang dev_printk(level, sdev->dev, "AR registers:\n"); 14058bb5081SRander Wang /* the number of ar registers is a multiple of 4 */ 14158bb5081SRander Wang for (i = 0; i < xoops->plat_hdr.numaregs; i += 4) { 14258bb5081SRander Wang hex_dump_to_buffer(xoops->ar + i, 16, 16, 4, 14358bb5081SRander Wang buf, sizeof(buf), false); 14458bb5081SRander Wang dev_printk(level, sdev->dev, "%#x: %s\n", i * 4, buf); 14558bb5081SRander Wang } 146e657c18aSPierre-Louis Bossart } 147e657c18aSPierre-Louis Bossart 1480ed66cb7SPeter Ujfalusi const struct dsp_arch_ops sof_xtensa_arch_ops = { 149e657c18aSPierre-Louis Bossart .dsp_oops = xtensa_dsp_oops, 150e657c18aSPierre-Louis Bossart .dsp_stack = xtensa_stack, 151e657c18aSPierre-Louis Bossart }; 152068ac0dbSPierre-Louis Bossart EXPORT_SYMBOL_NS(sof_xtensa_arch_ops, SND_SOC_SOF_XTENSA); 153e657c18aSPierre-Louis Bossart 154e657c18aSPierre-Louis Bossart MODULE_LICENSE("Dual BSD/GPL"); 155*06a2315dSPierre-Louis Bossart MODULE_DESCRIPTION("SOF Xtensa DSP support"); 156