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/freebsd/sys/dev/qat/qat_common/
H A Dadf_transport.c52 adf_reserve_ring(struct adf_etr_bank_data *bank, u32 ring) in adf_reserve_ring() argument
54 mtx_lock(&bank->lock); in adf_reserve_ring()
55 if (bank->ring_mask & (1 << ring)) { in adf_reserve_ring()
56 mtx_unlock(&bank->lock); in adf_reserve_ring()
59 bank->ring_mask |= (1 << ring); in adf_reserve_ring()
60 mtx_unlock(&bank->lock); in adf_reserve_ring()
65 adf_unreserve_ring(struct adf_etr_bank_data *bank, u32 ring) in adf_unreserve_ring() argument
67 mtx_lock(&bank->lock); in adf_unreserve_ring()
68 bank->ring_mask &= ~(1 << ring); in adf_unreserve_ring()
69 mtx_unlock(&bank->lock); in adf_unreserve_ring()
[all …]
H A Dadf_gen2_hw_data.c13 read_csr_ring_head(struct resource *csr_base_addr, u32 bank, u32 ring) in read_csr_ring_head() argument
15 return READ_CSR_RING_HEAD(csr_base_addr, bank, ring); in read_csr_ring_head()
20 u32 bank, in write_csr_ring_head() argument
24 WRITE_CSR_RING_HEAD(csr_base_addr, bank, ring, value); in write_csr_ring_head()
28 read_csr_ring_tail(struct resource *csr_base_addr, u32 bank, u32 ring) in read_csr_ring_tail() argument
30 return READ_CSR_RING_TAIL(csr_base_addr, bank, ring); in read_csr_ring_tail()
35 u32 bank, in write_csr_ring_tail() argument
39 WRITE_CSR_RING_TAIL(csr_base_addr, bank, ring, value); in write_csr_ring_tail()
43 read_csr_e_stat(struct resource *csr_base_addr, u32 bank) in read_csr_e_stat() argument
45 return READ_CSR_E_STAT(csr_base_addr, bank); in read_csr_e_stat()
[all …]
H A Dadf_gen4vf_hw_csr_data.c13 read_csr_ring_head(struct resource *csr_base_addr, u32 bank, u32 ring) in read_csr_ring_head() argument
15 return READ_CSR_RING_HEAD_GEN4VF(csr_base_addr, bank, ring); in read_csr_ring_head()
20 u32 bank, in write_csr_ring_head() argument
24 WRITE_CSR_RING_HEAD_GEN4VF(csr_base_addr, bank, ring, value); in write_csr_ring_head()
28 read_csr_ring_tail(struct resource *csr_base_addr, u32 bank, u32 ring) in read_csr_ring_tail() argument
30 return READ_CSR_RING_TAIL_GEN4VF(csr_base_addr, bank, ring); in read_csr_ring_tail()
35 u32 bank, in write_csr_ring_tail() argument
39 WRITE_CSR_RING_TAIL_GEN4VF(csr_base_addr, bank, ring, value); in write_csr_ring_tail()
43 read_csr_e_stat(struct resource *csr_base_addr, u32 bank) in read_csr_e_stat() argument
45 return READ_CSR_E_STAT_GEN4VF(csr_base_addr, bank); in read_csr_e_stat()
[all …]
H A Dadf_freebsd_transport_debug.c21 struct adf_etr_bank_data *bank = ring->bank; in adf_ring_show() local
22 struct adf_hw_csr_ops *csr_ops = GET_CSR_OPS(bank->accel_dev); in adf_ring_show()
23 struct resource *csr = ring->bank->csr_addr; in adf_ring_show()
33 bank->bank_number, in adf_ring_show()
36 bank->bank_number, in adf_ring_show()
38 empty = csr_ops->read_csr_e_stat(csr, bank->bank_number); in adf_ring_show()
45 "ring num %d, bank num %d\n", in adf_ring_show()
47 ring->bank->bank_number); in adf_ring_show()
89 SYSCTL_ADD_PROC(&ring->bank->accel_dev->sysctl_ctx, in adf_ring_debugfs_add()
90 SYSCTL_CHILDREN(ring->bank->bank_debug_dir), in adf_ring_debugfs_add()
[all …]
H A Dadf_gen4_hw_data.c17 read_csr_ring_head(struct resource *csr_base_addr, u32 bank, u32 ring) in read_csr_ring_head() argument
19 return READ_CSR_RING_HEAD(csr_base_addr, bank, ring); in read_csr_ring_head()
24 u32 bank, in write_csr_ring_head() argument
28 WRITE_CSR_RING_HEAD(csr_base_addr, bank, ring, value); in write_csr_ring_head()
32 read_csr_ring_tail(struct resource *csr_base_addr, u32 bank, u32 ring) in read_csr_ring_tail() argument
34 return READ_CSR_RING_TAIL(csr_base_addr, bank, ring); in read_csr_ring_tail()
39 u32 bank, in write_csr_ring_tail() argument
43 WRITE_CSR_RING_TAIL(csr_base_addr, bank, ring, value); in write_csr_ring_tail()
47 read_csr_e_stat(struct resource *csr_base_addr, u32 bank) in read_csr_e_stat() argument
49 return READ_CSR_E_STAT(csr_base_addr, bank); in read_csr_e_stat()
[all …]
H A Dadf_freebsd_uio_cleanup.c45 int bank; member
63 int bank = orphan->bank; in check_orphan_ring() local
74 bank, in check_orphan_ring()
78 bank, in check_orphan_ring()
91 bank, in check_orphan_ring()
95 bank, in check_orphan_ring()
104 get_orphan_bundle(int bank, in get_orphan_bundle() argument
128 orphan_bundle->bank = bank; in get_orphan_bundle()
136 bundle = &accel->bundle[bank]; in get_orphan_bundle()
151 base = csr_ops->read_csr_ring_base(csr_base, bank, i); in get_orphan_bundle()
[all …]
/freebsd/sys/dev/qat/include/common/
H A Dadf_gen4_hw_data.h29 #define ADF_WQM_CSR_RPRESETCTL(bank) (0x6000 + ((bank) << 3)) argument
31 #define ADF_WQM_CSR_RPRESETSTS(bank) (ADF_WQM_CSR_RPRESETCTL(bank) + 4) argument
36 #define ADF_WQM_CSR_RPRESETCTL(bank) (0x6000 + ((bank) << 3)) argument
39 #define ADF_WQM_CSR_RPRESETSTS(bank) (ADF_WQM_CSR_RPRESETCTL(bank) + 4) argument
43 #define READ_CSR_RING_HEAD(csr_base_addr, bank, ring) \ argument
45 ADF_RING_CSR_ADDR_OFFSET + ADF_RING_BUNDLE_SIZE * (bank) + \
47 #define READ_CSR_RING_TAIL(csr_base_addr, bank, ring) \ argument
49 ADF_RING_CSR_ADDR_OFFSET + ADF_RING_BUNDLE_SIZE * (bank) + \
51 #define READ_CSR_E_STAT(csr_base_addr, bank) \ argument
53 ADF_RING_CSR_ADDR_OFFSET + ADF_RING_BUNDLE_SIZE * (bank) + \
[all …]
H A Dadf_transport_access_macros.h79 #define READ_CSR_RING_HEAD(csr_base_addr, bank, ring) \ argument
81 (ADF_RING_BUNDLE_SIZE * bank) + ADF_RING_CSR_RING_HEAD + \
83 #define READ_CSR_RING_TAIL(csr_base_addr, bank, ring) \ argument
85 (ADF_RING_BUNDLE_SIZE * bank) + ADF_RING_CSR_RING_TAIL + \
87 #define READ_CSR_E_STAT(csr_base_addr, bank) \ argument
89 (ADF_RING_BUNDLE_SIZE * bank) + ADF_RING_CSR_E_STAT)
90 #define WRITE_CSR_RING_CONFIG(csr_base_addr, bank, ring, value) \ argument
92 (ADF_RING_BUNDLE_SIZE * bank) + ADF_RING_CSR_RING_CONFIG + \
95 #define WRITE_CSR_RING_BASE(csr_base_addr, bank, ring, value) \ argument
101 (ADF_RING_BUNDLE_SIZE * bank) + \
[all …]
H A Dadf_gen2_hw_data.h32 #define READ_CSR_RING_HEAD(csr_base_addr, bank, ring) \ argument
34 (ADF_RING_BUNDLE_SIZE * (bank)) + ADF_RING_CSR_RING_HEAD + \
36 #define READ_CSR_RING_TAIL(csr_base_addr, bank, ring) \ argument
38 (ADF_RING_BUNDLE_SIZE * (bank)) + ADF_RING_CSR_RING_TAIL + \
40 #define READ_CSR_E_STAT(csr_base_addr, bank) \ argument
42 (ADF_RING_BUNDLE_SIZE * (bank)) + ADF_RING_CSR_E_STAT)
43 #define WRITE_CSR_RING_CONFIG(csr_base_addr, bank, ring, value) \ argument
45 (ADF_RING_BUNDLE_SIZE * (bank)) + \
50 read_base(struct resource *csr_base_addr, u32 bank, u32 ring) in read_base() argument
56 (ADF_RING_BUNDLE_SIZE * bank) + in read_base()
[all …]
/freebsd/sys/dev/qat/include/
H A Dadf_gen4vf_hw_csr_data.h28 #define READ_CSR_RING_HEAD_GEN4VF(csr_base_addr, bank, ring) \ argument
31 ADF_RING_BUNDLE_SIZE_GEN4 * (bank)) + \
33 #define READ_CSR_RING_TAIL_GEN4VF(csr_base_addr, bank, ring) \ argument
36 ADF_RING_BUNDLE_SIZE_GEN4 * (bank)) + \
38 #define READ_CSR_E_STAT_GEN4VF(csr_base_addr, bank) \ argument
41 ADF_RING_BUNDLE_SIZE_GEN4 * (bank)) + \
43 #define WRITE_CSR_RING_CONFIG_GEN4VF(csr_base_addr, bank, ring, value) \ argument
46 ADF_RING_BUNDLE_SIZE_GEN4 * (bank)) + \
49 #define WRITE_CSR_RING_BASE_GEN4VF(csr_base_addr, bank, ring, value) \ argument
52 u32 _bank = bank; \
[all …]
/freebsd/tools/test/xregs_sig/
H A Dxregs_sig.c123 fill_xregs(uint8_t *xregs, int bank) in fill_xregs() argument
125 arc4random_buf(xregs, xregs_banks[bank].regs * xregs_banks[bank].bytes); in fill_xregs()
129 dump_xregs(const uint8_t *r, int bank) in dump_xregs() argument
133 for (k = 0; k < xregs_banks[bank].bytes; k++) { in dump_xregs()
144 show_diff(const uint8_t *xregs1, const uint8_t *xregs2, int bank) in show_diff() argument
154 for (i = 0; i < xregs_banks[bank].regs; i++) { in show_diff()
155 r1 = xregs1 + i * xregs_banks[bank].bytes; in show_diff()
156 r2 = xregs2 + i * xregs_banks[bank].bytes; in show_diff()
157 for (j = 0; j < xregs_banks[bank].bytes; j++) { in show_diff()
159 printf("%%%s%u\n", xregs_banks[bank].r_name, i); in show_diff()
[all …]
/freebsd/sys/dev/powermac_nvram/
H A Dpowermac_nvram.c225 void *bank; in powermac_nvram_close() local
249 bank = (sc->sc_bank == sc->sc_bank0) ? sc->sc_bank1 : sc->sc_bank0; in powermac_nvram_close()
250 if (erase_bank(sc->sc_dev, bank) != 0 || in powermac_nvram_close()
251 write_bank(sc->sc_dev, bank, sc->sc_data) != 0) { in powermac_nvram_close()
256 sc->sc_bank = bank; in powermac_nvram_close()
376 wait_operation_complete_amd(uint8_t *bank) in wait_operation_complete_amd() argument
381 if ((inb(bank) ^ inb(bank)) == 0) in wait_operation_complete_amd()
387 erase_bank_amd(device_t dev, uint8_t *bank) in erase_bank_amd() argument
392 OUTB_DELAY(bank + 0x555, 0xaa); in erase_bank_amd()
394 OUTB_DELAY(bank + 0x2aa, 0x55); in erase_bank_amd()
[all …]
/freebsd/sys/contrib/device-tree/src/arm/samsung/
H A Dexynos5410-pinctrl.dtsi12 gpa0: gpa0-gpio-bank {
20 gpa1: gpa1-gpio-bank {
28 gpa2: gpa2-gpio-bank {
36 gpb0: gpb0-gpio-bank {
44 gpb1: gpb1-gpio-bank {
52 gpb2: gpb2-gpio-bank {
60 gpb3: gpb3-gpio-bank {
68 gpc0: gpc0-gpio-bank {
76 gpc3: gpc3-gpio-bank {
84 gpc1: gpc1-gpio-bank {
[all …]
H A Dexynos5250-pinctrl.dtsi15 gpa0: gpa0-gpio-bank {
23 gpa1: gpa1-gpio-bank {
31 gpa2: gpa2-gpio-bank {
39 gpb0: gpb0-gpio-bank {
47 gpb1: gpb1-gpio-bank {
55 gpb2: gpb2-gpio-bank {
63 gpb3: gpb3-gpio-bank {
71 gpc0: gpc0-gpio-bank {
79 gpc1: gpc1-gpio-bank {
87 gpc2: gpc2-gpio-bank {
[all …]
H A Dexynos5420-pinctrl.dtsi15 gpy7: gpy7-gpio-bank {
23 gpx0: gpx0-gpio-bank {
34 gpx1: gpx1-gpio-bank {
45 gpx2: gpx2-gpio-bank {
53 gpx3: gpx3-gpio-bank {
77 gpc0: gpc0-gpio-bank {
85 gpc1: gpc1-gpio-bank {
93 gpc2: gpc2-gpio-bank {
101 gpc3: gpc3-gpio-bank {
109 gpc4: gpc4-gpio-bank {
[all …]
/freebsd/sys/contrib/device-tree/Bindings/pinctrl/
H A Dpinctrl-st.txt14 GPIO bank can have one of the two possible types of interrupt-wirings.
20 | |----> [gpio-bank (n) ]
21 | |----> [gpio-bank (n + 1)]
22 [irqN]-- | irq-mux |----> [gpio-bank (n + 2)]
23 | |----> [gpio-bank (... )]
24 |_________|----> [gpio-bank (n + 7)]
26 Second type has a dedicated interrupt per gpio bank.
28 [irqN]----> [gpio-bank (n)]
37 bank are capable of retiming. Retiming is mainly used to improve the
39 - ranges : defines mapping between pin controller node (parent) to gpio-bank
[all …]
/freebsd/contrib/llvm-project/llvm/utils/TableGen/
H A DRegisterBankEmitter.cpp1 //===- RegisterBankEmitter.cpp - Generate a Register Bank Desc. -*- C++ -*-===//
10 // register bank for a code generator.
23 #define DEBUG_TYPE "register-bank-emitter"
30 /// A vector of register classes that are included in the register bank.
36 /// The register classes that are covered by the register bank.
46 /// Get the human-readable name for the bank.
73 /// Add a register class to the bank without duplicates.
139 for (const auto &Bank : Banks) in emitHeader() local
140 OS << " " << Bank.getEnumeratorName() << " = " << ID++ << ",\n"; in emitHeader()
159 /// Visit each register class belonging to the given register bank.
[all …]
/freebsd/sys/arm64/rockchip/
H A Drk_pinctrl.c58 uint32_t bank; member
66 uint32_t bank; member
73 uint32_t bank; member
82 uint32_t bank; member
120 .bank = _bank, \
128 .bank = _bank, \
137 .bank = _bank, \
145 .bank = _bank, \
162 /* bank sub offs nbits */
204 /* bank sub offs val ma */
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/tesla/
H A Dfsd-pinctrl.dtsi14 gpf0: gpf0-gpio-bank {
22 gpf1: gpf1-gpio-bank {
30 gpf6: gpf6-gpio-bank {
38 gpf4: gpf4-gpio-bank {
46 gpf5: gpf5-gpio-bank {
70 gpc8: gpc8-gpio-bank {
78 gpf2: gpf2-gpio-bank {
86 gpf3: gpf3-gpio-bank {
94 gpd0: gpd0-gpio-bank {
102 gpb0: gpb0-gpio-bank {
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/exynos/
H A Dexynos7-pinctrl.dtsi15 gpa0: gpa0-gpio-bank {
32 gpa1: gpa1-gpio-bank {
49 gpa2: gpa2-gpio-bank {
57 gpa3: gpa3-gpio-bank {
67 gpb0: gpb0-gpio-bank {
75 gpc0: gpc0-gpio-bank {
83 gpc1: gpc1-gpio-bank {
91 gpc2: gpc2-gpio-bank {
99 gpc3: gpc3-gpio-bank {
107 gpd0: gpd0-gpio-bank {
[all …]
H A Dexynos5433-pinctrl.dtsi32 gpa0: gpa0-gpio-bank {
49 gpa1: gpa1-gpio-bank {
66 gpa2: gpa2-gpio-bank {
74 gpa3: gpa3-gpio-bank {
82 gpf1: gpf1-gpio-bank {
90 gpf2: gpf2-gpio-bank {
98 gpf3: gpf3-gpio-bank {
106 gpf4: gpf4-gpio-bank {
114 gpf5: gpf5-gpio-bank {
124 gpz0: gpz0-gpio-bank {
[all …]
/freebsd/sys/dev/smc/
H A Dif_smcreg.h31 /* All Banks, Offset 0xe: Bank Select Register */
33 #define BSR_BANK_MASK 0x0007 /* Which bank is currently selected */
37 /* Bank 0, Offset 0x0: Transmit Control Register */
50 /* Bank 0, Offset 0x2: EPH Status Register */
67 /* Bank 0, Offset 0x4: Receive Control Register */
78 /* Bank 0, Offset 0x6: Counter Register */
89 /* Bank 0, Offset 0x8: Memory Information Register */
97 /* Bank 0, Offset 0xa: Receive/PHY Control Reigster */
114 /* Bank 1, Offset 0x0: Configuration Register */
121 /* Bank 1, Offset 0x2: Base Address Register */
[all …]
/freebsd/sys/contrib/device-tree/Bindings/soc/fsl/cpm_qe/
H A Dgpio.txt10 - compatible : "fsl,cpm1-pario-bank-a", "fsl,cpm1-pario-bank-b",
11 "fsl,cpm1-pario-bank-c", "fsl,cpm1-pario-bank-d",
12 "fsl,cpm1-pario-bank-e", "fsl,cpm2-pario-bank"
29 compatible = "fsl,cpm1-pario-bank-a";
36 compatible = "fsl,cpm1-pario-bank-b";
43 compatible = "fsl,cpm1-pario-bank-c";
53 compatible = "fsl,cpm1-pario-bank-e";
/freebsd/sys/dev/ice/
H A Dice_nvm.c449 * ice_get_flash_bank_offset - Get offset into requested flash bank in ice_release_nvm()
451 * @bank: whether to read from the active or inactive flash bank
460 static u32 ice_get_flash_bank_offset(struct ice_hw *hw, enum ice_bank_select bank, u16 module)
496 ice_debug(hw, ICE_DBG_NVM, "Unexpected value for active flash bank: %u\n", in ice_get_flash_bank_offset()
501 /* The second flash bank is stored immediately following the first in ice_get_flash_bank_offset()
502 * bank. Based on whether the 1st or 2nd bank is active, and whether in ice_get_flash_bank_offset()
503 * we want the active or inactive bank, calculate the desired offset. in ice_get_flash_bank_offset()
505 switch (bank) { in ice_get_flash_bank_offset()
463 ice_get_flash_bank_offset(struct ice_hw * hw,enum ice_bank_select bank,u16 module) ice_get_flash_bank_offset() argument
537 ice_read_flash_module(struct ice_hw * hw,enum ice_bank_select bank,u16 module,u32 offset,u8 * data,u32 length) ice_read_flash_module() argument
574 ice_read_nvm_module(struct ice_hw * hw,enum ice_bank_select bank,u32 offset,u16 * data) ice_read_nvm_module() argument
597 ice_get_nvm_css_hdr_len(struct ice_hw * hw,enum ice_bank_select bank,u32 * hdr_len) ice_get_nvm_css_hdr_len() argument
634 ice_read_nvm_sr_copy(struct ice_hw * hw,enum ice_bank_select bank,u32 offset,u16 * data) ice_read_nvm_sr_copy() argument
660 ice_read_orom_module(struct ice_hw * hw,enum ice_bank_select bank,u32 offset,u16 * data) ice_read_orom_module() argument
683 ice_read_netlist_module(struct ice_hw * hw,enum ice_bank_select bank,u32 offset,u16 * data) ice_read_netlist_module() argument
851 ice_get_nvm_srev(struct ice_hw * hw,enum ice_bank_select bank,u32 * srev) ice_get_nvm_srev() argument
879 ice_get_nvm_ver_info(struct ice_hw * hw,enum ice_bank_select bank,struct ice_nvm_info * nvm) ice_get_nvm_ver_info() argument
936 ice_get_orom_srev(struct ice_hw * hw,enum ice_bank_select bank,u32 * srev) ice_get_orom_srev() argument
981 ice_get_orom_civd_data(struct ice_hw * hw,enum ice_bank_select bank,struct ice_orom_civd_info * civd) ice_get_orom_civd_data() argument
1058 ice_get_orom_ver_info(struct ice_hw * hw,enum ice_bank_select bank,struct ice_orom_info * orom) ice_get_orom_ver_info() argument
1110 ice_get_netlist_info(struct ice_hw * hw,enum ice_bank_select bank,struct ice_netlist_info * netlist) ice_get_netlist_info() argument
[all...]
/freebsd/sys/arm/broadcom/bcm2835/
H A Dbcm2835_gpio.c94 { SYS_RES_IRQ, 0, RF_ACTIVE }, /* bank 0 interrupt */
95 { SYS_RES_IRQ, 1, RF_ACTIVE }, /* bank 1 interrupt */
196 uint32_t bank, func, offset; in bcm_gpio_get_function() local
198 /* Five banks, 10 pins per bank, 3 bits per pin. */ in bcm_gpio_get_function()
199 bank = pin / 10; in bcm_gpio_get_function()
200 offset = (pin - bank * 10) * 3; in bcm_gpio_get_function()
203 func = (BCM_GPIO_READ(sc, BCM_GPIO_GPFSEL(bank)) >> offset) & 7; in bcm_gpio_get_function()
285 uint32_t bank, data, offset; in bcm_gpio_set_function() local
290 /* Five banks, 10 pins per bank, 3 bits per pin. */ in bcm_gpio_set_function()
291 bank = pin / 10; in bcm_gpio_set_function()
[all …]

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