1 /* SPDX-License-Identifier: BSD-3-Clause */
2 /* Copyright(c) 2007-2022 Intel Corporation */
3 #ifndef ADF_GEN4VF_HW_CSR_DATA_H_
4 #define ADF_GEN4VF_HW_CSR_DATA_H_
5
6 #define ADF_RING_CSR_ADDR_OFFSET_GEN4VF 0x0
7 #define ADF_RING_BUNDLE_SIZE_GEN4 0x2000
8 #define ADF_RING_CSR_RING_HEAD 0x0C0
9 #define ADF_RING_CSR_RING_TAIL 0x100
10 #define ADF_RING_CSR_E_STAT 0x14C
11 #define ADF_RING_CSR_RING_CONFIG_GEN4 0x1000
12 #define ADF_RING_CSR_RING_LBASE_GEN4 0x1040
13 #define ADF_RING_CSR_RING_UBASE_GEN4 0x1080
14 #define ADF_RING_CSR_INT_FLAG 0x170
15 #define ADF_RING_CSR_INT_FLAG_AND_COL 0x184
16 #define ADF_RING_CSR_NEXT_INT_SRCSEL 0x4
17 #define ADF_RING_CSR_INT_SRCSEL 0x174
18 #define ADF_RING_CSR_INT_COL_EN 0x17C
19 #define ADF_RING_CSR_INT_COL_CTL 0x180
20 #define ADF_RING_CSR_RING_SRV_ARB_EN 0x19C
21 #define ADF_BANK_INT_SRC_SEL_MASK_GEN4 0x44UL
22 #define ADF_RING_CSR_INT_COL_CTL_ENABLE 0x80000000
23 #define ADF_BANK_INT_FLAG_CLEAR_MASK_GEN4 0x3
24 #define ADF_RINGS_PER_INT_SRCSEL_GEN4 2
25
26 #define BUILD_RING_BASE_ADDR_GEN4(addr, size) \
27 ((((addr) >> 6) & (0xFFFFFFFFFFFFFFFFULL << (size))) << 6)
28 #define READ_CSR_RING_HEAD_GEN4VF(csr_base_addr, bank, ring) \
29 ADF_CSR_RD((csr_base_addr), \
30 (ADF_RING_CSR_ADDR_OFFSET_GEN4VF + \
31 ADF_RING_BUNDLE_SIZE_GEN4 * (bank)) + \
32 ADF_RING_CSR_RING_HEAD + ((ring) << 2))
33 #define READ_CSR_RING_TAIL_GEN4VF(csr_base_addr, bank, ring) \
34 ADF_CSR_RD((csr_base_addr), \
35 (ADF_RING_CSR_ADDR_OFFSET_GEN4VF + \
36 ADF_RING_BUNDLE_SIZE_GEN4 * (bank)) + \
37 ADF_RING_CSR_RING_TAIL + ((ring) << 2))
38 #define READ_CSR_E_STAT_GEN4VF(csr_base_addr, bank) \
39 ADF_CSR_RD((csr_base_addr), \
40 (ADF_RING_CSR_ADDR_OFFSET_GEN4VF + \
41 ADF_RING_BUNDLE_SIZE_GEN4 * (bank)) + \
42 ADF_RING_CSR_E_STAT)
43 #define WRITE_CSR_RING_CONFIG_GEN4VF(csr_base_addr, bank, ring, value) \
44 ADF_CSR_WR((csr_base_addr), \
45 (ADF_RING_CSR_ADDR_OFFSET_GEN4VF + \
46 ADF_RING_BUNDLE_SIZE_GEN4 * (bank)) + \
47 ADF_RING_CSR_RING_CONFIG_GEN4 + ((ring) << 2), \
48 (value))
49 #define WRITE_CSR_RING_BASE_GEN4VF(csr_base_addr, bank, ring, value) \
50 do { \
51 struct resource *_csr_base_addr = csr_base_addr; \
52 u32 _bank = bank; \
53 u32 _ring = ring; \
54 dma_addr_t _value = value; \
55 u32 l_base = 0, u_base = 0; \
56 l_base = (u32)((_value)&0xFFFFFFFF); \
57 u_base = (u32)(((_value)&0xFFFFFFFF00000000ULL) >> 32); \
58 ADF_CSR_WR((_csr_base_addr), \
59 (ADF_RING_CSR_ADDR_OFFSET_GEN4VF + \
60 ADF_RING_BUNDLE_SIZE_GEN4 * (_bank)) + \
61 ADF_RING_CSR_RING_LBASE_GEN4 + ((_ring) << 2), \
62 l_base); \
63 ADF_CSR_WR((_csr_base_addr), \
64 (ADF_RING_CSR_ADDR_OFFSET_GEN4VF + \
65 ADF_RING_BUNDLE_SIZE_GEN4 * (_bank)) + \
66 ADF_RING_CSR_RING_UBASE_GEN4 + ((_ring) << 2), \
67 u_base); \
68 } while (0)
69
70 static inline u64
read_base_gen4vf(struct resource * csr_base_addr,u32 bank,u32 ring)71 read_base_gen4vf(struct resource *csr_base_addr, u32 bank, u32 ring)
72 {
73 u32 l_base, u_base;
74 u64 addr;
75
76 l_base = ADF_CSR_RD(csr_base_addr,
77 (ADF_RING_BUNDLE_SIZE_GEN4 * bank) +
78 ADF_RING_CSR_RING_LBASE_GEN4 + (ring << 2));
79 u_base = ADF_CSR_RD(csr_base_addr,
80 (ADF_RING_BUNDLE_SIZE_GEN4 * bank) +
81 ADF_RING_CSR_RING_UBASE_GEN4 + (ring << 2));
82
83 addr = (u64)l_base & 0x00000000FFFFFFFFULL;
84 addr |= (u64)u_base << 32 & 0xFFFFFFFF00000000ULL;
85
86 return addr;
87 }
88
89 #define WRITE_CSR_INT_SRCSEL_GEN4VF(csr_base_addr, bank) \
90 ADF_CSR_WR((csr_base_addr), \
91 ADF_RING_CSR_ADDR_OFFSET_GEN4VF + \
92 ADF_RING_BUNDLE_SIZE_GEN4 * (bank) + \
93 ADF_RING_CSR_INT_SRCSEL, \
94 ADF_BANK_INT_SRC_SEL_MASK_GEN4)
95
96 #define READ_CSR_RING_BASE_GEN4VF(csr_base_addr, bank, ring) \
97 read_base_gen4vf((csr_base_addr), (bank), (ring))
98
99 #define WRITE_CSR_RING_HEAD_GEN4VF(csr_base_addr, bank, ring, value) \
100 ADF_CSR_WR((csr_base_addr), \
101 (ADF_RING_CSR_ADDR_OFFSET_GEN4VF + \
102 ADF_RING_BUNDLE_SIZE_GEN4 * (bank)) + \
103 ADF_RING_CSR_RING_HEAD + ((ring) << 2), \
104 (value))
105 #define WRITE_CSR_RING_TAIL_GEN4VF(csr_base_addr, bank, ring, value) \
106 ADF_CSR_WR((csr_base_addr), \
107 (ADF_RING_CSR_ADDR_OFFSET_GEN4VF + \
108 ADF_RING_BUNDLE_SIZE_GEN4 * (bank)) + \
109 ADF_RING_CSR_RING_TAIL + ((ring) << 2), \
110 (value))
111 #define WRITE_CSR_INT_FLAG_GEN4VF(csr_base_addr, bank, value) \
112 ADF_CSR_WR((csr_base_addr), \
113 (ADF_RING_CSR_ADDR_OFFSET_GEN4VF + \
114 ADF_RING_BUNDLE_SIZE_GEN4 * (bank)) + \
115 ADF_RING_CSR_INT_FLAG, \
116 (value))
117 #define WRITE_CSR_INT_COL_EN_GEN4VF(csr_base_addr, bank, value) \
118 ADF_CSR_WR((csr_base_addr), \
119 (ADF_RING_CSR_ADDR_OFFSET_GEN4VF + \
120 ADF_RING_BUNDLE_SIZE_GEN4 * (bank)) + \
121 ADF_RING_CSR_INT_COL_EN, \
122 (value))
123 #define WRITE_CSR_INT_COL_CTL_GEN4VF(csr_base_addr, bank, value) \
124 ADF_CSR_WR((csr_base_addr), \
125 (ADF_RING_CSR_ADDR_OFFSET_GEN4VF + \
126 ADF_RING_BUNDLE_SIZE_GEN4 * (bank)) + \
127 ADF_RING_CSR_INT_COL_CTL, \
128 (value))
129 #define WRITE_CSR_INT_FLAG_AND_COL_GEN4VF(csr_base_addr, bank, value) \
130 ADF_CSR_WR((csr_base_addr), \
131 (ADF_RING_CSR_ADDR_OFFSET_GEN4VF + \
132 ADF_RING_BUNDLE_SIZE_GEN4 * (bank)) + \
133 ADF_RING_CSR_INT_FLAG_AND_COL, \
134 (value))
135 #define READ_CSR_RING_SRV_ARB_EN_GEN4VF(csr_base_addr, bank) \
136 ADF_CSR_RD((csr_base_addr), \
137 (ADF_RING_CSR_ADDR_OFFSET_GEN4VF + \
138 ADF_RING_BUNDLE_SIZE_GEN4 * (bank)) + \
139 ADF_RING_CSR_RING_SRV_ARB_EN)
140 #define WRITE_CSR_RING_SRV_ARB_EN_GEN4VF(csr_base_addr, bank, value) \
141 ADF_CSR_WR((csr_base_addr), \
142 (ADF_RING_CSR_ADDR_OFFSET_GEN4VF + \
143 ADF_RING_BUNDLE_SIZE_GEN4 * (bank)) + \
144 ADF_RING_CSR_RING_SRV_ARB_EN, \
145 (value))
146
147 struct adf_hw_csr_info;
148 void gen4vf_init_hw_csr_info(struct adf_hw_csr_info *csr_info);
149
150 #endif /* ADF_GEN4VF_HW_CSR_DATA_H_ */
151