1 /* SPDX-License-Identifier: BSD-3-Clause */
2 /* Copyright(c) 2007-2022 Intel Corporation */
3 #ifndef ADF_TRANSPORT_ACCESS_MACROS_H
4 #define ADF_TRANSPORT_ACCESS_MACROS_H
5
6 #include "adf_accel_devices.h"
7 #define ADF_BANK_INT_SRC_SEL_MASK_0 0x4444444CUL
8 #define ADF_BANK_INT_SRC_SEL_MASK_X 0x44444444UL
9 #define ADF_BANK_INT_FLAG_CLEAR_MASK 0xFFFF
10 #define ADF_RING_CSR_RING_CONFIG 0x000
11 #define ADF_RING_CSR_RING_LBASE 0x040
12 #define ADF_RING_CSR_RING_UBASE 0x080
13 #define ADF_RING_CSR_RING_HEAD 0x0C0
14 #define ADF_RING_CSR_RING_TAIL 0x100
15 #define ADF_RING_CSR_E_STAT 0x14C
16 #define ADF_RING_CSR_INT_FLAG 0x170
17 #define ADF_RING_CSR_INT_SRCSEL 0x174
18 #define ADF_RING_CSR_INT_SRCSEL_2 0x178
19 #define ADF_RING_CSR_INT_COL_EN 0x17C
20 #define ADF_RING_CSR_INT_COL_CTL 0x180
21 #define ADF_RING_CSR_INT_FLAG_AND_COL 0x184
22 #define ADF_RING_CSR_INT_COL_CTL_ENABLE 0x80000000
23 #define ADF_RING_BUNDLE_SIZE 0x1000
24 #define ADF_RING_CONFIG_NEAR_FULL_WM 0x0A
25 #define ADF_RING_CONFIG_NEAR_EMPTY_WM 0x05
26 #define ADF_COALESCING_MIN_TIME 0x1FF
27 #define ADF_COALESCING_MAX_TIME 0xFFFFF
28 #define ADF_COALESCING_DEF_TIME 0x27FF
29 #define ADF_RING_NEAR_WATERMARK_512 0x08
30 #define ADF_RING_NEAR_WATERMARK_0 0x00
31 #define ADF_RING_EMPTY_SIG 0x7F7F7F7F
32
33 /* Valid internal ring size values */
34 #define ADF_RING_SIZE_128 0x01
35 #define ADF_RING_SIZE_256 0x02
36 #define ADF_RING_SIZE_512 0x03
37 #define ADF_RING_SIZE_4K 0x06
38 #define ADF_RING_SIZE_16K 0x08
39 #define ADF_RING_SIZE_4M 0x10
40 #define ADF_MIN_RING_SIZE ADF_RING_SIZE_128
41 #define ADF_MAX_RING_SIZE ADF_RING_SIZE_4M
42 #define ADF_DEFAULT_RING_SIZE ADF_RING_SIZE_16K
43
44 /* Valid internal msg size values */
45 #define ADF_MSG_SIZE_32 0x01
46 #define ADF_MSG_SIZE_64 0x02
47 #define ADF_MSG_SIZE_128 0x04
48 #define ADF_MIN_MSG_SIZE ADF_MSG_SIZE_32
49 #define ADF_MAX_MSG_SIZE ADF_MSG_SIZE_128
50
51 /* Size to bytes conversion macros for ring and msg size values */
52 #define ADF_MSG_SIZE_TO_BYTES(SIZE) (SIZE << 5)
53 #define ADF_BYTES_TO_MSG_SIZE(SIZE) (SIZE >> 5)
54 #define ADF_SIZE_TO_RING_SIZE_IN_BYTES(SIZE) ((1 << (SIZE - 1)) << 7)
55 #define ADF_RING_SIZE_IN_BYTES_TO_SIZE(SIZE) ((1 << (SIZE - 1)) >> 7)
56
57 /* Set the response quota to a high number */
58 #define ADF_NO_RESPONSE_QUOTA 0xFFFFFFFF
59
60 /* Minimum ring bufer size for memory allocation */
61 #define ADF_RING_SIZE_BYTES_MIN(SIZE) \
62 ((SIZE < ADF_SIZE_TO_RING_SIZE_IN_BYTES(ADF_RING_SIZE_4K)) ? \
63 ADF_SIZE_TO_RING_SIZE_IN_BYTES(ADF_RING_SIZE_4K) : \
64 SIZE)
65 #define ADF_RING_SIZE_MODULO(SIZE) (SIZE + 0x6)
66 #define ADF_SIZE_TO_POW(SIZE) \
67 ((((SIZE & 0x4) >> 1) | ((SIZE & 0x4) >> 2) | SIZE) & ~0x4)
68 /* Max outstanding requests */
69 #define ADF_MAX_INFLIGHTS(RING_SIZE, MSG_SIZE) \
70 ((((1 << (RING_SIZE - 1)) << 3) >> ADF_SIZE_TO_POW(MSG_SIZE)) - 1)
71 #define BUILD_RING_CONFIG(size) \
72 ((ADF_RING_NEAR_WATERMARK_0 << ADF_RING_CONFIG_NEAR_FULL_WM) | \
73 (ADF_RING_NEAR_WATERMARK_0 << ADF_RING_CONFIG_NEAR_EMPTY_WM) | size)
74 #define BUILD_RESP_RING_CONFIG(size, watermark_nf, watermark_ne) \
75 ((watermark_nf << ADF_RING_CONFIG_NEAR_FULL_WM) | \
76 (watermark_ne << ADF_RING_CONFIG_NEAR_EMPTY_WM) | size)
77 #define BUILD_RING_BASE_ADDR(addr, size) \
78 ((addr >> 6) & (0xFFFFFFFFFFFFFFFFULL << size))
79 #define READ_CSR_RING_HEAD(csr_base_addr, bank, ring) \
80 ADF_CSR_RD(csr_base_addr, \
81 (ADF_RING_BUNDLE_SIZE * bank) + ADF_RING_CSR_RING_HEAD + \
82 (ring << 2))
83 #define READ_CSR_RING_TAIL(csr_base_addr, bank, ring) \
84 ADF_CSR_RD(csr_base_addr, \
85 (ADF_RING_BUNDLE_SIZE * bank) + ADF_RING_CSR_RING_TAIL + \
86 (ring << 2))
87 #define READ_CSR_E_STAT(csr_base_addr, bank) \
88 ADF_CSR_RD(csr_base_addr, \
89 (ADF_RING_BUNDLE_SIZE * bank) + ADF_RING_CSR_E_STAT)
90 #define WRITE_CSR_RING_CONFIG(csr_base_addr, bank, ring, value) \
91 ADF_CSR_WR(csr_base_addr, \
92 (ADF_RING_BUNDLE_SIZE * bank) + ADF_RING_CSR_RING_CONFIG + \
93 (ring << 2), \
94 value)
95 #define WRITE_CSR_RING_BASE(csr_base_addr, bank, ring, value) \
96 do { \
97 uint32_t l_base = 0, u_base = 0; \
98 l_base = (uint32_t)(value & 0xFFFFFFFF); \
99 u_base = (uint32_t)((value & 0xFFFFFFFF00000000ULL) >> 32); \
100 ADF_CSR_WR(csr_base_addr, \
101 (ADF_RING_BUNDLE_SIZE * bank) + \
102 ADF_RING_CSR_RING_LBASE + (ring << 2), \
103 l_base); \
104 ADF_CSR_WR(csr_base_addr, \
105 (ADF_RING_BUNDLE_SIZE * bank) + \
106 ADF_RING_CSR_RING_UBASE + (ring << 2), \
107 u_base); \
108 } while (0)
109 static inline uint64_t
read_base(struct resource * csr_base_addr,uint32_t bank,uint32_t ring)110 read_base(struct resource *csr_base_addr, uint32_t bank, uint32_t ring)
111 {
112 uint32_t l_base, u_base;
113 uint64_t addr;
114
115 l_base = ADF_CSR_RD(csr_base_addr,
116 (ADF_RING_BUNDLE_SIZE * bank) +
117 ADF_RING_CSR_RING_LBASE + (ring << 2));
118 u_base = ADF_CSR_RD(csr_base_addr,
119 (ADF_RING_BUNDLE_SIZE * bank) +
120 ADF_RING_CSR_RING_UBASE + (ring << 2));
121
122 addr = (uint64_t)l_base & 0x00000000FFFFFFFFULL;
123 addr |= (uint64_t)u_base << 32 & 0xFFFFFFFF00000000ULL;
124
125 return addr;
126 }
127
128 #define READ_CSR_RING_BASE(csr_base_addr, bank, ring) \
129 read_base(csr_base_addr, bank, ring)
130 #define WRITE_CSR_RING_HEAD(csr_base_addr, bank, ring, value) \
131 ADF_CSR_WR(csr_base_addr, \
132 (ADF_RING_BUNDLE_SIZE * bank) + ADF_RING_CSR_RING_HEAD + \
133 (ring << 2), \
134 value)
135 #define WRITE_CSR_RING_TAIL(csr_base_addr, bank, ring, value) \
136 ADF_CSR_WR(csr_base_addr, \
137 (ADF_RING_BUNDLE_SIZE * bank) + ADF_RING_CSR_RING_TAIL + \
138 (ring << 2), \
139 value)
140 #define WRITE_CSR_INT_FLAG(csr_base_addr, bank, value) \
141 ADF_CSR_WR(csr_base_addr, \
142 (ADF_RING_BUNDLE_SIZE * (bank)) + ADF_RING_CSR_INT_FLAG, \
143 value)
144 #define WRITE_CSR_INT_SRCSEL(csr_base_addr, bank) \
145 do { \
146 ADF_CSR_WR(csr_base_addr, \
147 (ADF_RING_BUNDLE_SIZE * bank) + \
148 ADF_RING_CSR_INT_SRCSEL, \
149 ADF_BANK_INT_SRC_SEL_MASK_0); \
150 ADF_CSR_WR(csr_base_addr, \
151 (ADF_RING_BUNDLE_SIZE * bank) + \
152 ADF_RING_CSR_INT_SRCSEL_2, \
153 ADF_BANK_INT_SRC_SEL_MASK_X); \
154 } while (0)
155 #define WRITE_CSR_INT_COL_EN(csr_base_addr, bank, value) \
156 ADF_CSR_WR(csr_base_addr, \
157 (ADF_RING_BUNDLE_SIZE * bank) + ADF_RING_CSR_INT_COL_EN, \
158 value)
159 #define WRITE_CSR_INT_COL_CTL(csr_base_addr, bank, value) \
160 ADF_CSR_WR(csr_base_addr, \
161 (ADF_RING_BUNDLE_SIZE * bank) + ADF_RING_CSR_INT_COL_CTL, \
162 ADF_RING_CSR_INT_COL_CTL_ENABLE | value)
163 #define WRITE_CSR_INT_FLAG_AND_COL(csr_base_addr, bank, value) \
164 ADF_CSR_WR(csr_base_addr, \
165 (ADF_RING_BUNDLE_SIZE * bank) + \
166 ADF_RING_CSR_INT_FLAG_AND_COL, \
167 value)
168 #endif
169