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/freebsd/contrib/llvm-project/clang/lib/Headers/
H A Dmmintrin.h1 /*===---- mmintrin.h - MMX intrinsics --------------------------------------===
5 * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 *===-----------------------------------------------------------------------===
26 __attribute__((__always_inline__, __nodebug__, __target__("mmx,no-evex512"), \
27 __min_vector_width__(64)))
37 __target__("mmx,no-evex512")))
42 /// Constructs a 64-bit integer vector, setting the lower 32 bits to the
43 /// value of the 32-bit integer parameter and setting the upper 32 bits to 0.
50 /// A 32-bit integer value.
51 /// \returns A 64-bit integer vector. The lower 32 bits contain the value of the
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H A Dfmaintrin.h1 /*===---- fmaintrin.h - FMA intrinsics -------------------------------------===
5 * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 *===-----------------------------------------------------------------------===
21 /// Computes a multiply-add of 128-bit vectors of [4 x float].
29 /// A 128-bit vector of [4 x float] containing the multiplicand.
31 /// A 128-bit vector of [4 x float] containing the multiplier.
33 /// A 128-bit vector of [4 x float] containing the addend.
34 /// \returns A 128-bit vector of [4 x float] containing the result.
41 /// Computes a multiply-add of 128-bit vectors of [2 x double].
49 /// A 128-bit vector of [2 x double] containing the multiplicand.
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H A Dbmi2intrin.h1 /*===---- bmi2intrin.h - BMI2 intrinsics -----------------------------------===
5 * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 *===-----------------------------------------------------------------------===
20 /// Copies the unsigned 32-bit integer \a __X and zeroes the upper bits
21 /// starting at bit number \a __Y.
36 /// The 32-bit source value to copy.
38 /// The lower 8 bits specify the bit number of the lowest bit to zero.
39 /// \returns The partially zeroed 32-bit value.
46 /// Deposit (scatter) low-order bits from the unsigned 32-bit integer \a __X
47 /// into the 32-bit result, according to the mask in the unsigned 32-bit
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H A Dtmmintrin.h1 /*===---- tmmintrin.h - SSSE3 intrinsics -----------------------------------===
5 * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 *===-----------------------------------------------------------------------===
22 __target__("ssse3,no-evex512"), __min_vector_width__(64)))
25 __target__("mmx,ssse3,no-evex512"), \
26 __min_vector_width__(64)))
28 /// Computes the absolute value of each of the packed 8-bit signed
29 /// integers in the source operand and stores the 8-bit unsigned integer
37 /// A 64-bit vector of [8 x i8].
38 /// \returns A 64-bit integer vector containing the absolute values of the
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H A Demmintrin.h1 /*===---- emmintrin.h - SSE2 intrinsics ------------------------------------===
5 * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 *===-----------------------------------------------------------------------===
54 __target__("sse2,no-evex512"), __min_vector_width__(128)))
57 __target__("mmx,sse2,no-evex512"), __min_vector_width__(64)))
59 /// Adds lower double-precision values in both operands and returns the
60 /// sum in the lower 64 bits of the result. The upper 64 bits of the result
61 /// are copied from the upper double-precision value of the first operand.
68 /// A 128-bit vector of [2 x double] containing one of the source operands.
70 /// A 128-bit vector of [2 x double] containing one of the source operands.
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H A Dbmiintrin.h1 /*===---- bmiintrin.h - BMI intrinsics -------------------------------------===
5 * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 *===-----------------------------------------------------------------------===
17 /* Allow using the tzcnt intrinsics even for non-BMI targets. Since the TZCNT
18 instruction behaves as BSF on non-BMI targets, there is code that expects
29 /// An unsigned 16-bit integer whose trailing zeros are to be counted.
30 /// \returns An unsigned 16-bit integer containing the number of trailing zero
50 /// An unsigned 16-bit integer whose trailing zeros are to be counted.
51 /// \returns An unsigned 16-bit integer containing the number of trailing zero
63 /// An unsigned 32-bit integer whose trailing zeros are to be counted.
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H A Draointintrin.h1 /*===----------------------- raointintrin.h - RAOINT ------------------------===
5 * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 *===-----------------------------------------------------------------------===
20 /// Atomically add a 32-bit value at memory operand \a __A and a 32-bit \a __B,
31 /// A pointer to a 32-bit memory location.
33 /// A 32-bit integer value.
42 /// Atomically and a 32-bit value at memory operand \a __A and a 32-bit \a __B,
53 /// A pointer to a 32-bit memory location.
55 /// A 32-bit integer value.
64 /// Atomically or a 32-bit value at memory operand \a __A and a 32-bit \a __B,
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H A Dia32intrin.h1 /* ===-------- ia32intrin.h ---------------------------------------------------===
5 * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 *===-----------------------------------------------------------------------===
29 /// Finds the first set bit starting from the least significant bit. The result
38 /// A 32-bit integer operand.
39 /// \returns A 32-bit integer containing the bit number.
46 /// Finds the first set bit starting from the most significant bit. The result
55 /// A 32-bit integer operand.
56 /// \returns A 32-bit integer containing the bit number.
60 return 31 - __builtin_clz((unsigned int)__A); in __bsrd()
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H A Dxmmintrin.h1 /*===---- xmmintrin.h - SSE intrinsics -------------------------------------===
5 * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 *===-----------------------------------------------------------------------===
36 __attribute__((__always_inline__, __nodebug__, __target__("sse,no-evex512"), \
40 __target__("mmx,sse,no-evex512"), __min_vector_width__(64)))
42 /// Adds the 32-bit float values in the low-order bits of the operands.
49 /// A 128-bit vector of [4 x float] containing one of the source operands.
52 /// A 128-bit vector of [4 x float] containing one of the source operands.
54 /// \returns A 128-bit vector of [4 x float] whose lower 32 bits contain the sum
64 /// Adds two 128-bit vectors of [4 x float], and returns the results of
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H A Davxifmaintrin.h1 /*===----------------- avxifmaintrin.h - IFMA intrinsics -------------------===
5 * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 *===-----------------------------------------------------------------------===
25 // must vex-encoding
27 /// Multiply packed unsigned 52-bit integers in each 64-bit element of \a __Y
28 /// and \a __Z to form a 104-bit intermediate result. Add the high 52-bit
30 /// unsigned 64-bit integer in \a __X, and store the results in \a dst.
44 /// A 128-bit vector of [2 x i64]
46 /// A 128-bit vector of [2 x i64]
48 /// A 128-bit vector of [2 x i64]
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/freebsd/secure/lib/libcrypto/man/man3/
H A DOPENSSL_ia32cap.318 .\" Set up some character translations and predefined strings. \*(-- will
24 .tr \(*W-
27 . ds -- \(*W-
29 . if (\n(.H=4u)&(1m=24u) .ds -- \(*W\h'-12u'\(*W\h'-12u'-\" diablo 10 pitch
30 . if (\n(.H=4u)&(1m=20u) .ds -- \(*W\h'-12u'\(*W\h'-8u'-\" diablo 12 pitch
37 . ds -- \|\(em\|
71 .\" Fear. Run. Save yourself. No user-serviceable parts.
81 . ds #H ((1u-(\\\\n(.fu%2u))*.13m)
97 . ds ' \\k:\h'-(\\n(.wu*8/10-\*(#H)'\'\h"|\\n:u"
98 . ds ` \\k:\h'-(\\n(.wu*8/10-\*(#H)'\`\h'|\\n:u'
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/freebsd/contrib/file/magic/Magdir/
H A Dmach2 #------------------------------------------------------------
8 #------------------------------------------------------------
9 # if set, it's for the 64-bit version of the architecture
10 # yes, this is separate from the low-order magic number bit
11 # it's also separate from the "64-bit libraries" bit in the
14 # Reference: https://opensource.apple.com/source/cctools/cctools-949.0.1/
15 # include/mach-o/loader.h
17 0 name mach-o-cpu
20 # 32-bit ABIs.
153 # 64-bit ABIs.
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H A Ddyadic2 #------------------------------------------------------------------------------
21 >>>1 byte 0x01 component file 32-bit non-journaled non-checksummed
27 >>>>7 byte&0x28 0x00 32-bit
28 >>>>7 byte&0x28 0x20 64-bit
31 >>>>7 byte&0x88 0x00 big-endian
32 >>>>7 byte&0x88 0x80 little-endian
36 >>>1 byte 0x08 mapped file 32-bit
37 >>>1 byte 0x09 component file 64-bit non-journaled non-checksummed
38 >>>1 byte 0x0a mapped file 64-bit
39 >>>1 byte 0x0b component file 32-bit level 1 journaled non-checksummed
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/freebsd/crypto/openssl/doc/man3/
H A DOPENSSL_ia32cap.pod5 OPENSSL_ia32cap - the x86[_64] processor capabilities vector
24 =item bit #4 denoting presence of Time-Stamp Counter.
26 =item bit #19 denoting availability of CLFLUSH instruction;
28 =item bit #20, reserved by Intel, is used to choose among RC4 code paths;
30 =item bit #23 denoting MMX support;
32 =item bit #24, FXSR bit, denoting availability of XMM registers;
34 =item bit #25 denoting SSE support;
36 =item bit #26 denoting SSE2 support;
38 =item bit #28 denoting Hyperthreading, which is used to distinguish
41 =item bit #30, reserved by Intel, denotes specifically Intel CPUs;
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/freebsd/sys/contrib/openzfs/config/
H A Dhost-cpu-c-abi.m41 # host-cpu-c-abi.m4 serial 11
2 dnl Copyright (C) 2002-2019 Free Software Foundation, Inc.
24 dnl contains 32-bit instructions, whereas 'sparc64' code contains 64-bit
25 dnl instructions. A process on a SPARC CPU can be in 32-bit mode or in 64-bit
36 dnl - 'arm': test __ARMEL__.
37 dnl - 'mips', 'mipsn32', 'mips64': test _MIPSEB vs. _MIPSEL.
38 dnl - 'powerpc64': test _BIG_ENDIAN vs. _LITTLE_ENDIAN.
41 dnl - Instructions that do not exist on all of these CPUs (cmpxchg,
45 dnl - Speed of execution of the common instruction set is reasonable across
66 # - 64-bit instruction set, 64-bit pointers, 64-bit 'long': x86_64.
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/freebsd/sys/dev/liquidio/base/
H A Dcn23xx_pf_regs.h60 /* 2 scatch registers (64-bit) */
66 /* 1 registers (64-bit) - SLI_CTL_STATUS */
70 * SLI Packet Input Jabber Register (64 bit register)
96 * 4 registers (64-bit) for mapping IOQs to MACs(PEMs)-
101 /*1 register (64-bit) to determine whether IOQs are in reset. */
104 /* Each Input Queue register is at a 16-byte Offset in BAR0 */
118 /* Starting bit of the TRS field in LIO_CN23XX_SLI_PKT_MAC_RINFO64 register */
123 /* 64 registers for Input Queue Instr Count - SLI_PKT_IN_DONE0_CNTS */
126 /* 64 registers for Input Queues Start Addr - SLI_PKT0_INSTR_BADDR */
129 /* 64 registers for Input Doorbell - SLI_PKT0_INSTR_BAOFF_DBELL */
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/freebsd/sys/contrib/edk2/Include/Library/
H A DBaseLib.h3 functions, file path functions, and CPU architecture-specific functions.
5 Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>
6 Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
10 SPDX-License-Identifier: BSD-2-Clause-Patent
18 // Definitions for architecture-specific types
22 /// The IA-32 architecture context buffer used by SetJump() and LongJump().
54 UINT8 XmmBuffer[160]; ///< XMM6-XMM15.
132 /// The RISC-V architecture context buffer used by SetJump() and LongJump().
161 Returns the length of a Null-terminated Unicode string.
165 If String is not aligned on a 16-bit boundary, then ASSERT().
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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64GenRegisterBankInfo.def1 //===- AArch64GenRegisterBankInfo.def ----------------------------*- C++ -*-==//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
16 // 0: FPR 16-bit value.
18 // 1: FPR 32-bit value.
20 // 2: FPR 64-bit value.
21 {0, 64, AArch64::FPRRegBank},
22 // 3: FPR 128-bit value.
24 // 4: FPR 256-bit value.
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/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVSchedule.td1 //===-- RISCVSchedule.td - RISC-V Scheduling Definitions ---*- tablegen -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
10 def WriteIALU : SchedWrite; // 32 or 64-bit integer ALU operations
11 def WriteIALU32 : SchedWrite; // 32-bit integer ALU operations on RV64I
12 def WriteShiftImm : SchedWrite; // 32 or 64-bit shift by immediate operations
13 def WriteShiftImm32 : SchedWrite; // 32-bit shift by immediate operations on RV64Ix
14 def WriteShiftReg : SchedWrite; // 32 or 64-bit shift by immediate operations
15 def WriteShiftReg32 : SchedWrite; // 32-bit shift by immediate operations on RV64Ix
16 def WriteIDiv : SchedWrite; // 32-bit or 64-bit divide
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/freebsd/contrib/llvm-project/compiler-rt/lib/builtins/ppc/
H A Dfloattitf.c1 //===-- lib/builtins/ppc/floattitf.c - Convert int128->long double -*-C -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file implements converting a signed 128 bit integer to a 128bit IBM /
10 // PowerPC long double (double-double) value.
12 //===----------------------------------------------------------------------===//
16 // Conversions from signed and unsigned 64-bit int to long double.
20 // Convert a signed 128-bit integer to long double.
21 // This uses the following property: Let hi and lo be 64-bits each,
23 // argument interpreted as a signed or unsigned k-bit integer. Then,
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/freebsd/sys/contrib/dev/acpica/components/tables/
H A Dtbfadt.c3 * Module Name: tbfadt - FADT table utilities
11 * Some or all of this work - Copyright (c) 1999 - 2023, Intel Corp.
28 * 2.3. Intel grants Licensee a non-exclusive and non-transferable patent
104 * re-exports any such software from a foreign destination, Licensee shall
105 * ensure that the distribution and export/re-export of the software is in
108 * any of its subsidiaries will export/re-export any technical data, process,
130 * 3. Neither the names of the above-listed copyright holders nor the names
303 * PARAMETERS: GenericAddress - GAS struct to be initialized
304 * SpaceId - ACPI Space ID for this register
305 * ByteWidth - Width of this register
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/freebsd/contrib/libcxxrt/
H A Dguard.cc2 * Copyright 2010-2012 PathScale, Inc. All rights reserved.
29 * guard.cc: Functions for thread-safe static initialisation.
37 * Statics that require initialisation are protected by a 64-bit value. Any
38 * platform that can do 32-bit atomic test and set operations can use this
39 * value as a low-overhead lock. Because statics (in most sane code) are
57 // x86 and ARM are the most common little-endian CPUs, so let's have a
66 * The Itanium C++ ABI defines guard words that are 64-bit (32-bit on AArch32)
67 * values with one bit defined to indicate that the guarded variable is and
68 * another bit to indicate that it's currently locked (initialisation in
69 * progress). The bit to use depends on the byte order of the target.
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/freebsd/contrib/llvm-project/libcxx/src/include/ryu/
H A Dd2s_intrinsics.h1 //===----------
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/freebsd/contrib/llvm-project/clang/include/clang/Basic/
H A DBuiltinsRISCV.td1 //==- BuiltinsRISCV.td - RISC-V Builtin function database ---*- tablegen -*-==//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file defines the RISC-V-specific builtin function database.
11 //===----------------------------------------------------------------------===//
22 //===----------------------------------------------------------------------===//
24 //===----------------------------------------------------------------------===//
26 def orc_b_64 : RISCVBuiltin<"uint64_t(uint64_t)", "zbb,64bit">;
28 def clz_64 : RISCVBuiltin<"unsigned int(uint64_t)", "zbb|xtheadbb,64bit">;
30 def ctz_64 : RISCVBuiltin<"unsigned int(uint64_t)", "zbb,64bit">;
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/freebsd/contrib/llvm-project/lldb/source/Plugins/ObjectFile/ELF/
H A DELFHeader.h1 //===-- ELFHeader.h ------------------------------------------- -*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
15 /// information present in both 32 and 64 bit variants of the format. Each
17 /// reading both 32 and 64 bit instances of the object.
18 //===----------------------------------------------------------------------===//
25 #include "lldb/lldb-enumerations.h"
26 #include "lldb/lldb-types.h"
39 /// 32 and 64 bit ELF variants.
81 /// Returns true if this is a 32 bit ELF file header.
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