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5 OPENSSL_ia32cap - the x86[_64] processor capabilities vector
24 =item bit #4 denoting presence of Time-Stamp Counter.
26 =item bit #19 denoting availability of CLFLUSH instruction;
28 =item bit #20, reserved by Intel, is used to choose among RC4 code paths;
30 =item bit #23 denoting MMX support;
32 =item bit #24, FXSR bit, denoting availability of XMM registers;
34 =item bit #25 denoting SSE support;
36 =item bit #26 denoting SSE2 support;
38 =item bit #28 denoting Hyperthreading, which is used to distinguish
41 =item bit #30, reserved by Intel, denotes specifically Intel CPUs;
43 =item bit #33 denoting availability of PCLMULQDQ instruction;
45 =item bit #41 denoting SSSE3, Supplemental SSE3, support;
47 =item bit #43 denoting AMD XOP support (forced to zero on non-AMD CPUs);
49 =item bit #54 denoting availability of MOVBE instruction;
51 =item bit #57 denoting AES-NI instruction set extension;
53 =item bit #58, XSAVE bit, lack of which in combination with MOVBE is used
56 =item bit #59, OSXSAVE bit, denoting availability of YMM registers;
58 =item bit #60 denoting AVX extension;
60 =item bit #62 denoting availability of RDRAND instruction;
64 For example, in 32-bit application context clearing bit #26 at run-time
65 disables high-performance SSE2 code present in the crypto library, while
66 clearing bit #24 disables SSE2 code operating on 128-bit XMM register
76 effect. Alternatively you can reconfigure the toolkit with no-sse2
79 Less intuitive is clearing bit #28, or ~0x10000000 in the "environment
83 on whether or not expensive countermeasures against cache-timing attacks
91 =item bit #64+3 denoting availability of BMI1 instructions, e.g. ANDN;
93 =item bit #64+5 denoting availability of AVX2 instructions;
95 =item bit #64+8 denoting availability of BMI2 instructions, e.g. MULX
98 =item bit #64+16 denoting availability of AVX512F extension;
100 =item bit #64+17 denoting availability of AVX512DQ extension;
102 =item bit #64+18 denoting availability of RDSEED instruction;
104 =item bit #64+19 denoting availability of ADCX and ADOX instructions;
106 =item bit #64+21 denoting availability of VPMADD52[LH]UQ instructions,
109 =item bit #64+29 denoting availability of SHA extension;
111 =item bit #64+30 denoting availability of AVX512BW extension;
113 =item bit #64+31 denoting availability of AVX512VL extension;
115 =item bit #64+41 denoting availability of VAES extension;
117 =item bit #64+42 denoting availability of VPCLMULQDQ extension;
123 C<:~0x20> would disable AVX2 code paths, and C<:0> - all post-AVX
132 Copyright 2004-2021 The OpenSSL Project Authors. All Rights Reserved.