Lines Matching +full:64 +full:- +full:bit
1 //===- AArch64GenRegisterBankInfo.def ----------------------------*- C++ -*-==//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
16 // 0: FPR 16-bit value.
18 // 1: FPR 32-bit value.
20 // 2: FPR 64-bit value.
21 {0, 64, AArch64::FPRRegBank},
22 // 3: FPR 128-bit value.
24 // 4: FPR 256-bit value.
26 // 5: FPR 512-bit value.
28 // 6: GPR 32-bit value.
30 // 7: GPR 64-bit value.
31 {0, 64, AArch64::GPRRegBank},
32 // 8: GPR 128-bit value.
41 // 3-operands instructions (all binary operations should end up with one of
43 // 1: FPR 16-bit value. <-- This must match First3OpsIdx.
44 {&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR16 - PMI_Min], 1},
45 {&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR16 - PMI_Min], 1},
46 {&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR16 - PMI_Min], 1},
47 // 4: FPR 32-bit value. <-- This must match First3OpsIdx.
48 {&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR32 - PMI_Min], 1},
49 {&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR32 - PMI_Min], 1},
50 {&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR32 - PMI_Min], 1},
51 // 7: FPR 64-bit value.
52 {&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR64 - PMI_Min], 1},
53 {&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR64 - PMI_Min], 1},
54 {&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR64 - PMI_Min], 1},
55 // 10: FPR 128-bit value.
56 {&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR128 - PMI_Min], 1},
57 {&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR128 - PMI_Min], 1},
58 {&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR128 - PMI_Min], 1},
59 // 13: FPR 256-bit value.
60 {&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR256 - PMI_Min], 1},
61 {&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR256 - PMI_Min], 1},
62 {&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR256 - PMI_Min], 1},
63 // 16: FPR 512-bit value.
64 {&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR512 - PMI_Min], 1},
65 {&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR512 - PMI_Min], 1},
66 {&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR512 - PMI_Min], 1},
67 // 19: GPR 32-bit value.
68 {&AArch64GenRegisterBankInfo::PartMappings[PMI_GPR32 - PMI_Min], 1},
69 {&AArch64GenRegisterBankInfo::PartMappings[PMI_GPR32 - PMI_Min], 1},
70 {&AArch64GenRegisterBankInfo::PartMappings[PMI_GPR32 - PMI_Min], 1},
71 // 22: GPR 64-bit value.
72 {&AArch64GenRegisterBankInfo::PartMappings[PMI_GPR64 - PMI_Min], 1},
73 {&AArch64GenRegisterBankInfo::PartMappings[PMI_GPR64 - PMI_Min], 1},
74 {&AArch64GenRegisterBankInfo::PartMappings[PMI_GPR64 - PMI_Min], 1},
75 // 25: GPR 128-bit value. <-- This must match Last3OpsIdx.
76 {&AArch64GenRegisterBankInfo::PartMappings[PMI_GPR128 - PMI_Min], 1},
77 {&AArch64GenRegisterBankInfo::PartMappings[PMI_GPR128 - PMI_Min], 1},
78 {&AArch64GenRegisterBankInfo::PartMappings[PMI_GPR128 - PMI_Min], 1},
80 // 28: FPR 16-bit value to GPR 16-bit. <-- This must match
83 {&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR16 - PMI_Min], 1},
84 {&AArch64GenRegisterBankInfo::PartMappings[PMI_GPR32 - PMI_Min], 1},
85 // 30: FPR 32-bit value to GPR 32-bit value.
86 {&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR32 - PMI_Min], 1},
87 {&AArch64GenRegisterBankInfo::PartMappings[PMI_GPR32 - PMI_Min], 1},
88 // 32: FPR 64-bit value to GPR 64-bit value.
89 {&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR64 - PMI_Min], 1},
90 {&AArch64GenRegisterBankInfo::PartMappings[PMI_GPR64 - PMI_Min], 1},
91 // 34: FPR 128-bit value to GPR 128-bit value (invalid)
94 // 36: FPR 256-bit value to GPR 256-bit value (invalid)
97 // 38: FPR 512-bit value to GPR 512-bit value (invalid)
100 // 40: GPR 32-bit value to FPR 32-bit value.
101 {&AArch64GenRegisterBankInfo::PartMappings[PMI_GPR32 - PMI_Min], 1},
102 {&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR32 - PMI_Min], 1},
103 // 42: GPR 64-bit value to FPR 64-bit value. <-- This must match
105 {&AArch64GenRegisterBankInfo::PartMappings[PMI_GPR64 - PMI_Min], 1},
106 {&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR64 - PMI_Min], 1},
107 // 44: FPExt: 16 to 32. <-- This must match FPExt16To32Idx.
108 {&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR32 - PMI_Min], 1},
109 {&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR16 - PMI_Min], 1},
110 // 46: FPExt: 16 to 32. <-- This must match FPExt16To64Idx.
111 {&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR64 - PMI_Min], 1},
112 {&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR16 - PMI_Min], 1},
113 // 48: FPExt: 32 to 64. <-- This must match FPExt32To64Idx.
114 {&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR64 - PMI_Min], 1},
115 {&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR32 - PMI_Min], 1},
116 // 50: FPExt vector: 64 to 128. <-- This must match FPExt64To128Idx.
117 {&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR128 - PMI_Min], 1},
118 {&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR64 - PMI_Min], 1},
119 // 52: Shift scalar with 64 bit shift imm
120 {&AArch64GenRegisterBankInfo::PartMappings[PMI_GPR32 - PMI_Min], 1},
121 {&AArch64GenRegisterBankInfo::PartMappings[PMI_GPR32 - PMI_Min], 1},
122 {&AArch64GenRegisterBankInfo::PartMappings[PMI_GPR64 - PMI_Min], 1},
129 const PartialMapping &Map = PartMappings[Idx - PartialMappingIdx::PMI_Min];
138 unsigned PartialMapBaseIdx = Idx - PartialMappingIdx::PMI_Min;
176 if (Size <= 64)
180 return -1;
190 if (MinSize <= 64)
198 return -1;
200 return -1;
208 if (BaseIdxOffset == -1u)
212 First3OpsIdx + (RBIdx - PartialMappingIdx::PMI_Min + BaseIdxOffset) *
241 assert(Size <= 64 && "GPR cannot handle that size");
244 (DstRBIdx - PMI_Min + getRegBankBaseIdxOffset(DstRBIdx, Size)) *
255 // - For Scalar:
256 // - 16 to 32.
257 // - 16 to 64.
258 // - 32 to 64.
259 // => FPR 16 to FPR 32|64
260 // => FPR 32 to FPR 64
261 // - For vectors:
262 // - v4f16 to v4f32
263 // - v2f32 to v2f64
264 // => FPR 64 to FPR 128
268 assert((DstSize == 32 || DstSize == 64) && "Unexpected half extension");
275 assert(DstSize == 64 && "Unexpected float extension");
278 assert((SrcSize == 64 || DstSize == 128) && "Unexpected vector extension");