Lines Matching +full:64 +full:- +full:bit
60 /* 2 scatch registers (64-bit) */
66 /* 1 registers (64-bit) - SLI_CTL_STATUS */
70 * SLI Packet Input Jabber Register (64 bit register)
96 * 4 registers (64-bit) for mapping IOQs to MACs(PEMs)-
101 /*1 register (64-bit) to determine whether IOQs are in reset. */
104 /* Each Input Queue register is at a 16-byte Offset in BAR0 */
118 /* Starting bit of the TRS field in LIO_CN23XX_SLI_PKT_MAC_RINFO64 register */
123 /* 64 registers for Input Queue Instr Count - SLI_PKT_IN_DONE0_CNTS */
126 /* 64 registers for Input Queues Start Addr - SLI_PKT0_INSTR_BADDR */
129 /* 64 registers for Input Doorbell - SLI_PKT0_INSTR_BAOFF_DBELL */
132 /* 64 registers for Input Queue size - SLI_PKT0_INSTR_FIFO_RSIZE */
136 * 64 registers (64-bit) - ES, RO, NS, Arbitration for Input Queue Data &
141 /*------- Request Queue Macros ---------*/
162 /*------------------ Masks ----------------*/
164 #define LIO_CN23XX_PKT_INPUT_CTL_MAC_NUM BIT(29)
170 #define LIO_CN23XX_PKT_INPUT_CTL_IS_64B BIT(24)
171 #define LIO_CN23XX_PKT_INPUT_CTL_RST BIT(23)
172 #define LIO_CN23XX_PKT_INPUT_CTL_QUIET BIT(28)
173 #define LIO_CN23XX_PKT_INPUT_CTL_RING_ENB BIT(22)
174 #define LIO_CN23XX_PKT_INPUT_CTL_DATA_ES_64B_SWAP BIT(6)
175 #define LIO_CN23XX_PKT_INPUT_CTL_USE_CSR BIT(4)
200 /* 64 registers for Output queue control - SLI_PKT(0..63)_OUTPUT_CONTROL */
203 /* 64 registers for Output queue buffer and info size - SLI_PKT0_OUT_SIZE */
206 /* 64 registers for Output Queue Start Addr - SLI_PKT0_SLIST_BADDR */
209 /* 64 registers for Output Queue Packet Credits - SLI_PKT0_SLIST_BAOFF_DBELL */
212 /* 64 registers for Output Queue size - SLI_PKT0_SLIST_FIFO_RSIZE */
215 /* 64 registers for Output Queue Packet Count - SLI_PKT0_CNTS */
218 /* 64 registers for Output Queue INT Levels - SLI_PKT0_INT_LEVELS */
221 /* Each Output Queue register is at a 16-byte Offset in BAR0 */
224 /* 1 (64-bit register) for Output Queue backpressure across all rings. */
236 /*------- Output Queue Macros ---------*/
266 /*------------------ Masks ----------------*/
267 #define LIO_CN23XX_PKT_OUTPUT_CTL_TENB BIT(13)
268 #define LIO_CN23XX_PKT_OUTPUT_CTL_CENB BIT(12)
269 #define LIO_CN23XX_PKT_OUTPUT_CTL_IPTR BIT(11)
270 #define LIO_CN23XX_PKT_OUTPUT_CTL_ES BIT(9)
271 #define LIO_CN23XX_PKT_OUTPUT_CTL_NSR BIT(8)
272 #define LIO_CN23XX_PKT_OUTPUT_CTL_ROR BIT(7)
273 #define LIO_CN23XX_PKT_OUTPUT_CTL_DPTR BIT(6)
274 #define LIO_CN23XX_PKT_OUTPUT_CTL_BMODE BIT(5)
275 #define LIO_CN23XX_PKT_OUTPUT_CTL_ES_P BIT(3)
276 #define LIO_CN23XX_PKT_OUTPUT_CTL_NSR_P BIT(2)
277 #define LIO_CN23XX_PKT_OUTPUT_CTL_ROR_P BIT(1)
278 #define LIO_CN23XX_PKT_OUTPUT_CTL_RING_ENB BIT(0)
298 /* 1 register (64-bit) for Interrupt Summary */
301 /* 4 registers (64-bit) for Interrupt Enable for each Port */
314 /* 1 register (64-bit) to indicate which Output Queue reached pkt threshold */
317 /* 1 register (64-bit) to indicate which Output Queue reached time threshold */
320 /*------------------ Interrupt Masks ----------------*/
328 #define LIO_CN23XX_INTR_MIO_INT BIT(1)
329 #define LIO_CN23XX_INTR_PKT_TIME BIT(5)
330 #define LIO_CN23XX_INTR_M0UPB0_ERR BIT(8)
331 #define LIO_CN23XX_INTR_M0UPWI_ERR BIT(9)
332 #define LIO_CN23XX_INTR_M0UNB0_ERR BIT(10)
333 #define LIO_CN23XX_INTR_M0UNWI_ERR BIT(11)
373 /* 4 Registers (64 - bit) */
396 /* 4 Registers (64-bit) */