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/linux/arch/arm/include/asm/hardware/
H A Dcp14.h45 #define RCP14_DBGDIDR() MRC14(0, c0, c0, 0)
46 #define RCP14_DBGDSCRint() MRC14(0, c0, c1, 0)
47 #define RCP14_DBGDTRRXint() MRC14(0, c0, c5, 0)
48 #define RCP14_DBGWFAR() MRC14(0, c0, c6, 0)
49 #define RCP14_DBGVCR() MRC14(0, c0, c7, 0)
50 #define RCP14_DBGECR() MRC14(0, c0, c9, 0)
51 #define RCP14_DBGDSCCR() MRC14(0, c0, c10, 0)
52 #define RCP14_DBGDSMCR() MRC14(0, c0, c11, 0)
53 #define RCP14_DBGDTRRXext() MRC14(0, c0, c0, 2)
54 #define RCP14_DBGDSCRext() MRC14(0, c0, c2, 2)
[all …]
/linux/drivers/gpu/drm/nouveau/nvkm/engine/sec/fuc/
H A Dg98.fuc0s7 * the Free Software Foundation; either version 2 of the License, or
194 mov $r5 2
240 shl b32 $r5 $r4 2
259 ld b16 $r6 D[$r4 + 2]
260 cmpu b32 $r6 2
342 or $r2 2
349 // if < 2, no QUERY object is involved
350 cmpu b32 $r3 2
374 // if == 2, only a single QUERY is involved...
375 cmpu b32 $r3 2
[all …]
/linux/tools/testing/selftests/hid/tests/
H A Dtest_multitouch.py30 "CYPRESS": BIT(2),
109 input_info=(BusType.USB, 1, 2), argument
222 elif value == 2:
346 Report ID (2)
396 {rdesc_finger_str * 2}
408 Report ID (2)
478 Report ID (2)
492 …c0 c0 05 0d 09 06 15 00 26 ff 00 a1 01 85 02 75 08 95 3f 09 00 82 02 01 95 3f 09 00 92 02 01 c0 05…
552 if uhdev.max_contacts > 2:
553 assert evdev.slots[2][libevdev.EV_ABS.ABS_MT_TRACKING_ID] == -1
[all …]
H A Dtest_tablet.py84 raise ValueError("2 tools are not allowed")
525 input_info=(BusType.USB, 1, 2), argument
1302 …c0 c0 05 01 09 01 a1 01 85 01 09 01 a1 00 05 09 19 01 29 02 15 00 25 01 95 02 75 01 81 02 95 01 75…
1310 …c0 c0 05 01 09 01 a1 01 85 01 09 01 a1 00 05 09 19 01 29 02 15 00 25 01 95 02 75 01 81 02 95 01 75…
1318 …c0 c0 05 01 09 01 a1 01 85 01 09 01 a1 00 05 09 19 01 29 02 15 00 25 01 95 02 75 01 81 02 95 01 75…
1326 …c0 c0 05 01 09 01 a1 01 85 01 09 01 a1 00 05 09 19 01 29 02 15 00 25 01 95 02 75 01 81 02 95 01 75…
1334 …c0 c0 05 01 09 01 a1 01 85 01 09 01 a1 00 05 09 19 01 29 02 15 00 25 01 95 02 75 01 81 02 95 01 75…
1342 …2c 26 ff 7f 81 02 05 0d 09 55 25 08 75 08 95 01 b1 02 c0 c0 05 01 09 01 a1 01 85 01 09 01 a1 00 05…
1350 …c0 c0 05 0d 09 04 a1 01 85 30 09 22 a1 02 09 42 15 00 25 01 75 01 95 01 81 02 09 32 81 02 09 47 81…
1358 …c0 a1 02 05 0d 09 42 15 00 25 01 75 01 95 01 81 02 09 32 81 02 95 06 81 03 75 08 09 51 95 01 81 02…
[all …]
/linux/arch/arm/mm/
H A Dproc-v7.S25 #include "proc-v7-2level.S"
35 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
38 mcr p15, 0, r0, c1, c0, 0 @ disable caches
58 mrc p15, 0, r2, c1, c0, 0 @ ctrl register
61 mcr p15, 0, r2, c1, c0, 0 @ disable MMU
89 2: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
92 bhi 2b
138 mrc p15, 0, r4, c13, c0, 0 @ FCSE/PID
139 mrc p15, 0, r5, c13, c0, 3 @ User r/o thread ID
142 mrc p15, 0, r6, c3, c0,
[all...]
H A Dproc-v6.S25 #define TTB_IMP (1 << 2)
28 #define TTB_RGN_WT (2 << 3)
43 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
46 mcr p15, 0, r0, c1, c0, 0 @ disable caches
62 mrc p15, 0, r1, c1, c0, 0 @ ctrl register
64 mcr p15, 0, r1, c1, c0, 0 @ disable MMU
81 mcr p15, 0, r1, c7, c0, 4 @ wait for interrupt
111 mcr p15, 0, r0, c2, c0, 0 @ set TTB 0
113 mrc p15, 0, r2, c13, c0, 1 @ read current context ID
118 mcr p15, 0, r1, c13, c0, 1 @ set context ID
[all …]
H A Dproc-arm740.S48 mrc p15, 0, r0, c1, c0, 0
51 mcr p15, 0, r0, c1, c0, 0 @ disable caches
63 mcr p15, 0, ip, c7, c0, 0 @ invalidate cache
64 mrc p15, 0, ip, c1, c0, 0 @ get ctrl register
66 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
74 mcr p15, 0, r0, c7, c0, 0 @ invalidate caches
83 mcr p15, 0, r0, c6, c0 @ set area 0, default
88 1: add r4, r4, #1 @ area size *= 2
99 beq 2f
101 1: add r4, r4, #1 @ area size *= 2
[all …]
H A Dproc-sa1100.S42 mcr p15, 0, r0, c15, c1, 2 @ Enable clock switching
43 mcr p15, 0, r0, c9, c0, 5 @ Allow read-buffer operations from userland
55 mcr p15, 0, ip, c15, c2, 2 @ Disable clock switching
56 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
59 mcr p15, 0, r0, c1, c0, 0 @ disable caches
81 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
84 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
97 * 2 = switch to slow processor clock
111 mcr p15, 0, r0, c15, c2, 2 @ disable clock switching
113 mcr p15, 0, r0, c15, c8, 2 @ wait for interrupt
[all …]
H A Dcache-v7.S25 .align 2
44 mcr p15, 2, r0, c0, c0, 0 @ select L1 data cache in CSSELR
46 mrc p15, 1, r0, c0, c0, 0 @ read cache geometry from CCSIDR
62 2: mov ip, r0, lsl r2 @ NumSet << SetShift
64 mcr p15, 0, ip, c7, c6, 2
66 bpl 2b
69 mrc p15, 1, r0, c0, c0, 0 @ re-read cache geometry from CCSIDR
101 mrc p15, 1, r0, c0, c0, 1 @ read clidr, r0 = clidr
104 ands r3, r3, #7 << 1 @ extract LoU*2 field from clidr
107 ALT_SMP(mrc p15, 0, r2, c0, c0, 0) @ read main ID register
[all …]
H A Dproc-arm940.S41 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
44 mcr p15, 0, r0, c1, c0, 0 @ disable caches
59 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
62 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
72 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
119 2: mcr p15, 0, r3, c7, c14, 2 @ clean/flush D index
121 bcs 2b @ entries 63 to 0
174 2: mcr p15, 0, r3, c7, c14, 2 @ clean/flush D index
176 bcs 2b @ entries 63 to 0
197 2: mcr p15, 0, r3, c7, c6, 2 @ flush D entry
[all …]
/linux/tools/testing/selftests/cgroup/
H A Dtest_cpuset_prs.sh50 DELAY_FACTOR=2
52 -d) DELAY_FACTOR=$2
105 rmdir A1/A2/A3 A1/A2 A1 B1 > /dev/null 2>&1
106 rmdir test > /dev/null 2>&1
179 # P<v> = set cpus.partition (0:member, 1:root, 2:isolated)
190 # Note that if there are 2 fields in ISOLCPUS, the first one is for
198 " C0-1 . . C2-3 S+ C4-5 . . 0 A2:0-1"
199 " C0-1 . . C2-3 P1 . . . 0 "
200 " C0-1 . . C2-3 P1:S+ C0-1:P1 . . 0 "
201 " C0-1 . . C2-3 P1:S+ C1:P1 . . 0 "
[all …]
/linux/drivers/gpu/drm/tidss/
H A Dtidss_scale_coefs.c17 .c2 = { 28, 34, 40, 46, 52, 58, 64, 70, 0, 2, 4, 8, 12, 16, 20, 24, },
19 .c0 = { 192, 192, 192, 190, 188, 186, 184, 182, 180, },
23 .c2 = { 24, 28, 32, 38, 44, 50, 56, 64, 0, 2, 4, 6, 8, 12, 16, 20, },
25 .c0 = { 200, 202, 204, 202, 200, 196, 192, 188, 184, },
29 .c2 = { 16, 20, 24, 30, 36, 42, 48, 56, 0, 0, 0, 2, 4, 8, 12, 14, },
31 .c0 = { 216, 216, 216, 214, 212, 208, 204, 198, 192, },
35 .c2 = { 12, 14, 16, 22, 28, 34, 40, 48, 0, 0, 0, 2, 4, 4, 4, 8, },
37 .c0 = { 232, 232, 232, 226, 220, 218, 216, 208, 200, },
41 .c2 = { 0, 2, 4, 8, 12, 18, 24, 32, 0, 0, 0, -2, -4, -4, -4, -2, },
43 .c0 = { 264, 262, 260, 254, 248, 242, 236, 226, 216, },
[all …]
/linux/arch/arm/kernel/
H A Dhyp-stub.S23 .align 2
29 * Save the primary CPU boot mode. Requires 2 scratch registers.
41 * Requires 2 additional scratch registers.
116 mcr p15, 4, r7, c12, c0, 0 @ set hypervisor vector base (HVBAR)
121 mcr p15, 4, r7, c1, c1, 2 @ HCPTR
126 mcr p15, 4, r7, c1, c0, 0 @ HSCTLR
133 mrc p15, 0, r7, c1, c0, 0 @ SCTLR
137 mcr p15, 0, r7, c1, c0, 0 @ SCTLR
139 mrc p15, 0, r7, c0, c0, 0 @ MIDR
140 mcr p15, 4, r7, c0, c0, 0 @ VPIDR
[all …]
/linux/arch/arm/include/debug/
H A Dicedcc.S16 mcr p14, 0, \rd, c0, c5, 0
21 mrc p14, 0, \rx, c0, c1, 0
34 mrc p14, 0, \rx, c0, c1, 0
43 mcr p14, 0, \rd, c8, c0, 0
48 mrc p14, 0, \rx, c14, c0, 0
61 mrc p14, 0, \rx, c14, c0, 0
70 mcr p14, 0, \rd, c1, c0, 0
75 mrc p14, 0, \rx, c0, c0, 0
76 tst \rx, #2
89 mrc p14, 0, \rx, c0, c0, 0
[all …]
/linux/arch/arm/include/asm/
H A Duaccess-asm.h50 mcr p15, 0, \tmp, c3, c0, 0 @ Set domain register
62 mcr p15, 0, \tmp, c3, c0, 0
76 mrc p15, 0, \tmp, c2, c0, 2 @ read TTBCR
79 mcr p15, 0, \tmp, c2, c0, 2 @ write TTBCR
90 mrc p15, 0, \tmp, c2, c0, 2 @ read TTBCR
93 mcr p15, 0, \tmp, c2, c0, 2 @ write TTBCR
132 DACR( mrc p15, 0, \tmp0, c3, c0, 0)
134 PAN( mrc p15, 0, \tmp0, c2, c0, 2)
139 mcr p15, 0, \tmp2, c3, c0, 0
145 mcr p15, 0, \tmp2, c3, c0, 0
[all …]
/linux/arch/s390/crypto/
H A Dchacha-s390.S22 .long 2,0,0,0
26 .long 0,1,2,3
101 VREPF XB2,K1,2
106 VREPF XD2,K3,2
112 VREPF XC2,K2,2
442 #define C0 %v2 macro
509 VAF D2,K3,T2 # K[3]+2
514 VLR C0,K2
545 VAF C0,C0,D0
551 VX B0,B0,C0
[all …]
/linux/tools/testing/selftests/net/forwarding/
H A Dbridge_igmp.sh17 MZPKT_IS_INC="22:00:9d:de:00:00:00:01:01:00:00:03:ef:0a:0a:0a:c0:00:02:01:c0:00:02:02:c0:00:02:03"
19 MZPKT_IS_INC2="22:00:9d:c3:00:00:00:01:01:00:00:03:ef:0a:0a:0a:c0:00:02:0a:c0:00:02:0b:c0:00:02:0c"
21 MZPKT_IS_INC3="22:00:5f:b4:00:00:00:01:01:00:00:02:ef:0a:0a:0a:c0:00:02:14:c0:00:02:1e"
23 MZPKT_ALLOW="22:00:99:c3:00:00:00:01:05:00:00:03:ef:0a:0a:0a:c0:00:02:0a:c0:00:02:0b:c0:00:02:0c"
25 MZPKT_ALLOW2="22:00:5b:b4:00:00:00:01:05:00:00:02:ef:0a:0a:0a:c0:00:02:14:c0:00:02:1e"
27 …_IS_EXC="22:00:da:b6:00:00:00:01:02:00:00:04:ef:0a:0a:0a:c0:00:02:01:c0:00:02:02:c0:00:02:14:c0:00…
29 MZPKT_IS_EXC2="22:00:5e:b4:00:00:00:01:02:00:00:02:ef:0a:0a:0a:c0:00:02:14:c0:00:02:1e"
31 MZPKT_TO_EXC="22:00:9a:b1:00:00:00:01:04:00:00:03:ef:0a:0a:0a:c0:00:02:01:c0:00:02:14:c0:00:02:1e"
33 MZPKT_BLOCK="22:00:98:b1:00:00:00:01:06:00:00:03:ef:0a:0a:0a:c0:00:02:01:c0:00:02:14:c0:00:02:1e"
49 simple_if_init $h2 192.0.2.2/24 2001:db8:1::2/64
[all …]
/linux/arch/arm/boot/compressed/
H A Dhead.S38 mcr p14, 0, \ch, c0, c5, 0
44 mcr p14, 0, \ch, c8, c0, 0
50 mcr p14, 0, \ch, c1, c0, 0
141 mrc p15, 0, \reg, c1, c0, 0 @ read SCTLR
145 mcr p15, 0, \reg, c1, c0, 0 @ write SCTLR
164 ldrb \tmp2, [\tmp1, #2]
658 .align 2
696 mrc p15, 0, \tmp, c0, c0, 1 @ read ctr
735 mcr p15, 0, r0, c2, c0, 0 @ D-cache on
736 mcr p15, 0, r0, c2, c0, 1 @ I-cache on
[all …]
/linux/arch/arm/mach-sunxi/
H A Dheadsmp.S25 mrc p15, 0, r1, c0, c0, 0
37 mrc p15, 1, r1, c15, c0, 4
39 mcr p15, 1, r1, c15, c0, 4
42 mrc p15, 1, r1, c15, c0, 0
47 mcr p15, 1, r1, c15, c0, 0
50 mrc p15, 1, r1, c9, c0, 2
53 mcr p15, 1, r1, c9, c0, 2
68 .align 2
/linux/Documentation/admin-guide/hw-vuln/
H A Dcross-thread-rsb.rst9 transitions out of C0 state, the other sibling thread could use return target
10 predictions from the sibling thread that transitioned out of C0.
15 transitioning out of C0. This could result in a guest-controlled return target
38 Affected SMT-capable processors support 1T and 2T modes of execution when SMT
39 is enabled. In 2T mode, both threads in a core are executing code. For the
41 requests to transition out of the C0 state. This can be communicated with the
42 HLT instruction or with an MWAIT instruction that requests non-C0.
43 When the thread re-enters the C0 state, the processor transitions back
44 to 2T mode, assuming the other thread is also still in C0 state.
47 depending on the SMT mode. For instance, in 2T mode each thread uses a private
[all …]
/linux/arch/arm/mach-omap2/
H A Dsleep44xx.S48 * 2 - CPUx L1 and logic lost + GIC lost: MPUSS OSWR
88 mrc p15, 0, r0, c1, c0, 0
89 bic r0, r0, #(1 << 2) @ Disable the C bit
90 mcr p15, 0, r0, c1, c0, 0
108 mrc p15, 0, r0, c0, c0, 5 @ Read MPIDR
119 mrc p15, 0, r0, c0, c0, 5 @ Read MPIDR
126 mrc p15, 0, r0, c1, c1, 2 @ Read NSACR data
128 mrcne p15, 0, r0, c1, c0, 1
130 mcrne p15, 0, r0, c1, c0, 1
146 mrc p15, 0, r5, c0, c0, 5 @ Read MPIDR
[all …]
/linux/arch/arm/mach-tegra/
H A Dsleep.S40 mrc p15, 0, r2, c1, c0, 0
43 mcrne p15, 0, r2, c1, c0, 0
65 mrc p15, 0, r0, c0, c0, 5
70 mrc p15, 0x1, r0, c9, c0, 2
72 cmp r0, #2
74 orrne r0, r0, #2
75 mcrne p15, 0x1, r0, c9, c0, 2
116 mrc p15, 0, r3, c1, c0, 0
120 mcr p15, 0, r3, c1, c0, 0
145 mov r0, #(2 << 28) @ burst policy = run mode
H A Dsleep.h32 #define CPU_RESETTABLE 2
70 mrc p15, 0, \rd, c0, c0, 5
82 mrc p15, 0, \tmp1, c0, c0, 0
90 mrc p15, 0, \tmp1, c1, c0, 1 @ ACTLR
92 mcr p15, 0, \tmp1, c1, c0, 1 @ ACTLR
96 mrceq p15, 0, \tmp1, c0, c0, 5
98 moveq \tmp1, \tmp1, lsl #2
/linux/arch/arm/mach-versatile/
H A Dhotplug.c30 " mrc p15, 0, %0, c1, c0, 1\n" in versatile_immitation_enter_lowpower()
32 " mcr p15, 0, %0, c1, c0, 1\n" in versatile_immitation_enter_lowpower()
33 " mrc p15, 0, %0, c1, c0, 0\n" in versatile_immitation_enter_lowpower()
34 " bic %0, %0, %2\n" in versatile_immitation_enter_lowpower()
35 " mcr p15, 0, %0, c1, c0, 0\n" in versatile_immitation_enter_lowpower()
46 "mrc p15, 0, %0, c1, c0, 0\n" in versatile_immitation_leave_lowpower()
48 " mcr p15, 0, %0, c1, c0, 0\n" in versatile_immitation_leave_lowpower()
49 " mrc p15, 0, %0, c1, c0, 1\n" in versatile_immitation_leave_lowpower()
50 " orr %0, %0, %2\n" in versatile_immitation_leave_lowpower()
51 " mcr p15, 0, %0, c1, c0, 1\n" in versatile_immitation_leave_lowpower()
/linux/Documentation/admin-guide/media/
H A Ddvb-usb-gp8psk-cardlist.rst16 - 09c0:0200, 09c0:0201
17 * - Genpix 8PSK-to-USB2 Rev.2 DVB-S receiver
18 - 09c0:0202
20 - 09c0:0203
21 * - Genpix SkyWalker-2 DVB-S receiver
22 - 09c0:0206

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