Lines Matching +full:2 +full:c0
48 mrc p15, 0, r0, c1, c0, 0
51 mcr p15, 0, r0, c1, c0, 0 @ disable caches
63 mcr p15, 0, ip, c7, c0, 0 @ invalidate cache
64 mrc p15, 0, ip, c1, c0, 0 @ get ctrl register
66 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
74 mcr p15, 0, r0, c7, c0, 0 @ invalidate caches
83 mcr p15, 0, r0, c6, c0 @ set area 0, default
88 1: add r4, r4, #1 @ area size *= 2
99 beq 2f
101 1: add r4, r4, #1 @ area size *= 2
106 2: mcr p15, 0, r0, c6, c2 @ set area 2, ROM/FLASH
109 mcr p15, 0, r0, c2, c0 @ Region 1&2 cacheable
115 mcr p15, 0, r0, c3, c0
119 mcr p15, 0, r0, c5, c0 @ all read/write access
121 mrc p15, 0, r0, c1, c0 @ get control register