Lines Matching +full:2 +full:c0
23 .align 2
29 * Save the primary CPU boot mode. Requires 2 scratch registers.
41 * Requires 2 additional scratch registers.
116 mcr p15, 4, r7, c12, c0, 0 @ set hypervisor vector base (HVBAR)
121 mcr p15, 4, r7, c1, c1, 2 @ HCPTR
126 mcr p15, 4, r7, c1, c0, 0 @ HSCTLR
133 mrc p15, 0, r7, c1, c0, 0 @ SCTLR
137 mcr p15, 0, r7, c1, c0, 0 @ SCTLR
139 mrc p15, 0, r7, c0, c0, 0 @ MIDR
140 mcr p15, 4, r7, c0, c0, 0 @ VPIDR
142 mrc p15, 0, r7, c0, c0, 5 @ MPIDR
143 mcr p15, 4, r7, c0, c0, 5 @ VMPIDR
147 mrc p15, 0, r7, c0, c1, 1 @ ID_PFR1
166 mrc p15, 0, r7, c0, c1, 1 @ ID_PFR1
169 beq 2f
181 beq 2f
184 2:
195 mcr p15, 4, r1, c12, c0, 0 @ set HVBAR
200 bne 2f
203 2: ldr r0, =HVC_STUB_ERR