Lines Matching +full:2 +full:c0
25 #include "proc-v7-2level.S"
35 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
38 mcr p15, 0, r0, c1, c0, 0 @ disable caches
58 mrc p15, 0, r2, c1, c0, 0 @ ctrl register
61 mcr p15, 0, r2, c1, c0, 0 @ disable MMU
89 2: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
92 bhi 2b
138 mrc p15, 0, r4, c13, c0, 0 @ FCSE/PID
139 mrc p15, 0, r5, c13, c0, 3 @ User r/o thread ID
142 mrc p15, 0, r6, c3, c0, 0 @ Domain ID
146 mrc p15, 0, r7, c2, c0, 1 @ TTB 1
148 mrc p15, 0, r11, c2, c0, 2 @ TTB control register
150 mrc p15, 0, r8, c1, c0, 0 @ Control register
151 mrc p15, 0, r9, c1, c0, 1 @ Auxiliary control register
152 mrc p15, 0, r10, c1, c0, 2 @ Co-processor access control
160 mcr p15, 0, ip, c13, c0, 1 @ set reserved context ID
162 mcr p15, 0, r4, c13, c0, 0 @ FCSE/PID
163 mcr p15, 0, r5, c13, c0, 3 @ User r/o thread ID
167 mcr p15, 0, r6, c3, c0, 0 @ Domain ID
174 mcr p15, 0, r1, c2, c0, 0 @ TTB 0
175 mcr p15, 0, r7, c2, c0, 1 @ TTB 1
177 mcr p15, 0, r11, c2, c0, 2 @ TTB control register
183 mrc p15, 0, r4, c1, c0, 1 @ Read Auxiliary control register
185 mcrne p15, 0, r9, c1, c0, 1 @ No, so write it
186 mcr p15, 0, r10, c1, c0, 2 @ Co-processor access control
195 .equ cpu_ca9mp_suspend_size, cpu_v7_suspend_size + 4 * 2
199 mrc p15, 0, r4, c15, c0, 1 @ Diagnostic register
200 mrc p15, 0, r5, c15, c0, 0 @ Power register
208 mrc p15, 0, r10, c15, c0, 1 @ Read Diagnostic register
210 mcrne p15, 0, r4, c15, c0, 1 @ No, so restore it
211 mrc p15, 0, r10, c15, c0, 0 @ Read Power register
213 mcrne p15, 0, r5, c15, c0, 0 @ No, so restore it
240 mrc p15, 1, r8, c15, c1, 2 @ save CP15 - Aux Debug Modes Ctrl 2
252 mcr p15, 1, r8, c15, c1, 2 @ restore CP15 - Aux Debug Modes Ctrl 2
311 ALT_SMP(mrc p15, 0, r0, c1, c0, 1)
315 mcrne p15, 0, r10, c1, c0, 1 @ No, update register
330 mrceq p15, 0, r0, c1, c0, 1 @ read aux control register
332 mcreq p15, 0, r0, c1, c0, 1 @ write aux control register
336 mrceq p15, 0, r0, c1, c0, 1 @ read aux control register
339 mcreq p15, 0, r0, c1, c0, 1 @ write aux control register
343 mrceq p15, 1, r0, c9, c0, 2 @ read L2 cache aux ctrl register
346 mcreq p15, 1, r0, c9, c0, 2 @ write the L2 cache aux ctrl register
353 mrcle p15, 0, r0, c15, c0, 1 @ read diagnostic register
355 mcrle p15, 0, r0, c15, c0, 1 @ write diagnostic register
361 mrceq p15, 0, r0, c15, c0, 1 @ read diagnostic register
364 mcreq p15, 0, r0, c15, c0, 1 @ write diagnostic register
368 mrceq p15, 0, r0, c15, c0, 1 @ read diagnostic register
370 mcreq p15, 0, r0, c15, c0, 1 @ write diagnostic register
375 mrclt p15, 0, r0, c15, c0, 1 @ read diagnostic register
377 mcrlt p15, 0, r0, c15, c0, 1 @ write diagnostic register
385 mrcle p15, 0, r0, c1, c0, 1 @ read aux control register
387 mcrle p15, 0, r0, c1, c0, 1 @ write aux control register
393 mrc p15, 0, r10, c15, c0, 1 @ read diagnostic register
395 mcr p15, 0, r10, c15, c0, 1 @ write diagnostic register
398 mrc p15, 0, r10, c15, c0, 2 @ read internal feature reg
400 mcr p15, 0, r10, c15, c0, 2 @ write internal feature reg
403 mrc p15, 0, r10, c15, c0, 1 @ read diagnostic register
405 mcr p15, 0, r10, c15, c0, 1 @ write diagnostic register
408 mrc p15, 0, r10, c15, c0, 1 @ read diagnostic register
410 mcr p15, 0, r10, c15, c0, 1 @ write diagnostic register
417 mrcle p15, 0, r10, c15, c0, 1 @ read diagnostic register
419 mcrle p15, 0, r10, c15, c0, 1 @ write diagnostic register
423 mrcle p15, 0, r10, c15, c0, 1 @ read diagnostic register
425 mcrle p15, 0, r10, c15, c0, 1 @ write diagnostic register
428 mrc p15, 0, r10, c15, c0, 1 @ read diagnostic register
430 mcr p15, 0, r10, c15, c0, 1 @ write diagnostic register
438 #define PJ4B_STATIC_BP (1 << 2) /* Enable Static BP */
442 /* Auxiliary Debug Modes Control 2 Register */
453 #define PJ4B_L1_PAR_CHK (1 << 2) /* Support L1 parity checking */
466 /* Auxiliary Debug Modes Control 2 Register */
467 mrc p15, 1, r0, c15, c1, 2
470 mcr p15, 1, r0, c15, c1, 2
538 mrc p15, 0, r0, c0, c1, 0 @ read ID_PFR0 for ThumbEE
543 mcr p14, 6, r3, c1, c0, 0 @ Initialize TEEHBR to 0
544 mrc p14, 6, r0, c0, c0, 0 @ load TEECR
546 mcr p14, 6, r0, c0, c0, 0 @ stop userspace TEEHBR access
556 mrc p15, 0, r0, c1, c0, 0 @ read control register