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/linux/arch/mips/include/asm/
H A Dsim.h28 ".frame\t$29, 0, $31\n\t" \
29 "sw\t$16,"__str(PT_R16)"($29)\t\t\t# save_static_function\n\t" \
30 "sw\t$17,"__str(PT_R17)"($29)\n\t" \
31 "sw\t$18,"__str(PT_R18)"($29)\n\t" \
32 "sw\t$19,"__str(PT_R19)"($29)\n\t" \
33 "sw\t$20,"__str(PT_R20)"($29)\n\t" \
34 "sw\t$21,"__str(PT_R21)"($29)\n\t" \
35 "sw\t$22,"__str(PT_R22)"($29)\n\t" \
36 "sw\t$23,"__str(PT_R23)"($29)\n\t" \
37 "sw\t$30,"__str(PT_R30)"($29)\n\t" \
[all …]
/linux/drivers/gpu/drm/i915/gt/
H A Dintel_gpu_commands.h21 #define INSTR_CLIENT_SHIFT 29
199 #define GFX_INSTR(opcode, flags) ((0x3 << 29) | ((opcode) << 24) | (flags))
201 #define GEN9_MEDIA_POOL_STATE ((0x3 << 29) | (0x2 << 27) | (0x5 << 16) | 4)
203 #define GFX_OP_RASTER_RULES ((0x3<<29)|(0x7<<24))
204 #define GFX_OP_SCISSOR ((0x3<<29)|(0x1c<<24)|(0x10<<19))
208 #define GFX_OP_LOAD_INDIRECT ((0x3<<29)|(0x1d<<24)|(0x7<<16))
209 #define GFX_OP_SCISSOR_INFO ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1))
214 #define GFX_OP_SCISSOR_ENABLE ((0x3<<29)|(0x1c<<24)|(0x10<<19))
215 #define GFX_OP_SCISSOR_RECT ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1)
216 #define GFX_OP_COLOR_FACTOR ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0)
[all …]
/linux/arch/powerpc/crypto/
H A Dcurve25519-ppc64le_asm.S82 std 29,120(1)
108 mulhdu 29,10,6
134 adde 29,29,21
160 adde 29,29,21
186 adde 29,29,21
205 adde 29,29,21
223 addze 29,29
229 insrdi 12,29,51,0
266 ld 29,120(1)
285 std 29,120(1)
[all …]
H A Daes-gcm-p10.S259 vxor 29, 29, 29
260 vsldoi 26, 24, 29, 8 # mL
261 vsldoi 29, 29, 24, 8 # mH
276 vxor 24, 24, 29
316 vxor 29, 29, 29
319 vsldoi 26, 24, 29, 8 # mL
320 vsldoi 29, 29, 24, 8 # mH
335 vxor 24, 24, 29 # H + mH
365 vxor 29, 29, 29
368 vsldoi 26, 24, 29, 8 # mL
[all …]
H A Dpoly1305-p10le_64.S112 SAVE_GPR 29, 232, 1
126 SAVE_VRS 29, 144, 9
145 SAVE_VSX 29, 432, 9
161 RESTORE_VRS 29, 144, 9
180 RESTORE_VSX 29, 432, 9
199 RESTORE_GPR 29, 232, 1
247 vmulouw 17, 4, 29
257 vmulouw 10, 5, 29
301 vmuleuw 9, 4, 29
313 vmuleuw 10, 5, 29
[all …]
H A Dchacha-p10le-8x.S98 SAVE_GPR 29, 232, 1
112 SAVE_VRS 29, 144, 9
131 SAVE_VSX 29, 432, 9
147 RESTORE_VRS 29, 144, 9
166 RESTORE_VSX 29, 432, 9
185 RESTORE_GPR 29, 232, 1
212 vpermxor 29, 29, 17, 25
221 vadduwm 25, 25, 29
260 vpermxor 29, 29, 17, 25
269 vadduwm 25, 25, 29
[all …]
/linux/drivers/gpu/drm/i915/display/
H A Dintel_backlight_regs.h27 #define BLM_PIPE_SELECT (1 << 29)
28 #define BLM_PIPE_SELECT_IVB (3 << 29)
29 #define BLM_PIPE_A (0 << 29)
30 #define BLM_PIPE_B (1 << 29)
31 #define BLM_PIPE_C (2 << 29) /* ivb + */
35 #define BLM_TRANSCODER_EDP (3 << 29)
36 #define BLM_PIPE(pipe) ((pipe) << 29)
84 #define BLM_PCH_POLARITY (1 << 29)
90 #define BXT_BLC_PWM_POLARITY (1 << 29)
108 #define UTIL_PIN_PIPE_MASK (3 << 29)
[all …]
/linux/Documentation/ABI/testing/
H A Dsysfs-class-mtd3 KernelVersion: 2.6.29
11 KernelVersion: 2.6.29
21 KernelVersion: 2.6.29
29 KernelVersion: 2.6.29
38 KernelVersion: 2.6.29
47 KernelVersion: 2.6.29
57 KernelVersion: 2.6.29
70 KernelVersion: 2.6.29
78 KernelVersion: 2.6.29
87 KernelVersion: 2.6.29
[all …]
/linux/Documentation/translations/zh_TW/admin-guide/
H A Dbug-hunting.rst318 Aug 29 09:51:01 blizard kernel: Unable to handle kernel paging request at virtual address f15e97cc
319 Aug 29 09:51:01 blizard kernel: current->tss.cr3 = 0062d000, %cr3 = 0062d000
320 Aug 29 09:51:01 blizard kernel: *pde = 00000000
321 Aug 29 09:51:01 blizard kernel: Oops: 0002
322 Aug 29 09:51:01 blizard kernel: CPU: 0
323 Aug 29 09:51:01 blizard kernel: EIP: 0010:[oops:_oops+16/3868]
324 Aug 29 09:51:01 blizard kernel: EFLAGS: 00010212
325 Aug 29 09:51:01 blizard kernel: eax: 315e97cc ebx: 003a6f80 ecx: 001be77b edx: 00237c0c
326 Aug 29 09:51:01 blizard kernel: esi: 00000000 edi: bffffdb3 ebp: 00589f90 esp: 00589f8c
327 Aug 29 09:51:01 blizard kernel: ds: 0018 es: 0018 fs: 002b gs: 002b ss: 0018
[all …]
/linux/Documentation/translations/zh_CN/admin-guide/
H A Dbug-hunting.rst315 Aug 29 09:51:01 blizard kernel: Unable to handle kernel paging request at virtual address f15e97cc
316 Aug 29 09:51:01 blizard kernel: current->tss.cr3 = 0062d000, %cr3 = 0062d000
317 Aug 29 09:51:01 blizard kernel: *pde = 00000000
318 Aug 29 09:51:01 blizard kernel: Oops: 0002
319 Aug 29 09:51:01 blizard kernel: CPU: 0
320 Aug 29 09:51:01 blizard kernel: EIP: 0010:[oops:_oops+16/3868]
321 Aug 29 09:51:01 blizard kernel: EFLAGS: 00010212
322 Aug 29 09:51:01 blizard kernel: eax: 315e97cc ebx: 003a6f80 ecx: 001be77b edx: 00237c0c
323 Aug 29 09:51:01 blizard kernel: esi: 00000000 edi: bffffdb3 ebp: 00589f90 esp: 00589f8c
324 Aug 29 09:51:01 blizard kernel: ds: 0018 es: 0018 fs: 002b gs: 002b ss: 0018
[all …]
/linux/Documentation/hwmon/
H A Dw83795.rst83 29/ 30 PECI/TSI (DTS1) 26h temp7
84 29/ 30 PECI/TSI (DTS2) 27h temp8
85 29/ 30 PECI/TSI (DTS3) 28h temp9
86 29/ 30 PECI/TSI (DTS4) 29h temp10
87 29/ 30 PECI/TSI (DTS5) 2Ah temp11
88 29/ 30 PECI/TSI (DTS6) 2Bh temp12
89 29/ 30 PECI/TSI (DTS7) 2Ch temp13
90 29/ 30 PECI/TSI (DTS8) 2Dh temp14
136 23 PECI (DTS4) 29h temp10
/linux/drivers/media/platform/samsung/exynos4-is/
H A Dfimc-reg.h18 #define FIMC_REG_CISRCFMT_ITU601_16BIT BIT(29)
28 #define FIMC_REG_CIWDOFST_CLROVRLB BIT(29)
38 #define FIMC_REG_CIGCTRL_SELCAM_ITU_A BIT(29)
79 #define FIMC_REG_CITRGFMT_YCBCR420 (0 << 29)
80 #define FIMC_REG_CITRGFMT_YCBCR422 (1 << 29)
81 #define FIMC_REG_CITRGFMT_YCBCR422_1P (2 << 29)
82 #define FIMC_REG_CITRGFMT_RGB (3 << 29)
83 #define FIMC_REG_CITRGFMT_FMT_MASK (3 << 29)
123 #define FIMC_REG_CISCCTRL_SCALEUP_V BIT(29)
154 #define FIMC_REG_CISTATUS_OVFICR BIT(29)
[all …]
/linux/include/linux/netfilter/
H A Dnf_conntrack_h323_types.h140 eH2250LogicalChannelParameters_mediaChannel = (1 << 29),
181 = (1 << 29),
206 = (1 << 29),
227 eNetworkAccessParameters_t120SetupProcedure = (1 << 29),
237 eOpenLogicalChannel_encryptionSync = (1 << 29),
255 eSetup_UUIE_destinationAddress = (1 << 29),
301 eCallProceeding_UUIE_h245SecurityMode = (1 << 29),
323 eConnect_UUIE_h245SecurityMode = (1 << 29),
351 eAlerting_UUIE_h245SecurityMode = (1 << 29),
394 eFacility_UUIE_conferenceID = (1 << 29),
[all …]
/linux/Documentation/translations/zh_CN/core-api/
H A Dpacking.rst63 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
77 24 25 26 27 28 29 30 31 16 17 18 19 20 21 22 23 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7
89 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 23 22 21 20 19 18 17 16 31 30 29 28 27 26 25 24
102 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
110 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
122 24 25 26 27 28 29 30 31 16 17 18 19 20 21 22 23 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7
132 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 23 22 21 20 19 18 17 16 31 30 29 28 27 26 25 24
143 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
/linux/drivers/gpu/drm/xe/instructions/
H A Dxe_gpu_commands.h11 #define XY_CTRL_SURF_COPY_BLT ((2 << 29) | (0x48 << 22) | 3)
21 #define XY_FAST_COLOR_BLT_CMD (2 << 29 | 0x44 << 22)
28 #define XY_FAST_COPY_BLT_CMD (2 << 29 | 0x42 << 22)
34 #define PVC_MEM_SET_CMD (2 << 29 | 0x5b << 22)
42 #define GFX_OP_PIPE_CONTROL(len) ((0x3<<29)|(0x3<<27)|(0x2<<24)|((len)-2))
46 #define PIPE_CONTROL_COMMAND_CACHE_INVALIDATE (1<<29)
/linux/drivers/gpu/drm/exynos/
H A Dregs-scaler.h231 #define SCALER_SRC_SPAN_GET_C_SPAN(r) SCALER_GET(r, 29, 16)
232 #define SCALER_SRC_SPAN_SET_C_SPAN(v) SCALER_SET(v, 29, 16)
243 #define SCALER_SRC_WH_GET_WIDTH(r) SCALER_GET(r, 29, 16)
244 #define SCALER_SRC_WH_SET_WIDTH(v) SCALER_SET(v, 29, 16)
261 #define SCALER_DST_SPAN_GET_C_SPAN(r) SCALER_GET(r, 29, 16)
262 #define SCALER_DST_SPAN_SET_C_SPAN(v) SCALER_SET(v, 29, 16)
267 #define SCALER_DST_WH_GET_WIDTH(r) SCALER_GET(r, 29, 16)
268 #define SCALER_DST_WH_SET_WIDTH(v) SCALER_SET(v, 29, 16)
273 #define SCALER_DST_POS_GET_H_POS(r) SCALER_GET(r, 29, 16)
274 #define SCALER_DST_POS_SET_H_POS(v) SCALER_SET(v, 29, 16)
[all …]
H A Dregs-fimc.h168 /* Y 29th frame start address for output DMA */
225 /* CB 29th frame start address for output DMA */
282 /* CR 29th frame start address for output DMA */
401 #define EXYNOS_CISRCFMT_ITU601_16BIT (1 << 29)
414 #define EXYNOS_CIWDOFST_CLROVRLB (1 << 29)
423 #define EXYNOS_CIGCTRL_SELCAM_ITU_B (0 << 29)
424 #define EXYNOS_CIGCTRL_SELCAM_ITU_A (1 << 29)
425 #define EXYNOS_CIGCTRL_SELCAM_ITU_MASK (1 << 29)
470 #define EXYNOS_CITRGFMT_OUTFORMAT_YCBCR420 (0 << 29)
471 #define EXYNOS_CITRGFMT_OUTFORMAT_YCBCR422 (1 << 29)
[all …]
/linux/drivers/media/pci/zoran/
H A Dzr36057.h75 #define ZR36057_MCTCR_C_EMPTY BIT(29)
84 #define ZR36057_ISR_GIRQ0 BIT(29)
90 #define ZR36057_ICR_GIRQ0 BIT(29)
101 #define ZR36057_JMC_JPG_EXP_MODE (0 << 29)
102 #define ZR36057_JMC_JPG_CMP_MODE BIT(29)
103 #define ZR36057_JMC_MJPG_EXP_MODE (2 << 29)
104 #define ZR36057_JMC_MJPG_CMP_MODE (3 << 29)
/linux/drivers/net/dsa/sja1105/
H A Dsja1105_dynamic_config.c206 sja1105_packing(buf, &cmd->rdwrset, 29, 29, size, op); in sja1105et_vl_lookup_cmd_packing()
220 sja1105_packing(p, &cmd->rdwrset, 29, 29, size, op); in sja1105pqrs_vl_lookup_cmd_packing()
233 sja1105_packing(p, &cmd->errors, 29, 29, size, op); in sja1110_vl_lookup_cmd_packing()
270 sja1105_packing(p, &cmd->errors, 29, 29, size, op); in sja1105pqrs_common_l2_lookup_cmd_packing()
418 sja1105_packing(p, &cmd->errors, 29, 29, size, op); in sja1105et_l2_lookup_cmd_packing()
421 sja1105_packing(buf, &cmd->index, 29, 20, in sja1105et_l2_lookup_cmd_packing()
531 sja1105_packing(p, &cmd->errors, 29, 29, size, op); in sja1110_vlan_lookup_cmd_packing()
562 sja1105_packing(p, &cmd->rdwrset, 29, 29, size, op); in sja1105_l2_forwarding_cmd_packing()
575 sja1105_packing(p, &cmd->errors, 29, 29, size, op); in sja1110_l2_forwarding_cmd_packing()
600 sja1105_packing(reg1, &entry->speed, 30, 29, size, op); in sja1105et_mac_config_entry_packing()
[all …]
/linux/drivers/clk/mxs/
H A Dclk-imx28.c191 clks[cpu_xtal] = mxs_clk_div("cpu_xtal", "ref_xtal", CPU, 16, 10, 29); in mx28_clocks_init()
194 clks[ssp0_div] = mxs_clk_div("ssp0_div", "ssp0_sel", SSP0, 0, 9, 29); in mx28_clocks_init()
195 clks[ssp1_div] = mxs_clk_div("ssp1_div", "ssp1_sel", SSP1, 0, 9, 29); in mx28_clocks_init()
196 clks[ssp2_div] = mxs_clk_div("ssp2_div", "ssp2_sel", SSP2, 0, 9, 29); in mx28_clocks_init()
197 clks[ssp3_div] = mxs_clk_div("ssp3_div", "ssp3_sel", SSP3, 0, 9, 29); in mx28_clocks_init()
198 clks[gpmi_div] = mxs_clk_div("gpmi_div", "gpmi_sel", GPMI, 0, 10, 29); in mx28_clocks_init()
200 clks[emi_xtal] = mxs_clk_div("emi_xtal", "ref_xtal", EMI, 8, 4, 29); in mx28_clocks_init()
201 clks[lcdif_div] = mxs_clk_div("lcdif_div", "lcdif_sel", LCDIF, 0, 13, 29); in mx28_clocks_init()
202 clks[etm_div] = mxs_clk_div("etm_div", "etm_sel", ETM, 0, 7, 29); in mx28_clocks_init()
204 clks[saif0_div] = mxs_clk_frac("saif0_div", "saif0_sel", SAIF0, 0, 16, 29); in mx28_clocks_init()
[all …]
H A Dclk-imx23.c126 clks[cpu_xtal] = mxs_clk_div("cpu_xtal", "ref_xtal", CPU, 16, 10, 29); in mx23_clocks_init()
127 clks[hbus] = mxs_clk_div("hbus", "cpu", HBUS, 0, 5, 29); in mx23_clocks_init()
129 clks[lcdif_div] = mxs_clk_div("lcdif_div", "lcdif_sel", PIX, 0, 12, 29); in mx23_clocks_init()
130 clks[ssp_div] = mxs_clk_div("ssp_div", "ssp_sel", SSP, 0, 9, 29); in mx23_clocks_init()
131 clks[gpmi_div] = mxs_clk_div("gpmi_div", "gpmi_sel", GPMI, 0, 10, 29); in mx23_clocks_init()
133 clks[emi_xtal] = mxs_clk_div("emi_xtal", "ref_xtal", EMI, 8, 4, 29); in mx23_clocks_init()
134 clks[etm_div] = mxs_clk_div("etm_div", "etm_sel", ETM, 0, 6, 29); in mx23_clocks_init()
135 clks[saif_div] = mxs_clk_frac("saif_div", "saif_sel", SAIF, 0, 16, 29); in mx23_clocks_init()
142 clks[pwm] = mxs_clk_gate("pwm", "ref_xtal", XTAL, 29); in mx23_clocks_init()
/linux/drivers/net/wireless/mediatek/mt76/
H A Dmt76_connac2_mac.h57 #define MT_TXD1_OWN_MAC GENMASK(29, 24)
69 #define MT_TXD2_POWER_OFFSET GENMASK(29, 24)
85 #define MT_TXD3_SW_POWER_MGMT BIT(29)
109 #define MT_TXD6_TX_RATE GENMASK(29, 16)
120 #define MT_TXD7_UDP_TCP_SUM BIT(29)
142 #define MT_TXS0_BW GENMASK(30, 29)
166 #define MT_TXS2_LAST_TX_RATE GENMASK(29, 27)
208 #define MT_RXD1_NORMAL_SPP_EN BIT(29)
228 #define MT_RXD2_NORMAL_NDATA BIT(29)
243 #define MT_RXD3_NORMAL_PF_MODE BIT(29)
[all …]
/linux/drivers/net/wireless/mediatek/mt76/mt7603/
H A Dmac.h7 #define MT_RXD0_PKT_TYPE GENMASK(31, 29)
43 #define MT_RXD2_NORMAL_NDATA BIT(29)
62 #define MT_RXD3_NORMAL_PF_MODE BIT(29)
73 #define MT_RXV1_VHTA2_B8_B1 GENMASK(29, 22)
89 #define MT_RXV3_F_AGC1_CAL_GAIN GENMASK(31, 29)
100 #define MT_RXV4_F_AGC_CAL_GAIN GENMASK(31, 29)
151 #define MT_TXD2_BA_DISABLE BIT(29)
185 #define MT_TXD6_TX_RATE GENMASK(29, 18)
233 #define MT_TXS4_LAST_TX_RATE GENMASK(31, 29)
/linux/Documentation/admin-guide/
H A Dbug-hunting.rst354 Aug 29 09:51:01 blizard kernel: Unable to handle kernel paging request at virtual address f15e97cc
355 Aug 29 09:51:01 blizard kernel: current->tss.cr3 = 0062d000, %cr3 = 0062d000
356 Aug 29 09:51:01 blizard kernel: *pde = 00000000
357 Aug 29 09:51:01 blizard kernel: Oops: 0002
358 Aug 29 09:51:01 blizard kernel: CPU: 0
359 Aug 29 09:51:01 blizard kernel: EIP: 0010:[oops:_oops+16/3868]
360 Aug 29 09:51:01 blizard kernel: EFLAGS: 00010212
361 Aug 29 09:51:01 blizard kernel: eax: 315e97cc ebx: 003a6f80 ecx: 001be77b edx: 00237c0c
362 Aug 29 09:51:01 blizard kernel: esi: 00000000 edi: bffffdb3 ebp: 00589f90 esp: 00589f8c
363 Aug 29 09:51:01 blizard kernel: ds: 0018 es: 0018 fs: 002b gs: 002b ss: 0018
[all …]
/linux/drivers/gpu/drm/nouveau/include/nvhw/class/
H A Dcl507c.h31 #define NV_DISP_BASE_NOTIFIER_1__0_TIMESTAMP 29:16
40 #define NV507C_DMA_OPCODE 31:29
45 #define NV507C_DMA_OPCODE 31:29
52 #define NV507C_DMA_OPCODE 31:29
55 #define NV507C_DMA_OPCODE 31:29
98 #define NV507C_SET_BASE_LUT_LO_MODE 29:29

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