Lines Matching full:29
191 clks[cpu_xtal] = mxs_clk_div("cpu_xtal", "ref_xtal", CPU, 16, 10, 29); in mx28_clocks_init()
194 clks[ssp0_div] = mxs_clk_div("ssp0_div", "ssp0_sel", SSP0, 0, 9, 29); in mx28_clocks_init()
195 clks[ssp1_div] = mxs_clk_div("ssp1_div", "ssp1_sel", SSP1, 0, 9, 29); in mx28_clocks_init()
196 clks[ssp2_div] = mxs_clk_div("ssp2_div", "ssp2_sel", SSP2, 0, 9, 29); in mx28_clocks_init()
197 clks[ssp3_div] = mxs_clk_div("ssp3_div", "ssp3_sel", SSP3, 0, 9, 29); in mx28_clocks_init()
198 clks[gpmi_div] = mxs_clk_div("gpmi_div", "gpmi_sel", GPMI, 0, 10, 29); in mx28_clocks_init()
200 clks[emi_xtal] = mxs_clk_div("emi_xtal", "ref_xtal", EMI, 8, 4, 29); in mx28_clocks_init()
201 clks[lcdif_div] = mxs_clk_div("lcdif_div", "lcdif_sel", LCDIF, 0, 13, 29); in mx28_clocks_init()
202 clks[etm_div] = mxs_clk_div("etm_div", "etm_sel", ETM, 0, 7, 29); in mx28_clocks_init()
204 clks[saif0_div] = mxs_clk_frac("saif0_div", "saif0_sel", SAIF0, 0, 16, 29); in mx28_clocks_init()
205 clks[saif1_div] = mxs_clk_frac("saif1_div", "saif1_sel", SAIF1, 0, 16, 29); in mx28_clocks_init()
211 clks[pwm] = mxs_clk_gate("pwm", "ref_xtal", XTAL, 29); in mx28_clocks_init()