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/linux/crypto/
H A Dsha3_generic.c20 * over 1 KB of stack if we inline the round calculation into the loop
47 static SHA3_INLINE void keccakf_round(u64 st[25]) in keccakf_round()
52 bc[0] = st[0] ^ st[5] ^ st[10] ^ st[15] ^ st[20]; in keccakf_round()
53 bc[1] = st[1] ^ st[6] ^ st[11] ^ st[16] ^ st[21]; in keccakf_round()
54 bc[2] = st[2] ^ st[7] ^ st[12] ^ st[17] ^ st[22]; in keccakf_round()
55 bc[3] = st[3] ^ st[8] ^ st[13] ^ st[18] ^ st[23]; in keccakf_round()
56 bc[4] = st[4] ^ st[9] ^ st[14] ^ st[19] ^ st[24]; in keccakf_round()
58 t[0] = bc[4] ^ rol64(bc[1], 1); in keccakf_round()
59 t[1] = bc[0] ^ rol64(bc[2], 1); in keccakf_round()
60 t[2] = bc[1] ^ rol64(bc[3], 1); in keccakf_round()
[all …]
H A Daegis128-neon-inner.c42 static void aegis128_save_state_neon(struct aegis128_state st, void *state) in aegis128_save_state_neon() argument
44 vst1q_u8(state, st.v[0]); in aegis128_save_state_neon()
45 vst1q_u8(state + 16, st.v[1]); in aegis128_save_state_neon()
46 vst1q_u8(state + 32, st.v[2]); in aegis128_save_state_neon()
47 vst1q_u8(state + 48, st.v[3]); in aegis128_save_state_neon()
48 vst1q_u8(state + 64, st.v[4]); in aegis128_save_state_neon()
57 if (!__builtin_expect(aegis128_have_aes_insn, 1)) { in aegis_aes_round()
88 w = (v << 1) ^ (uint8x16_t)(((int8x16_t)v >> 7) & 0x1b); in aegis_aes_round()
107 struct aegis128_state aegis128_update_neon(struct aegis128_state st, in aegis128_update_neon() argument
110 m ^= aegis_aes_round(st.v[4]); in aegis128_update_neon()
[all …]
/linux/Documentation/devicetree/bindings/iio/accel/
H A Dlis302.txt8 - compatible: should be set to "st,lis3lv02d-spi"
15 - compatible: should be set to "st,lis3lv02d"
23 - st,click-single-{x,y,z}: if present, tells the device to issue an
26 - st,click-double-{x,y,z}: if present, tells the device to issue an
29 - st,click-thresh-{x,y,z}: set the x/y/z axis threshold
30 - st,click-click-time-limit: click time limit, from 0 to 127.5msec
32 - st,click-latency: click latency, from 0 to 255 msec with
33 step of 1 msec.
34 - st,click-window: click window, from 0 to 255 msec with
35 step of 1 msec.
[all …]
/linux/Documentation/devicetree/bindings/iio/
H A Dst,st-sensors.yaml4 $id: http://devicetree.org/schemas/iio/st,st-sensors.yaml#
16 - Denis Ciocca <denis.ciocca@st.com>
24 - st,h3lis331dl-accel
25 - st,lis2de12
26 - st,lis2dw12
27 - st,lis2hh12
28 - st,lis2dh12-accel
29 - st,lis2ds12
30 - st,lis302dl
31 - st,lis331dl-accel
[all …]
/linux/drivers/iio/adc/
H A Dat91_adc.c34 #define AT91_ADC_SWRST (1 << 0) /* Software Reset */
35 #define AT91_ADC_START (1 << 1) /* Start Conversion */
40 #define AT91_ADC_TSAMOD_TS_ONLY_MODE (1 << 0) /* Touch Screen Only Mode */
41 #define AT91_ADC_TRGEN (1 << 0) /* Trigger Enable */
42 #define AT91_ADC_TRGSEL (7 << 1) /* Trigger Selection */
43 #define AT91_ADC_TRGSEL_TC0 (0 << 1)
44 #define AT91_ADC_TRGSEL_TC1 (1 << 1)
45 #define AT91_ADC_TRGSEL_TC2 (2 << 1)
46 #define AT91_ADC_TRGSEL_EXTERNAL (6 << 1)
47 #define AT91_ADC_LOWRES (1 << 4) /* Low Resolution */
[all …]
H A Dad7298.c32 #define AD7298_TAVG BIT(1) /* temperature sensor averaging enable */
59 .indexed = 1, \
76 .indexed = 1,
82 .scan_index = -1,
90 AD7298_V_CHAN(1),
106 struct ad7298_state *st = iio_priv(indio_dev); in ad7298_update_scan_mode() local
115 command = AD7298_WRITE | st->ext_ref; in ad7298_update_scan_mode()
117 for (i = 0, m = AD7298_CH(0); i < AD7298_MAX_CHAN; i++, m >>= 1) in ad7298_update_scan_mode()
121 st->tx_buf[0] = cpu_to_be16(command); in ad7298_update_scan_mode()
124 st->ring_xfer[0].tx_buf = &st->tx_buf[0]; in ad7298_update_scan_mode()
[all …]
H A Dad4130.c47 #define AD4130_ADC_CONTROL_MCLK_SEL_MASK GENMASK(1, 0)
83 #define AD4130_CONFIG_PGA_MASK GENMASK(3, 1)
88 #define AD4130_FILTER_SELECT_MIN 1
125 #define AD4130_INVALID_SLOT -1
128 [AD4130_STATUS_REG] = 1,
133 [AD4130_ID_REG] = 1,
136 [AD4130_MCLK_COUNT_REG] = 1,
137 [AD4130_CHANNEL_X_REG(0) ... AD4130_CHANNEL_X_REG(AD4130_MAX_CHANNELS - 1)] = 3,
138 [AD4130_CONFIG_X_REG(0) ... AD4130_CONFIG_X_REG(AD4130_MAX_SETUPS - 1)] = 2,
139 [AD4130_FILTER_X_REG(0) ... AD4130_FILTER_X_REG(AD4130_MAX_SETUPS - 1)] = 3,
[all …]
H A Dad7887.c30 #define AD7887_CH_AIN1 BIT(3) /* convert on channel 1, DUAL=1 */
31 #define AD7887_CH_AIN0 0 /* convert on channel 0, DUAL=0,1 */
33 #define AD7887_PM_MODE2 1 /* full on */
83 struct ad7887_state *st = iio_priv(indio_dev); in ad7887_ring_preenable() local
87 case (1 << 0): in ad7887_ring_preenable()
88 st->ring_msg = &st->msg[AD7887_CH0]; in ad7887_ring_preenable()
90 case (1 << 1): in ad7887_ring_preenable()
91 st->ring_msg = &st->msg[AD7887_CH1]; in ad7887_ring_preenable()
93 spi_sync(st->spi, st->ring_msg); in ad7887_ring_preenable()
95 case ((1 << 1) | (1 << 0)): in ad7887_ring_preenable()
[all …]
H A Dad7192.c37 #define AD7192_REG_MODE 1 /* Mode Register (RW, 24-bit */
60 #define AD7192_STAT_CH2 BIT(1) /* Channel 2 */
61 #define AD7192_STAT_CH1 BIT(0) /* Channel 1 */
79 #define AD7192_MODE_SINGLE 1 /* Single Conversion Mode */
90 #define AD7192_CLK_EXT_MCLK2 1 /* External Clock applied to MCLK2 */
109 #define AD7192_CH_AIN3P_AIN4M BIT(1) /* AIN3(+) - AIN4(-) */
133 #define AD7194_CH_POS(x) (((x) - 1) << 4)
134 #define AD7194_CH_NEG(x) ((x) - 1)
142 #define AD7194_CH_AIN_START 1
160 #define AD7192_GPOCON_P1DAT BIT(1) /* P1 state */
[all …]
H A Dad7266.c52 static int ad7266_wakeup(struct ad7266_state *st) in ad7266_wakeup() argument
55 return spi_read(st->spi, &st->data.sample[0], 2); in ad7266_wakeup()
58 static int ad7266_powerdown(struct ad7266_state *st) in ad7266_powerdown() argument
61 return spi_read(st->spi, &st->data.sample[0], 1); in ad7266_powerdown()
66 struct ad7266_state *st = iio_priv(indio_dev); in ad7266_preenable() local
67 return ad7266_wakeup(st); in ad7266_preenable()
72 struct ad7266_state *st = iio_priv(indio_dev); in ad7266_postdisable() local
73 return ad7266_powerdown(st); in ad7266_postdisable()
85 struct ad7266_state *st = iio_priv(indio_dev); in ad7266_trigger_handler() local
88 ret = spi_read(st->spi, st->data.sample, 4); in ad7266_trigger_handler()
[all …]
H A Dad7280a.c46 #define AD7280A_CTRL_HB_CONV_INPUT_6CELL_AUX1_3_5 1
51 #define AD7280A_CTRL_HB_CONV_RREAD_6CELL_AUX1_3_5 1
56 #define AD7280A_CTRL_HB_CONV_START_CS 1
57 #define AD7280A_CTRL_HB_CONV_AVG_MSK GENMASK(2, 1)
59 #define AD7280A_CTRL_HB_CONV_AVG_2 1
68 #define AD7280A_CTRL_LB_ACQ_TIME_800ns 1
74 #define AD7280A_CTRL_LB_INC_DEV_ADDR_MSK BIT(1)
85 #define AD7280A_ALERT_REMOVE_AUX3_AUX5 BIT(1)
125 #define AD7280A_MAX_SPI_CLK_HZ 700000 /* < 1MHz */
130 AD7280A_CELL_VOLTAGE_1_REG + 1)
[all …]
H A Dad7606.c45 1, 2, 4, 8, 16, 32, 64,
49 1, 2, 4, 8, 16, 32, 64, 128,
52 int ad7606_reset(struct ad7606_state *st) in ad7606_reset() argument
54 if (st->gpio_reset) { in ad7606_reset()
55 gpiod_set_value(st->gpio_reset, 1); in ad7606_reset()
57 gpiod_set_value(st->gpio_reset, 0); in ad7606_reset()
70 struct ad7606_state *st = iio_priv(indio_dev); in ad7606_reg_access() local
73 guard(mutex)(&st->lock); in ad7606_reg_access()
76 ret = st->bops->reg_read(st, reg); in ad7606_reg_access()
82 return st->bops->reg_write(st, reg, writeval); in ad7606_reg_access()
[all …]
/linux/drivers/staging/iio/frequency/
H A Dad9832.c72 #define RES_MASK(bits) ((1 << (bits)) - 1)
124 (u64)((u64)1L << AD9832_FREQ_BITS); in ad9832_calc_freqreg()
129 static int ad9832_write_frequency(struct ad9832_state *st, in ad9832_write_frequency() argument
135 clk_freq = clk_get_rate(st->mclk); in ad9832_write_frequency()
142 st->freq_data[0] = cpu_to_be16((AD9832_CMD_FRE8BITSW << CMD_SHIFT) | in ad9832_write_frequency()
145 st->freq_data[1] = cpu_to_be16((AD9832_CMD_FRE16BITSW << CMD_SHIFT) | in ad9832_write_frequency()
146 ((addr - 1) << ADD_SHIFT) | in ad9832_write_frequency()
148 st->freq_data[2] = cpu_to_be16((AD9832_CMD_FRE8BITSW << CMD_SHIFT) | in ad9832_write_frequency()
151 st->freq_data[3] = cpu_to_be16((AD9832_CMD_FRE16BITSW << CMD_SHIFT) | in ad9832_write_frequency()
155 return spi_sync(st->spi, &st->freq_msg); in ad9832_write_frequency()
[all …]
H A Dad9834.c49 #define AD9834_MODE BIT(1)
54 #define RES_MASK(bits) (BIT(bits) - 1)
109 static int ad9834_write_frequency(struct ad9834_state *st, in ad9834_write_frequency() argument
115 clk_freq = clk_get_rate(st->mclk); in ad9834_write_frequency()
122 st->freq_data[0] = cpu_to_be16(addr | (regval & in ad9834_write_frequency()
124 st->freq_data[1] = cpu_to_be16(addr | ((regval >> in ad9834_write_frequency()
128 return spi_sync(st->spi, &st->freq_msg); in ad9834_write_frequency()
131 static int ad9834_write_phase(struct ad9834_state *st, in ad9834_write_phase() argument
136 st->data = cpu_to_be16(addr | phase); in ad9834_write_phase()
138 return spi_sync(st->spi, &st->msg); in ad9834_write_phase()
[all …]
/linux/drivers/gpu/drm/etnaviv/
H A Detnaviv_cmd_parser.c26 #define ST(start, num) { (start) >> 2, (num) } macro
28 ST(0x1200, 1),
29 ST(0x1228, 1),
30 ST(0x1238, 1),
31 ST(0x1284, 1),
32 ST(0x128c, 1),
33 ST(0x1304, 1),
34 ST(0x1310, 1),
35 ST(0x1318, 1),
36 ST(0x12800, 4),
[all …]
/linux/drivers/iio/filter/
H A Dadmv8818.c54 #define ADMV8818_LSBFIRST_MSK BIT(1)
118 [1] = "manual",
122 static int __admv8818_hpf_select(struct admv8818_state *st, u64 freq) in __admv8818_hpf_select() argument
131 if (freq > freq_range_hpf[3][1]) { in __admv8818_hpf_select()
139 freq_step = div_u64((freq_range_hpf[i][1] - in __admv8818_hpf_select()
143 (freq < freq_range_hpf[i][1] + freq_step)) { in __admv8818_hpf_select()
144 hpf_band = i + 1; in __admv8818_hpf_select()
146 for (j = 1; j <= 16; j++) { in __admv8818_hpf_select()
148 hpf_step = j - 1; in __admv8818_hpf_select()
163 ret = regmap_update_bits(st->regmap, ADMV8818_REG_WR0_SW, in __admv8818_hpf_select()
[all …]
/linux/drivers/iio/accel/
H A Dadxl380.c65 #define ADXL380_FIFO_NORMAL 1
79 #define ADXL380_TAP_AXIS_MSK GENMASK(1, 0)
95 #define ADXL380_OP_MODE_HEART_SOUND 1
110 #define ADXL380_OP_MODE_8G_RANGE 1
111 #define ADXL382_OP_MODE_30G_RANGE 1
127 #define ADXL380_INT_MAP1_DOUBLE_TAP_INT0_MSK BIT(1)
140 #define ADXL380_STATUS_0_FIFO_FULL_MSK BIT(1)
145 #define ADXL380_STATUS_1_DOUBLE_TAP_MSK BIT(1)
179 static const int adxl380_range_scale_factor_tbl[] = { 1, 2, 4 };
268 static int adxl380_set_measure_en(struct adxl380_state *st, bool en) in adxl380_set_measure_en() argument
[all …]
H A Dsca3000.c34 #define SCA3000_EEPROM_CS_ERROR BIT(1)
63 * (approx 1 - 25Hz) and then a programmable threshold used to trigger
77 #define SCA3000_INT_STATUS_X_TRIGGER BIT(1)
109 #define SCA3000_MD_CTRL_OR_X BIT(1)
182 * @option_mode_1_freq: option mode 1 sampling frequency
277 static int sca3000_write_reg(struct sca3000_state *st, u8 address, u8 val) in sca3000_write_reg() argument
279 st->tx[0] = SCA3000_WRITE_REG(address); in sca3000_write_reg()
280 st->tx[1] = val; in sca3000_write_reg()
281 return spi_write(st->us, st->tx, 2); in sca3000_write_reg()
284 static int sca3000_read_data_short(struct sca3000_state *st, in sca3000_read_data_short() argument
[all …]
/linux/drivers/macintosh/
H A Dwindfarm_pid.c25 void wf_pid_init(struct wf_pid_state *st, struct wf_pid_param *param) in wf_pid_init() argument
27 memset(st, 0, sizeof(struct wf_pid_state)); in wf_pid_init()
28 st->param = *param; in wf_pid_init()
29 st->first = 1; in wf_pid_init()
33 s32 wf_pid_run(struct wf_pid_state *st, s32 new_sample) in wf_pid_run() argument
37 int i, hlen = st->param.history_len; in wf_pid_run()
40 error = new_sample - st->param.itarget; in wf_pid_run()
43 if (st->first) { in wf_pid_run()
45 st->samples[i] = new_sample; in wf_pid_run()
46 st->errors[i] = error; in wf_pid_run()
[all …]
/linux/drivers/iio/common/hid-sensors/
H A Dhid-sensor-attributes.c22 HID_USAGE_SENSOR_UNITS_METERS_PER_SEC_SQRD, 1, 0},
28 HID_USAGE_SENSOR_UNITS_METERS_PER_SEC_SQRD, 1, 0},
34 HID_USAGE_SENSOR_UNITS_RADIANS_PER_SECOND, 1, 0},
39 {HID_USAGE_SENSOR_COMPASS_3D, HID_USAGE_SENSOR_UNITS_GAUSS, 1, 0},
45 HID_USAGE_SENSOR_UNITS_RADIANS, 1, 0},
47 {HID_USAGE_SENSOR_ALS, 0, 1, 0},
48 {HID_USAGE_SENSOR_ALS, HID_USAGE_SENSOR_UNITS_LUX, 1, 0},
57 {HID_USAGE_SENSOR_DEVICE_ORIENTATION, 0, 1, 0},
59 {HID_USAGE_SENSOR_RELATIVE_ORIENTATION, 0, 1, 0},
61 {HID_USAGE_SENSOR_GEOMAGNETIC_ORIENTATION, 0, 1, 0},
[all …]
/linux/drivers/iio/frequency/
H A Dadrf6780.c52 #define ADRF6780_LO_EN_MSK BIT(1)
66 #define ADRF6780_ADC_EN_MSK BIT(1)
91 static int __adrf6780_spi_read(struct adrf6780_state *st, unsigned int reg, in __adrf6780_spi_read() argument
97 st->data[0] = 0x80 | (reg << 1); in __adrf6780_spi_read()
98 st->data[1] = 0x0; in __adrf6780_spi_read()
99 st->data[2] = 0x0; in __adrf6780_spi_read()
101 t.rx_buf = &st->data[0]; in __adrf6780_spi_read()
102 t.tx_buf = &st->data[0]; in __adrf6780_spi_read()
105 ret = spi_sync_transfer(st->spi, &t, 1); in __adrf6780_spi_read()
109 *val = (get_unaligned_be24(&st->data[0]) >> 1) & GENMASK(15, 0); in __adrf6780_spi_read()
[all …]
H A Dadf4377.c32 #define ADF4377_0000_LSB_FIRST_MSK BIT(1)
158 #define ADF4377_0019_PD_ADC_MSK BIT(1)
174 #define ADF4377_001A_PD_CLKOUT1_MSK BIT(1)
202 #define ADF4377_001D_CP_DOWN_MSK BIT(1)
286 #define ADF4377_002E_EN_ADC_MSK BIT(1)
294 #define ADF4377_002F_DCLK_DIV1_MSK GENMASK(1, 0)
330 #define ADF4377_003D_O_VCO_BIAS_MSK BIT(1)
353 #define ADF4377_0049_FSM_BUSY_MSK BIT(1)
357 #define ADF4377_004B_VCO_CORE_MSK GENMASK(1, 0)
479 struct adf4377_state *st = iio_priv(indio_dev); in adf4377_reg_access() local
[all …]
/linux/Documentation/devicetree/bindings/mfd/
H A Dst,stmpe.yaml4 $id: http://devicetree.org/schemas/mfd/st,stmpe.yaml#
23 - st,stmpe601
24 - st,stmpe801
25 - st,stmpe811
26 - st,stmpe1600
27 - st,stmpe1601
28 - st,stmpe2401
29 - st,stmpe2403
32 maxItems: 1
35 maxItems: 1
[all …]
/linux/drivers/iio/resolver/
H A Dad2s1210.c17 * LOT Low Threshold [1] | 0x8E | events/in_angl1_thresh_rising_hysteresis
27 * [1]: The value written to the LOT low register is high value minus the
75 #define AD2S1210_SET_RES GENMASK(1, 0)
84 #define AD2S1210_FAULT_PHASE BIT(1)
118 /* Threshold voltage registers have 1 LSB == 38 mV */
175 static int ad2s1210_set_mode(struct ad2s1210_state *st, enum ad2s1210_mode mode) in ad2s1210_set_mode() argument
177 struct gpio_descs *gpios = st->mode_gpios; in ad2s1210_set_mode()
181 return mode == st->fixed_mode ? 0 : -EOPNOTSUPP; in ad2s1210_set_mode()
198 struct ad2s1210_state *st = context; in ad2s1210_regmap_reg_write() local
201 .len = 1, in ad2s1210_regmap_reg_write()
[all …]
/linux/drivers/iio/dac/
H A Dad5791.c32 #define AD5791_ADDR_DAC0 1
38 #define AD5791_CTRL_RBUF BIT(1)
46 #define AD5791_LINCOMP_10_12 1
56 #define AD5791_SWCTRL_CLR BIT(1)
60 #define AD5791_DAC_PWRDN_3STATE 1
108 static int ad5791_spi_write(struct ad5791_state *st, u8 addr, u32 val) in ad5791_spi_write() argument
110 st->data[0].d32 = cpu_to_be32(AD5791_CMD_WRITE | in ad5791_spi_write()
114 return spi_write(st->spi, &st->data[0].d8[1], 3); in ad5791_spi_write()
117 static int ad5791_spi_read(struct ad5791_state *st, u8 addr, u32 *val) in ad5791_spi_read() argument
122 .tx_buf = &st->data[0].d8[1], in ad5791_spi_read()
[all …]

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