65 #define ADXL380_FIFO_NORMAL			1
79 #define ADXL380_TAP_AXIS_MSK			GENMASK(1, 0)
95 #define ADXL380_OP_MODE_HEART_SOUND		1
110 #define ADXL380_OP_MODE_8G_RANGE		1
111 #define ADXL382_OP_MODE_30G_RANGE		1
127 #define ADXL380_INT_MAP1_DOUBLE_TAP_INT0_MSK	BIT(1)
140 #define ADXL380_STATUS_0_FIFO_FULL_MSK		BIT(1)
145 #define ADXL380_STATUS_1_DOUBLE_TAP_MSK		BIT(1)
179 static const int adxl380_range_scale_factor_tbl[] = { 1, 2, 4 };
268 static int adxl380_set_measure_en(struct adxl380_state *st, bool en)  in adxl380_set_measure_en()  argument
275 		ret = regmap_read(st->regmap, ADXL380_ACT_INACT_CTL_REG, &act_inact_ctl);  in adxl380_set_measure_en()
287 	return regmap_update_bits(st->regmap, ADXL380_OP_MODE_REG,  in adxl380_set_measure_en()
292 static void adxl380_scale_act_inact_thresholds(struct adxl380_state *st,  in adxl380_scale_act_inact_thresholds()  argument
296 	st->act_threshold = mult_frac(st->act_threshold,  in adxl380_scale_act_inact_thresholds()
299 	st->inact_threshold = mult_frac(st->inact_threshold,  in adxl380_scale_act_inact_thresholds()
304 static int adxl380_write_act_inact_threshold(struct adxl380_state *st,  in adxl380_write_act_inact_threshold()  argument
314 	ret = regmap_write(st->regmap, reg + 1, th & GENMASK(7, 0));  in adxl380_write_act_inact_threshold()
318 	ret = regmap_update_bits(st->regmap, reg, GENMASK(2, 0), th >> 8);  in adxl380_write_act_inact_threshold()
323 		st->act_threshold = th;  in adxl380_write_act_inact_threshold()
325 		st->inact_threshold = th;  in adxl380_write_act_inact_threshold()
334 	struct adxl380_state *st = iio_priv(indio_dev);  in adxl380_set_act_inact_threshold()  local
337 	guard(mutex)(&st->lock);  in adxl380_set_act_inact_threshold()
339 	ret = adxl380_set_measure_en(st, false);  in adxl380_set_act_inact_threshold()
343 	ret = adxl380_write_act_inact_threshold(st, act, th);  in adxl380_set_act_inact_threshold()
347 	return adxl380_set_measure_en(st, true);  in adxl380_set_act_inact_threshold()
353 	struct adxl380_state *st = iio_priv(indio_dev);  in adxl380_set_tap_threshold_value()  local
355 	guard(mutex)(&st->lock);  in adxl380_set_tap_threshold_value()
357 	ret = adxl380_set_measure_en(st, false);  in adxl380_set_tap_threshold_value()
361 	ret = regmap_write(st->regmap, ADXL380_TAP_THRESH_REG, th);  in adxl380_set_tap_threshold_value()
365 	st->tap_threshold = th;  in adxl380_set_tap_threshold_value()
367 	return adxl380_set_measure_en(st, true);  in adxl380_set_tap_threshold_value()
370 static int _adxl380_write_tap_time_us(struct adxl380_state *st,  in _adxl380_write_tap_time_us()  argument
383 	ret = regmap_write(st->regmap, reg, reg_val);  in _adxl380_write_tap_time_us()
388 		st->tap_window_us = us;  in _adxl380_write_tap_time_us()
390 		st->tap_latent_us = us;  in _adxl380_write_tap_time_us()
395 static int adxl380_write_tap_time_us(struct adxl380_state *st,  in adxl380_write_tap_time_us()  argument
400 	guard(mutex)(&st->lock);  in adxl380_write_tap_time_us()
402 	ret = adxl380_set_measure_en(st, false);  in adxl380_write_tap_time_us()
406 	ret = _adxl380_write_tap_time_us(st, tap_time_type, us);  in adxl380_write_tap_time_us()
410 	return adxl380_set_measure_en(st, true);  in adxl380_write_tap_time_us()
417 	struct adxl380_state *st = iio_priv(indio_dev);  in adxl380_write_tap_dur_us()  local
422 	ret = adxl380_set_measure_en(st, false);  in adxl380_write_tap_dur_us()
426 	ret = regmap_write(st->regmap, ADXL380_TAP_DUR_REG, reg_val);  in adxl380_write_tap_dur_us()
430 	return adxl380_set_measure_en(st, true);  in adxl380_write_tap_dur_us()
433 static int adxl380_read_chn(struct adxl380_state *st, u8 addr)  in adxl380_read_chn()  argument
437 	guard(mutex)(&st->lock);  in adxl380_read_chn()
439 	ret = regmap_bulk_read(st->regmap, addr, &st->transf_buf, 2);  in adxl380_read_chn()
443 	return get_unaligned_be16(st->transf_buf);  in adxl380_read_chn()
446 static int adxl380_get_odr(struct adxl380_state *st, int *odr)  in adxl380_get_odr()  argument
451 	ret = regmap_read(st->regmap, ADXL380_TRIG_CFG_REG, &trig_cfg);  in adxl380_get_odr()
455 	odr_idx = (FIELD_GET(ADXL380_TRIG_CFG_SINC_RATE_MSK, trig_cfg) << 1) |  in adxl380_get_odr()
456 		  (FIELD_GET(ADXL380_TRIG_CFG_DEC_2X_MSK, trig_cfg) & 1);  in adxl380_get_odr()
458 	*odr = st->chip_info->samp_freq_tbl[odr_idx];  in adxl380_get_odr()
464 	1, 4, 8, 16,
467 static int adxl380_fill_lpf_tbl(struct adxl380_state *st)  in adxl380_fill_lpf_tbl()  argument
472 	ret = adxl380_get_odr(st, &odr);  in adxl380_fill_lpf_tbl()
476 	for (i = 0; i < ARRAY_SIZE(st->lpf_tbl); i++)  in adxl380_fill_lpf_tbl()
477 		st->lpf_tbl[i] = DIV_ROUND_CLOSEST(odr, adxl380_lpf_div[i]);  in adxl380_fill_lpf_tbl()
486 static int adxl380_fill_hpf_tbl(struct adxl380_state *st)  in adxl380_fill_hpf_tbl()  argument
492 	ret =  adxl380_get_odr(st, &odr_hz);  in adxl380_fill_hpf_tbl()
502 		st->hpf_tbl[i][0] = div;  in adxl380_fill_hpf_tbl()
503 		st->hpf_tbl[i][1] = div_u64(rem, MEGA * 100);  in adxl380_fill_hpf_tbl()
509 static int adxl380_set_odr(struct adxl380_state *st, u8 odr)  in adxl380_set_odr()  argument
513 	guard(mutex)(&st->lock);  in adxl380_set_odr()
515 	ret = adxl380_set_measure_en(st, false);  in adxl380_set_odr()
519 	ret = regmap_update_bits(st->regmap, ADXL380_TRIG_CFG_REG,  in adxl380_set_odr()
521 				 FIELD_PREP(ADXL380_TRIG_CFG_DEC_2X_MSK, odr & 1));  in adxl380_set_odr()
525 	ret = regmap_update_bits(st->regmap, ADXL380_TRIG_CFG_REG,  in adxl380_set_odr()
527 				 FIELD_PREP(ADXL380_TRIG_CFG_SINC_RATE_MSK, odr >> 1));  in adxl380_set_odr()
531 	ret = adxl380_set_measure_en(st, true);  in adxl380_set_odr()
535 	ret = adxl380_fill_lpf_tbl(st);  in adxl380_set_odr()
539 	return adxl380_fill_hpf_tbl(st);  in adxl380_set_odr()
552 	return size - 1;  in adxl380_find_match_1d_tbl()
560 		if (freq_tbl[i][0] == val && freq_tbl[i][1] == val2)  in adxl380_find_match_2d_tbl()
567 static int adxl380_get_lpf(struct adxl380_state *st, int *lpf)  in adxl380_get_lpf()  argument
572 	guard(mutex)(&st->lock);  in adxl380_get_lpf()
574 	ret = regmap_read(st->regmap, ADXL380_FILTER_REG, &trig_cfg);  in adxl380_get_lpf()
580 	*lpf = st->lpf_tbl[lpf_idx];  in adxl380_get_lpf()
585 static int adxl380_set_lpf(struct adxl380_state *st, u8 lpf)  in adxl380_set_lpf()  argument
590 	guard(mutex)(&st->lock);  in adxl380_set_lpf()
592 	ret = adxl380_set_measure_en(st, false);  in adxl380_set_lpf()
597 		eq_bypass = 1;  in adxl380_set_lpf()
599 	ret = regmap_update_bits(st->regmap, ADXL380_FILTER_REG,  in adxl380_set_lpf()
605 	ret = regmap_update_bits(st->regmap, ADXL380_FILTER_REG,  in adxl380_set_lpf()
611 	return adxl380_set_measure_en(st, true);  in adxl380_set_lpf()
614 static int adxl380_get_hpf(struct adxl380_state *st, int *hpf_int, int *hpf_frac)  in adxl380_get_hpf()  argument
619 	guard(mutex)(&st->lock);  in adxl380_get_hpf()
621 	ret = regmap_read(st->regmap, ADXL380_FILTER_REG, &trig_cfg);  in adxl380_get_hpf()
627 	*hpf_int = st->hpf_tbl[hpf_idx][0];  in adxl380_get_hpf()
628 	*hpf_frac = st->hpf_tbl[hpf_idx][1];  in adxl380_get_hpf()
633 static int adxl380_set_hpf(struct adxl380_state *st, u8 hpf)  in adxl380_set_hpf()  argument
638 	guard(mutex)(&st->lock);  in adxl380_set_hpf()
640 	ret = adxl380_set_measure_en(st, false);  in adxl380_set_hpf()
645 		hpf_path = 1;  in adxl380_set_hpf()
647 	ret = regmap_update_bits(st->regmap, ADXL380_FILTER_REG,  in adxl380_set_hpf()
653 	ret = regmap_update_bits(st->regmap, ADXL380_FILTER_REG,  in adxl380_set_hpf()
659 	return adxl380_set_measure_en(st, true);  in adxl380_set_hpf()
662 static int _adxl380_set_act_inact_time_ms(struct adxl380_state *st,  in _adxl380_set_act_inact_time_ms()  argument
673 	put_unaligned_be24(reg_val, &st->transf_buf[0]);  in _adxl380_set_act_inact_time_ms()
675 	ret = regmap_bulk_write(st->regmap, reg, st->transf_buf, sizeof(st->transf_buf));  in _adxl380_set_act_inact_time_ms()
680 		st->act_time_ms = ms;  in _adxl380_set_act_inact_time_ms()
682 		st->inact_time_ms = ms;  in _adxl380_set_act_inact_time_ms()
687 static int adxl380_set_act_inact_time_ms(struct adxl380_state *st,  in adxl380_set_act_inact_time_ms()  argument
693 	guard(mutex)(&st->lock);  in adxl380_set_act_inact_time_ms()
695 	ret = adxl380_set_measure_en(st, false);  in adxl380_set_act_inact_time_ms()
699 	ret = _adxl380_set_act_inact_time_ms(st, act, ms);  in adxl380_set_act_inact_time_ms()
703 	return adxl380_set_measure_en(st, true);  in adxl380_set_act_inact_time_ms()
706 static int adxl380_set_range(struct adxl380_state *st, u8 range)  in adxl380_set_range()  argument
710 	guard(mutex)(&st->lock);  in adxl380_set_range()
712 	ret = adxl380_set_measure_en(st, false);  in adxl380_set_range()
716 	ret = regmap_update_bits(st->regmap, ADXL380_OP_MODE_REG,  in adxl380_set_range()
723 	adxl380_scale_act_inact_thresholds(st, st->range, range);  in adxl380_set_range()
726 	ret = adxl380_write_act_inact_threshold(st, ADXL380_ACTIVITY,  in adxl380_set_range()
727 						st->act_threshold);  in adxl380_set_range()
731 	ret = adxl380_write_act_inact_threshold(st, ADXL380_INACTIVITY,  in adxl380_set_range()
732 						st->inact_threshold);  in adxl380_set_range()
736 	st->range = range;  in adxl380_set_range()
738 	return adxl380_set_measure_en(st, true);  in adxl380_set_range()
741 static int adxl380_write_act_inact_en(struct adxl380_state *st,  in adxl380_write_act_inact_en()  argument
746 		return regmap_update_bits(st->regmap, ADXL380_ACT_INACT_CTL_REG,  in adxl380_write_act_inact_en()
750 	return regmap_update_bits(st->regmap, ADXL380_ACT_INACT_CTL_REG,  in adxl380_write_act_inact_en()
755 static int adxl380_read_act_inact_int(struct adxl380_state *st,  in adxl380_read_act_inact_int()  argument
762 	guard(mutex)(&st->lock);  in adxl380_read_act_inact_int()
764 	ret = regmap_read(st->regmap, st->int_map[0], &reg_val);  in adxl380_read_act_inact_int()
776 static int adxl380_write_act_inact_int(struct adxl380_state *st,  in adxl380_write_act_inact_int()  argument
781 		return regmap_update_bits(st->regmap, st->int_map[0],  in adxl380_write_act_inact_int()
785 	return regmap_update_bits(st->regmap, st->int_map[0],  in adxl380_write_act_inact_int()
790 static int adxl380_act_inact_config(struct adxl380_state *st,  in adxl380_act_inact_config()  argument
796 	guard(mutex)(&st->lock);  in adxl380_act_inact_config()
798 	ret = adxl380_set_measure_en(st, false);  in adxl380_act_inact_config()
802 	ret = adxl380_write_act_inact_en(st, type, en);  in adxl380_act_inact_config()
806 	ret = adxl380_write_act_inact_int(st, type, en);  in adxl380_act_inact_config()
810 	return adxl380_set_measure_en(st, true);  in adxl380_act_inact_config()
813 static int adxl380_write_tap_axis(struct adxl380_state *st,  in adxl380_write_tap_axis()  argument
818 	ret = regmap_update_bits(st->regmap, ADXL380_TAP_CFG_REG,  in adxl380_write_tap_axis()
825 	st->tap_axis_en = axis;  in adxl380_write_tap_axis()
830 static int adxl380_read_tap_int(struct adxl380_state *st, enum adxl380_tap_type type, bool *en)  in adxl380_read_tap_int()  argument
835 	ret = regmap_read(st->regmap, st->int_map[1], &reg_val);  in adxl380_read_tap_int()
847 static int adxl380_write_tap_int(struct adxl380_state *st, enum adxl380_tap_type type, bool en)  in adxl380_write_tap_int()  argument
850 		return regmap_update_bits(st->regmap, st->int_map[1],  in adxl380_write_tap_int()
854 	return regmap_update_bits(st->regmap, st->int_map[1],  in adxl380_write_tap_int()
859 static int adxl380_tap_config(struct adxl380_state *st,  in adxl380_tap_config()  argument
866 	guard(mutex)(&st->lock);  in adxl380_tap_config()
868 	ret = adxl380_set_measure_en(st, false);  in adxl380_tap_config()
872 	ret = adxl380_write_tap_axis(st, axis);  in adxl380_tap_config()
876 	ret = adxl380_write_tap_int(st, type, en);  in adxl380_tap_config()
880 	return adxl380_set_measure_en(st, true);  in adxl380_tap_config()
883 static int adxl380_set_fifo_samples(struct adxl380_state *st)  in adxl380_set_fifo_samples()  argument
886 	u16 fifo_samples = st->watermark * st->fifo_set_size;  in adxl380_set_fifo_samples()
888 	ret = regmap_update_bits(st->regmap, ADXL380_FIFO_CONFIG_0_REG,  in adxl380_set_fifo_samples()
895 	return regmap_write(st->regmap, ADXL380_FIFO_CONFIG_1_REG,  in adxl380_set_fifo_samples()
899 static int adxl380_get_status(struct adxl380_state *st, u8 *status0, u8 *status1)  in adxl380_get_status()  argument
904 	ret = regmap_bulk_read(st->regmap, ADXL380_STATUS_0_REG,  in adxl380_get_status()
905 			       &st->transf_buf, 2);  in adxl380_get_status()
909 	*status0 = st->transf_buf[0];  in adxl380_get_status()
910 	*status1 = st->transf_buf[1];  in adxl380_get_status()
915 static int adxl380_get_fifo_entries(struct adxl380_state *st, u16 *fifo_entries)  in adxl380_get_fifo_entries()  argument
919 	ret = regmap_bulk_read(st->regmap, ADXL380_FIFO_STATUS_0_REG,  in adxl380_get_fifo_entries()
920 			       &st->transf_buf, 2);  in adxl380_get_fifo_entries()
924 	*fifo_entries = st->transf_buf[0] | ((BIT(0) & st->transf_buf[1]) << 8);  in adxl380_get_fifo_entries()
959 	struct adxl380_state *st = iio_priv(indio_dev);  in adxl380_irq_handler()  local
965 	guard(mutex)(&st->lock);  in adxl380_irq_handler()
967 	ret = adxl380_get_status(st, &status0, &status1);  in adxl380_irq_handler()
976 	ret = adxl380_get_fifo_entries(st, &fifo_entries);  in adxl380_irq_handler()
980 	for (i = 0; i < fifo_entries; i += st->fifo_set_size) {  in adxl380_irq_handler()
981 		ret = regmap_noinc_read(st->regmap, ADXL380_FIFO_DATA,  in adxl380_irq_handler()
982 					&st->fifo_buf[i],  in adxl380_irq_handler()
983 					2 * st->fifo_set_size);  in adxl380_irq_handler()
986 		iio_push_to_buffers(indio_dev, &st->fifo_buf[i]);  in adxl380_irq_handler()
992 static int adxl380_write_calibbias_value(struct adxl380_state *st,  in adxl380_write_calibbias_value()  argument
998 	guard(mutex)(&st->lock);  in adxl380_write_calibbias_value()
1000 	ret = adxl380_set_measure_en(st, false);  in adxl380_write_calibbias_value()
1004 	ret = regmap_write(st->regmap, ADXL380_X_DSM_OFFSET_REG + chan_addr, calibbias);  in adxl380_write_calibbias_value()
1008 	return adxl380_set_measure_en(st, true);  in adxl380_write_calibbias_value()
1011 static int adxl380_read_calibbias_value(struct adxl380_state *st,  in adxl380_read_calibbias_value()  argument
1018 	guard(mutex)(&st->lock);  in adxl380_read_calibbias_value()
1020 	ret = regmap_read(st->regmap, ADXL380_X_DSM_OFFSET_REG + chan_addr, &reg_val);  in adxl380_read_calibbias_value()
1033 	return sysfs_emit(buf, "1\n");  in hwfifo_watermark_min_show()
1048 	struct adxl380_state *st = iio_priv(indio_dev);  in adxl380_get_fifo_watermark()  local
1050 	return sysfs_emit(buf, "%d\n", st->watermark);  in adxl380_get_fifo_watermark()
1058 	struct adxl380_state *st = iio_priv(indio_dev);  in adxl380_get_fifo_enabled()  local
1062 	ret = regmap_read(st->regmap, ADXL380_DIG_EN_REG, &reg_val);  in adxl380_get_fifo_enabled()
1087 	struct adxl380_state *st = iio_priv(indio_dev);  in adxl380_buffer_postenable()  local
1091 	guard(mutex)(&st->lock);  in adxl380_buffer_postenable()
1093 	ret = adxl380_set_measure_en(st, false);  in adxl380_buffer_postenable()
1097 	ret = regmap_update_bits(st->regmap,  in adxl380_buffer_postenable()
1098 				 st->int_map[0],  in adxl380_buffer_postenable()
1100 				 FIELD_PREP(ADXL380_INT_MAP0_FIFO_WM_INT0_MSK, 1));  in adxl380_buffer_postenable()
1105 		ret = regmap_update_bits(st->regmap, ADXL380_DIG_EN_REG,  in adxl380_buffer_postenable()
1112 	st->fifo_set_size = bitmap_weight(indio_dev->active_scan_mask,  in adxl380_buffer_postenable()
1115 	if ((st->watermark * st->fifo_set_size) > ADXL380_FIFO_SAMPLES)  in adxl380_buffer_postenable()
1116 		st->watermark = (ADXL380_FIFO_SAMPLES  / st->fifo_set_size);  in adxl380_buffer_postenable()
1118 	ret = adxl380_set_fifo_samples(st);  in adxl380_buffer_postenable()
1122 	ret = regmap_update_bits(st->regmap, ADXL380_DIG_EN_REG, ADXL380_FIFO_EN_MSK,  in adxl380_buffer_postenable()
1123 				 FIELD_PREP(ADXL380_FIFO_EN_MSK, 1));  in adxl380_buffer_postenable()
1127 	return adxl380_set_measure_en(st, true);  in adxl380_buffer_postenable()
1132 	struct adxl380_state *st = iio_priv(indio_dev);  in adxl380_buffer_predisable()  local
1135 	guard(mutex)(&st->lock);  in adxl380_buffer_predisable()
1137 	ret = adxl380_set_measure_en(st, false);  in adxl380_buffer_predisable()
1141 	ret = regmap_update_bits(st->regmap,  in adxl380_buffer_predisable()
1142 				 st->int_map[0],  in adxl380_buffer_predisable()
1149 		ret = regmap_update_bits(st->regmap, ADXL380_DIG_EN_REG,  in adxl380_buffer_predisable()
1151 					 1 << (4 + i));  in adxl380_buffer_predisable()
1156 	ret = regmap_update_bits(st->regmap, ADXL380_DIG_EN_REG, ADXL380_FIFO_EN_MSK,  in adxl380_buffer_predisable()
1161 	return adxl380_set_measure_en(st, true);  in adxl380_buffer_predisable()
1173 	struct adxl380_state *st = iio_priv(indio_dev);  in adxl380_read_raw()  local
1182 		ret = adxl380_read_chn(st, chan->address);  in adxl380_read_raw()
1188 				     chan->scan_type.realbits - 1);  in adxl380_read_raw()
1193 			scoped_guard(mutex, &st->lock) {  in adxl380_read_raw()
1194 				*val = st->chip_info->scale_tbl[st->range][0];  in adxl380_read_raw()
1195 				*val2 = st->chip_info->scale_tbl[st->range][1];  in adxl380_read_raw()
1209 			*val = st->chip_info->temp_offset;  in adxl380_read_raw()
1217 			ret = adxl380_read_calibbias_value(st, chan->scan_index, val);  in adxl380_read_raw()
1225 		ret = adxl380_get_odr(st, val);  in adxl380_read_raw()
1230 		ret =  adxl380_get_lpf(st, val);  in adxl380_read_raw()
1235 		ret =  adxl380_get_hpf(st, val, val2);  in adxl380_read_raw()
1249 	struct adxl380_state *st = iio_priv(indio_dev);  in adxl380_read_avail()  local
1256 		*vals = (const int *)st->chip_info->scale_tbl;  in adxl380_read_avail()
1258 		*length = ARRAY_SIZE(st->chip_info->scale_tbl) * 2;  in adxl380_read_avail()
1261 		*vals = (const int *)st->chip_info->samp_freq_tbl;  in adxl380_read_avail()
1263 		*length = ARRAY_SIZE(st->chip_info->samp_freq_tbl);  in adxl380_read_avail()
1266 		*vals = (const int *)st->lpf_tbl;  in adxl380_read_avail()
1268 		*length = ARRAY_SIZE(st->lpf_tbl);  in adxl380_read_avail()
1271 		*vals = (const int *)st->hpf_tbl;  in adxl380_read_avail()
1274 		*length = ARRAY_SIZE(st->hpf_tbl) * 2;  in adxl380_read_avail()
1285 	struct adxl380_state *st = iio_priv(indio_dev);  in adxl380_write_raw()  local
1290 		odr_index = adxl380_find_match_1d_tbl(st->chip_info->samp_freq_tbl,  in adxl380_write_raw()
1291 						      ARRAY_SIZE(st->chip_info->samp_freq_tbl),  in adxl380_write_raw()
1293 		return adxl380_set_odr(st, odr_index);  in adxl380_write_raw()
1295 		return adxl380_write_calibbias_value(st, chan->scan_index, val);  in adxl380_write_raw()
1297 		lpf_index = adxl380_find_match_1d_tbl(st->lpf_tbl,  in adxl380_write_raw()
1298 						      ARRAY_SIZE(st->lpf_tbl),  in adxl380_write_raw()
1300 		return adxl380_set_lpf(st, lpf_index);  in adxl380_write_raw()
1302 		hpf_index = adxl380_find_match_2d_tbl(st->hpf_tbl,  in adxl380_write_raw()
1303 						      ARRAY_SIZE(st->hpf_tbl),  in adxl380_write_raw()
1307 		return adxl380_set_hpf(st, hpf_index);  in adxl380_write_raw()
1309 		range_index = adxl380_find_match_2d_tbl(st->chip_info->scale_tbl,  in adxl380_write_raw()
1310 							ARRAY_SIZE(st->chip_info->scale_tbl),  in adxl380_write_raw()
1314 		return adxl380_set_range(st, range_index);  in adxl380_write_raw()
1340 	struct adxl380_state *st = iio_priv(indio_dev);  in adxl380_read_event_config()  local
1347 		tap_axis_en = st->tap_axis_en == ADXL380_X_AXIS;  in adxl380_read_event_config()
1350 		tap_axis_en = st->tap_axis_en == ADXL380_Y_AXIS;  in adxl380_read_event_config()
1353 		tap_axis_en = st->tap_axis_en == ADXL380_Z_AXIS;  in adxl380_read_event_config()
1361 		ret = adxl380_read_act_inact_int(st, ADXL380_ACTIVITY, &int_en);  in adxl380_read_event_config()
1366 		ret = adxl380_read_act_inact_int(st, ADXL380_INACTIVITY, &int_en);  in adxl380_read_event_config()
1371 		ret = adxl380_read_tap_int(st, ADXL380_SINGLE_TAP, &int_en);  in adxl380_read_event_config()
1376 		ret = adxl380_read_tap_int(st, ADXL380_DOUBLE_TAP, &int_en);  in adxl380_read_event_config()
1391 	struct adxl380_state *st = iio_priv(indio_dev);  in adxl380_write_event_config()  local
1410 		return adxl380_act_inact_config(st, ADXL380_ACTIVITY, state);  in adxl380_write_event_config()
1412 		return adxl380_act_inact_config(st, ADXL380_INACTIVITY, state);  in adxl380_write_event_config()
1414 		return adxl380_tap_config(st, axis, ADXL380_SINGLE_TAP, state);  in adxl380_write_event_config()
1416 		return adxl380_tap_config(st, axis, ADXL380_DOUBLE_TAP, state);  in adxl380_write_event_config()
1429 	struct adxl380_state *st = iio_priv(indio_dev);  in adxl380_read_event_value()  local
1431 	guard(mutex)(&st->lock);  in adxl380_read_event_value()
1439 				*val = st->act_threshold;  in adxl380_read_event_value()
1442 				*val = st->inact_threshold;  in adxl380_read_event_value()
1451 				*val = st->act_time_ms;  in adxl380_read_event_value()
1455 				*val = st->inact_time_ms;  in adxl380_read_event_value()
1467 			*val = st->tap_threshold;  in adxl380_read_event_value()
1470 			*val = st->tap_window_us;  in adxl380_read_event_value()
1474 			*val = st->tap_latent_us;  in adxl380_read_event_value()
1490 	struct adxl380_state *st = iio_priv(indio_dev);  in adxl380_write_event_value()  local
1514 				return adxl380_set_act_inact_time_ms(st,  in adxl380_write_event_value()
1517 				return adxl380_set_act_inact_time_ms(st,  in adxl380_write_event_value()
1532 			return adxl380_write_tap_time_us(st,  in adxl380_write_event_value()
1537 			return adxl380_write_tap_time_us(st,  in adxl380_write_event_value()
1554 	struct adxl380_state *st = iio_priv(indio_dev);  in in_accel_gesture_tap_maxtomin_time_show()  local
1556 	guard(mutex)(&st->lock);  in in_accel_gesture_tap_maxtomin_time_show()
1558 	vals[0] = st->tap_duration_us;  in in_accel_gesture_tap_maxtomin_time_show()
1559 	vals[1] = MICRO;  in in_accel_gesture_tap_maxtomin_time_show()
1569 	struct adxl380_state *st = iio_priv(indio_dev);  in in_accel_gesture_tap_maxtomin_time_store()  local
1572 	guard(mutex)(&st->lock);  in in_accel_gesture_tap_maxtomin_time_store()
1605 	struct adxl380_state *st = iio_priv(indio_dev);  in adxl380_reg_access()  local
1608 		return regmap_read(st->regmap, reg, readval);  in adxl380_reg_access()
1610 	return regmap_write(st->regmap, reg, writeval);  in adxl380_reg_access()
1615 	struct adxl380_state *st  = iio_priv(indio_dev);  in adxl380_set_watermark()  local
1617 	st->watermark = min(val, ADXL380_FIFO_SAMPLES);  in adxl380_set_watermark()
1671 	.modified = 1,							\
1699 	ADXL380_ACCEL_CHANNEL(1, ADXL380_Y_DATA_H_REG, Y),
1720 	struct adxl380_state *st = iio_priv(indio_dev);  in adxl380_config_irq()  local
1727 	st->irq = fwnode_irq_get_byname(dev_fwnode(st->dev), "INT0");  in adxl380_config_irq()
1728 	if (st->irq > 0) {  in adxl380_config_irq()
1729 		st->int_map[0] = ADXL380_INT0_MAP0_REG;  in adxl380_config_irq()
1730 		st->int_map[1] = ADXL380_INT0_MAP1_REG;  in adxl380_config_irq()
1732 		st->irq = fwnode_irq_get_byname(dev_fwnode(st->dev), "INT1");  in adxl380_config_irq()
1733 		if (st->irq > 0)  in adxl380_config_irq()
1734 			return dev_err_probe(st->dev, -ENODEV,  in adxl380_config_irq()
1736 		st->int_map[0] = ADXL380_INT1_MAP0_REG;  in adxl380_config_irq()
1737 		st->int_map[1] = ADXL380_INT1_MAP1_REG;  in adxl380_config_irq()
1740 	desc = irq_get_irq_data(st->irq);  in adxl380_config_irq()
1742 		return dev_err_probe(st->dev, -EINVAL, "Could not find IRQ %d\n", st->irq);  in adxl380_config_irq()
1749 		polarity = 1;  in adxl380_config_irq()
1752 		return dev_err_probe(st->dev, -EINVAL,  in adxl380_config_irq()
1757 	ret = regmap_update_bits(st->regmap, ADXL380_INT0_REG,  in adxl380_config_irq()
1763 	return devm_request_threaded_irq(st->dev, st->irq, NULL,  in adxl380_config_irq()
1773 	struct adxl380_state *st = iio_priv(indio_dev);  in adxl380_setup()  local
1775 	ret = regmap_read(st->regmap, ADXL380_DEVID_AD_REG, &reg_val);  in adxl380_setup()
1780 		dev_warn(st->dev, "Unknown chip id %x\n", reg_val);  in adxl380_setup()
1782 	ret = regmap_bulk_read(st->regmap, ADLX380_PART_ID_REG,  in adxl380_setup()
1783 			       &st->transf_buf, 2);  in adxl380_setup()
1787 	part_id = get_unaligned_be16(st->transf_buf);  in adxl380_setup()
1791 		dev_warn(st->dev, "Unknown part id %x\n", part_id);  in adxl380_setup()
1793 	ret = regmap_read(st->regmap, ADXL380_MISC_0_REG, &reg_val);  in adxl380_setup()
1803 	if (chip_id != st->chip_info->chip_id)  in adxl380_setup()
1804 		dev_warn(st->dev, "Unknown chip id %x\n", chip_id);  in adxl380_setup()
1806 	ret = regmap_write(st->regmap, ADXL380_RESET_REG, ADXL380_RESET_CODE);  in adxl380_setup()
1817 		ret = regmap_update_bits(st->regmap, ADXL380_DIG_EN_REG,  in adxl380_setup()
1819 					 1 << (4 + i));  in adxl380_setup()
1824 	ret = regmap_update_bits(st->regmap, ADXL380_FIFO_CONFIG_0_REG,  in adxl380_setup()
1831 	ret = regmap_update_bits(st->regmap, ADXL380_SNSR_AXIS_EN_REG,  in adxl380_setup()
1842 	ret = adxl380_fill_lpf_tbl(st);  in adxl380_setup()
1846 	ret = adxl380_fill_hpf_tbl(st);  in adxl380_setup()
1850 	return adxl380_set_measure_en(st, true);  in adxl380_setup()
1857 	struct adxl380_state *st;  in adxl380_probe()  local
1860 	indio_dev = devm_iio_device_alloc(dev, sizeof(*st));  in adxl380_probe()
1864 	st = iio_priv(indio_dev);  in adxl380_probe()
1866 	st->dev = dev;  in adxl380_probe()
1867 	st->regmap = regmap;  in adxl380_probe()
1868 	st->chip_info = chip_info;  in adxl380_probe()
1870 	mutex_init(&st->lock);  in adxl380_probe()
1880 		return dev_err_probe(st->dev, ret,  in adxl380_probe()
1883 	ret = devm_regulator_get_enable(st->dev, "vsupply");  in adxl380_probe()
1885 		return dev_err_probe(st->dev, ret,  in adxl380_probe()
1892 	ret = devm_iio_kfifo_buffer_setup_ext(st->dev, indio_dev,  in adxl380_probe()