/linux/arch/arm64/boot/dts/ti/ |
H A D | k3-am62.dtsi | 55 ranges = <0x00 0x000f0000 0x00 0x000f0000 0x00 0x00030000>, /* Main MMRs */ 56 <0x00 0x00420000 0x00 0x00420000 0x00 0x00001000>, /* ESM0 */ 57 <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */ 58 <0x00 0x00703000 0x00 0x00703000 0x00 0x00000200>, /* USB0 debug trace */ 59 <0x00 0x0070c000 0x00 0x0070c000 0x00 0x00000200>, /* USB1 debug trace */ 60 <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* Timesync router */ 61 <0x00 0x01000000 0x00 0x01000000 0x00 0x01b28400>, /* First peripheral window */ 62 <0x00 0x08000000 0x00 0x08000000 0x00 0x00200000>, /* Main CPSW */ 63 <0x00 0x0e000000 0x00 0x0e000000 0x00 0x01d20000>, /* Second peripheral window */ 64 <0x00 0x0fd00000 0x00 0x0fd00000 0x00 0x00020000>, /* GPU */ [all …]
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H A D | k3-am62p.dtsi | 53 ranges = <0x00 0x000f0000 0x00 0x000f0000 0x00 0x00030000>, /* Main MMRs */ 54 <0x00 0x00420000 0x00 0x00420000 0x00 0x00001000>, /* ESM0 */ 55 <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */ 56 <0x00 0x00703000 0x00 0x00703000 0x00 0x00000200>, /* USB0 debug trace */ 57 <0x00 0x0070c000 0x00 0x0070c000 0x00 0x00000200>, /* USB1 debug trace */ 58 <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* Timesync router */ 59 <0x00 0x01000000 0x00 0x01000000 0x00 0x01b28400>, /* First peripheral window */ 60 <0x00 0x08000000 0x00 0x08000000 0x00 0x00200000>, /* Main CPSW */ 61 <0x00 0x0e000000 0x00 0x0e000000 0x00 0x01d20000>, /* Second peripheral window */ 62 <0x00 0x0fd00000 0x00 0x0fd00000 0x00 0x00020000>, /* GPU */ [all …]
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H A D | k3-am62a.dtsi | 54 ranges = <0x00 0x000f0000 0x00 0x000f0000 0x00 0x00030000>, /* Main MMRs */ 55 <0x00 0x00420000 0x00 0x00420000 0x00 0x00001000>, /* ESM0 */ 56 <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */ 57 <0x00 0x00703000 0x00 0x00703000 0x00 0x00000200>, /* USB0 debug trace */ 58 <0x00 0x0070c000 0x00 0x0070c000 0x00 0x00000200>, /* USB1 debug trace */ 59 <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* Timesync router */ 60 <0x00 0x01000000 0x00 0x01000000 0x00 0x01b28400>, /* First peripheral window */ 61 <0x00 0x08000000 0x00 0x08000000 0x00 0x00200000>, /* Main CPSW */ 62 <0x00 0x0e000000 0x00 0x0e000000 0x00 0x01d20000>, /* Second peripheral window */ 63 <0x00 0x0fd00000 0x00 0x0fd00000 0x00 0x00020000>, /* GPU */ [all …]
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H A D | k3-j722s.dtsi | 24 #size-cells = <0>; 46 cpu0: cpu@0 { 48 reg = <0x000>; 51 i-cache-size = <0x8000>; 54 d-cache-size = <0x8000>; 58 clocks = <&k3_clks 135 0>; 63 reg = <0x001>; 66 i-cache-size = <0x8000>; 69 d-cache-size = <0x8000>; 73 clocks = <&k3_clks 136 0>; [all …]
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H A D | k3-am65-mcu.dtsi | 13 ranges = <0x0 0x0 0x40f00000 0x20000>; 17 reg = <0x200 0x8>; 22 reg = <0x4040 0x4>; 30 reg = <0x0 0x40f04200 0x0 0x10>; 33 pinctrl-single,function-mask = <0x00000101>; 39 reg = <0x0 0x40f04280 0x0 0x8>; 42 pinctrl-single,function-mask = <0x00000003>; 47 reg = <0x00 0x40a00000 0x00 0x100>; 56 reg = <0x00 0x41c00000 0x00 0x80000>; 57 ranges = <0x0 0x00 0x41c00000 0x80000>; [all …]
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H A D | k3-j721e-mcu-wakeup.dtsi | 19 reg = <0x00 0x44083000 0x0 0x1000>; 44 ranges = <0x0 0x0 0x40f00000 0x20000>; 48 reg = <0x200 0x8>; 53 reg = <0x4040 0x4>; 62 ranges = <0x0 0x00 0x43000000 0x20000>; 66 reg = <0x14 0x4>; 73 /* Proxy 0 addressing */ 74 reg = <0x00 0x4301c000 0x00 0x178>; 77 pinctrl-single,function-mask = <0xffffffff>; 83 reg = <0x00 0x40f04200 0x00 0x28>; [all …]
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H A D | k3-j721s2-mcu-wakeup.dtsi | 19 reg = <0x00 0x44083000 0x00 0x1000>; 44 ranges = <0x0 0x00 0x43000000 0x20000>; 48 reg = <0x14 0x4>; 57 reg = <0x00 0x43600000 0x00 0x10000>, 58 <0x00 0x44880000 0x00 0x20000>, 59 <0x00 0x44860000 0x00 0x20000>; 72 reg = <0x00 0x41c00000 0x00 0x100000>; 73 ranges = <0x00 0x00 0x41c00000 0x100000>; 80 /* Proxy 0 addressing */ 81 reg = <0x00 0x4301c000 0x00 0x034>; [all …]
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/linux/Documentation/devicetree/bindings/display/ |
H A D | arm,hdlcd.yaml | 64 reg = <0x2b000000 0x1000>; 65 interrupts = <0 85 4>; 78 #size-cells = <0>; 81 reg = <0x70>;
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/linux/drivers/gpu/drm/amd/include/asic_reg/nbio/ |
H A D | nbio_7_0_default.h | 26 #define cfgNB_NBCFG0_NB_VENDOR_ID_DEFAULT 0x00000000 27 #define cfgNB_NBCFG0_NB_DEVICE_ID_DEFAULT 0x00000000 28 #define cfgNB_NBCFG0_NB_COMMAND_DEFAULT 0x00000000 29 #define cfgNB_NBCFG0_NB_STATUS_DEFAULT 0x00000000 30 #define cfgNB_NBCFG0_NB_REVISION_ID_DEFAULT 0x00000000 31 #define cfgNB_NBCFG0_NB_REGPROG_INF_DEFAULT 0x00000000 32 #define cfgNB_NBCFG0_NB_SUB_CLASS_DEFAULT 0x00000000 33 #define cfgNB_NBCFG0_NB_BASE_CODE_DEFAULT 0x00000000 34 #define cfgNB_NBCFG0_NB_CACHE_LINE_DEFAULT 0x00000000 35 #define cfgNB_NBCFG0_NB_LATENCY_DEFAULT 0x00000000 [all …]
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H A D | nbio_2_3_default.h | 26 #define mmBIF_BX_PF_MM_INDEX_DEFAULT 0x00000000 27 #define mmBIF_BX_PF_MM_DATA_DEFAULT 0x00000000 28 #define mmBIF_BX_PF_MM_INDEX_HI_DEFAULT 0x00000000 32 #define mmSYSHUB_INDEX_OVLP_DEFAULT 0x00000000 33 #define mmSYSHUB_DATA_OVLP_DEFAULT 0x00000000 34 #define mmPCIE_INDEX_DEFAULT 0x00000000 35 #define mmPCIE_DATA_DEFAULT 0x00000000 36 #define mmPCIE_INDEX2_DEFAULT 0x00000000 37 #define mmPCIE_DATA2_DEFAULT 0x00000000 38 #define mmSBIOS_SCRATCH_0_DEFAULT 0x00000000 [all …]
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H A D | nbio_6_1_default.h | 26 #define cfgPSWUSCFG0_VENDOR_ID_DEFAULT 0x00000000 27 #define cfgPSWUSCFG0_DEVICE_ID_DEFAULT 0x00000000 28 #define cfgPSWUSCFG0_COMMAND_DEFAULT 0x00000000 29 #define cfgPSWUSCFG0_STATUS_DEFAULT 0x00000000 30 #define cfgPSWUSCFG0_REVISION_ID_DEFAULT 0x00000000 31 #define cfgPSWUSCFG0_PROG_INTERFACE_DEFAULT 0x00000000 32 #define cfgPSWUSCFG0_SUB_CLASS_DEFAULT 0x00000000 33 #define cfgPSWUSCFG0_BASE_CLASS_DEFAULT 0x00000000 34 #define cfgPSWUSCFG0_CACHE_LINE_DEFAULT 0x00000000 35 #define cfgPSWUSCFG0_LATENCY_DEFAULT 0x00000000 [all …]
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/linux/arch/arm/boot/dts/arm/ |
H A D | vexpress-v2p-ca15-tc1.dts | 16 arm,hbi = <0x237>; 17 arm,vexpress,site = <0xf>; 36 #size-cells = <0>; 38 cpu@0 { 41 reg = <0>; 53 reg = <0 0x80000000 0 0x40000000>; 61 /* Chipselect 2 is physically at 0x18000000 */ 65 reg = <0 0x18000000 0 0x00800000>; 72 reg = <0 0x2b000000 0 0x1000>; 73 interrupts = <0 85 4>; [all …]
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H A D | vexpress-v2p-ca15_a7.dts | 16 arm,hbi = <0x249>; 17 arm,vexpress,site = <0xf>; 36 #size-cells = <0>; 38 cpu0: cpu@0 { 41 reg = <0>; 61 reg = <0x100>; 71 reg = <0x101>; 81 reg = <0x102>; 109 reg = <0 0x80000000 0 0x40000000>; 117 /* Chipselect 2 is physically at 0x18000000 */ [all …]
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/linux/arch/hexagon/kernel/ |
H A D | vm_init_segtable.S | 16 * Start with mapping PA=0 to both VA=0x0 and VA=0xc000000 as 16MB large pages. 46 /* VA 0x00000000 */ 59 /* VA 0x40000000 */ 68 /* VA 0x80000000 */ 74 /*0xa8*/.word X,X,X,X 77 /*0xa9*/.word BKPG_IO(0xa9000000),BKPG_IO(0xa9000000),BKPG_IO(0xa9000000),BKPG_IO(0xa9000000) 79 /*0xa9*/.word X,X,X,X 81 /*0xaa*/.word X,X,X,X 82 /*0xab*/.word X,X,X,X 83 /*0xac*/.word X,X,X,X [all …]
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/linux/crypto/ |
H A D | aes_generic.c | 67 0xa56363c6, 0x847c7cf8, 0x997777ee, 0x8d7b7bf6, 68 0x0df2f2ff, 0xbd6b6bd6, 0xb16f6fde, 0x54c5c591, 69 0x50303060, 0x03010102, 0xa96767ce, 0x7d2b2b56, 70 0x19fefee7, 0x62d7d7b5, 0xe6abab4d, 0x9a7676ec, 71 0x45caca8f, 0x9d82821f, 0x40c9c989, 0x877d7dfa, 72 0x15fafaef, 0xeb5959b2, 0xc947478e, 0x0bf0f0fb, 73 0xecadad41, 0x67d4d4b3, 0xfda2a25f, 0xeaafaf45, 74 0xbf9c9c23, 0xf7a4a453, 0x967272e4, 0x5bc0c09b, 75 0xc2b7b775, 0x1cfdfde1, 0xae93933d, 0x6a26264c, 76 0x5a36366c, 0x413f3f7e, 0x02f7f7f5, 0x4fcccc83, [all …]
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/linux/arch/riscv/boot/dts/starfive/ |
H A D | jh7110.dtsi | 20 #size-cells = <0>; 22 S7_0: cpu@0 { 24 reg = <0>; 200 cpu_opp: opp-table-0 { 260 #clock-cells = <0>; 265 #clock-cells = <0>; 271 #clock-cells = <0>; 277 #clock-cells = <0>; 283 #clock-cells = <0>; 289 #clock-cells = <0>; [all …]
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