Lines Matching +full:0 +full:x2b000000
19 reg = <0x00 0x44083000 0x00 0x1000>;
44 ranges = <0x0 0x00 0x43000000 0x20000>;
48 reg = <0x14 0x4>;
57 reg = <0x00 0x43600000 0x00 0x10000>,
58 <0x00 0x44880000 0x00 0x20000>,
59 <0x00 0x44860000 0x00 0x20000>;
72 reg = <0x00 0x41c00000 0x00 0x100000>;
73 ranges = <0x00 0x00 0x41c00000 0x100000>;
80 /* Proxy 0 addressing */
81 reg = <0x00 0x4301c000 0x00 0x034>;
84 pinctrl-single,function-mask = <0xffffffff>;
89 /* Proxy 0 addressing */
90 reg = <0x00 0x4301c038 0x00 0x02C>;
93 pinctrl-single,function-mask = <0xffffffff>;
98 /* Proxy 0 addressing */
99 reg = <0x00 0x4301c068 0x00 0x120>;
102 pinctrl-single,function-mask = <0xffffffff>;
107 /* Proxy 0 addressing */
108 reg = <0x00 0x4301c190 0x00 0x004>;
111 pinctrl-single,function-mask = <0xffffffff>;
117 reg = <0x00 0x40f04200 0x00 0x28>;
120 pinctrl-single,function-mask = <0x0000000f>;
128 reg = <0x00 0x40f04280 0x00 0x28>;
131 pinctrl-single,function-mask = <0x0000000f>;
138 reg = <0x00 0x42200000 0x00 0x400>;
152 ranges = <0x0 0x0 0x40f00000 0x20000>;
156 reg = <0x200 0x8>;
161 reg = <0x4040 0x4>;
169 reg = <0x00 0x40400000 0x00 0x400>;
184 reg = <0x00 0x40410000 0x00 0x400>;
198 reg = <0x00 0x40420000 0x00 0x400>;
212 reg = <0x00 0x40430000 0x00 0x400>;
226 reg = <0x00 0x40440000 0x00 0x400>;
240 reg = <0x00 0x40450000 0x00 0x400>;
254 reg = <0x00 0x40460000 0x00 0x400>;
268 reg = <0x00 0x40470000 0x00 0x400>;
282 reg = <0x00 0x40480000 0x00 0x400>;
296 reg = <0x00 0x40490000 0x00 0x400>;
310 reg = <0x00 0x42300000 0x00 0x200>;
320 reg = <0x00 0x40a00000 0x00 0x200>;
330 reg = <0x00 0x42110000 0x00 0x100>;
338 ti,davinci-gpio-unbanked = <0>;
340 clocks = <&k3_clks 115 0>;
347 reg = <0x00 0x42100000 0x00 0x100>;
355 ti,davinci-gpio-unbanked = <0>;
357 clocks = <&k3_clks 116 0>;
364 reg = <0x00 0x42120000 0x00 0x100>;
367 #size-cells = <0>;
377 reg = <0x00 0x40b00000 0x00 0x100>;
380 #size-cells = <0>;
389 reg = <0x00 0x40b10000 0x00 0x100>;
392 #size-cells = <0>;
401 reg = <0x00 0x40528000 0x00 0x200>,
402 <0x00 0x40500000 0x00 0x8000>;
405 clocks = <&k3_clks 207 0>, <&k3_clks 207 1>;
410 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
416 reg = <0x00 0x40568000 0x00 0x200>,
417 <0x00 0x40540000 0x00 0x8000>;
420 clocks = <&k3_clks 208 0>, <&k3_clks 208 1>;
425 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
431 reg = <0x00 0x040300000 0x00 0x400>;
434 #size-cells = <0>;
442 reg = <0x00 0x040310000 0x00 0x400>;
445 #size-cells = <0>;
453 reg = <0x00 0x040320000 0x00 0x400>;
456 #size-cells = <0>;
466 ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>;
474 reg = <0x0 0x2b800000 0x0 0x400000>,
475 <0x0 0x2b000000 0x0 0x400000>,
476 <0x0 0x28590000 0x0 0x100>,
477 <0x0 0x2a500000 0x0 0x40000>,
478 <0x0 0x28440000 0x0 0x40000>;
482 ti,sci-rm-range-gp-rings = <0x1>;
490 reg = <0x0 0x285c0000 0x0 0x100>,
491 <0x0 0x2a800000 0x0 0x40000>,
492 <0x0 0x2aa00000 0x0 0x40000>,
493 <0x0 0x284a0000 0x0 0x4000>,
494 <0x0 0x284c0000 0x0 0x4000>,
495 <0x0 0x28400000 0x0 0x2000>;
505 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
506 <0x0f>; /* TX_HCHAN */
507 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
508 <0x0b>; /* RX_HCHAN */
509 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
517 reg = <0x00 0x2a480000 0x00 0x80000>,
518 <0x00 0x2a380000 0x00 0x80000>,
519 <0x00 0x2a400000 0x00 0x80000>;
534 reg = <0x0 0x46000000 0x0 0x200000>;
536 ranges = <0x0 0x0 0x0 0x46000000 0x0 0x200000>;
542 dmas = <&mcu_udmap 0xf000>,
543 <&mcu_udmap 0xf001>,
544 <&mcu_udmap 0xf002>,
545 <&mcu_udmap 0xf003>,
546 <&mcu_udmap 0xf004>,
547 <&mcu_udmap 0xf005>,
548 <&mcu_udmap 0xf006>,
549 <&mcu_udmap 0xf007>,
550 <&mcu_udmap 0x7000>;
557 #size-cells = <0>;
563 ti,syscon-efuse = <&cpsw_mac_syscon 0x0>;
570 reg = <0x0 0xf00 0x0 0x100>;
572 #size-cells = <0>;
580 reg = <0x0 0x3d000 0x0 0x400>;
594 reg = <0x00 0x40200000 0x00 0x1000>;
596 power-domains = <&k3_pds 0 TI_SCI_PD_EXCLUSIVE>;
597 clocks = <&k3_clks 0 0>;
598 assigned-clocks = <&k3_clks 0 2>;
601 dmas = <&main_udmap 0x7400>,
602 <&main_udmap 0x7401>;
614 reg = <0x00 0x40210000 0x00 0x1000>;
617 clocks = <&k3_clks 1 0>;
621 dmas = <&main_udmap 0x7402>,
622 <&main_udmap 0x7403>;
636 ranges = <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>,
637 <0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>,
638 <0x04 0x00000000 0x04 0x00000000 0x04 0x00000000>;
642 reg = <0x00 0x47040000 0x00 0x100>,
643 <0x05 0x00000000 0x01 0x00000000>;
647 cdns,trigger-address = <0x0>;
654 #size-cells = <0>;
661 reg = <0x00 0x47050000 0x00 0x100>,
662 <0x07 0x00000000 0x01 0x00000000>;
666 cdns,trigger-address = <0x0>;
670 #size-cells = <0>;
678 reg = <0x00 0x42040000 0x0 0x350>,
679 <0x00 0x42050000 0x0 0x350>;
690 ranges = <0x41000000 0x00 0x41000000 0x20000>,
691 <0x41400000 0x00 0x41400000 0x20000>;
696 reg = <0x41000000 0x00010000>,
697 <0x41010000 0x00010000>;
701 ti,sci-proc-ids = <0x01 0xff>;
711 reg = <0x41400000 0x00010000>,
712 <0x41410000 0x00010000>;
716 ti,sci-proc-ids = <0x02 0xff>;
727 reg = <0x00 0x40800000 0x00 0x1000>;
734 reg = <0x00 0x42080000 0x00 0x1000>;
745 reg = <0x00 0x40600000 0x00 0x100>;
756 reg = <0x00 0x40610000 0x00 0x100>;