Lines Matching +full:0 +full:x2b000000
13 ranges = <0x0 0x0 0x40f00000 0x20000>;
17 reg = <0x200 0x8>;
22 reg = <0x4040 0x4>;
30 reg = <0x0 0x40f04200 0x0 0x10>;
33 pinctrl-single,function-mask = <0x00000101>;
39 reg = <0x0 0x40f04280 0x0 0x8>;
42 pinctrl-single,function-mask = <0x00000003>;
47 reg = <0x00 0x40a00000 0x00 0x100>;
56 reg = <0x00 0x41c00000 0x00 0x80000>;
57 ranges = <0x0 0x00 0x41c00000 0x80000>;
64 reg = <0x0 0x40b00000 0x0 0x100>;
67 #size-cells = <0>;
76 reg = <0x0 0x40300000 0x0 0x400>;
81 #size-cells = <0>;
87 reg = <0x0 0x40310000 0x0 0x400>;
92 #size-cells = <0>;
98 reg = <0x0 0x40320000 0x0 0x400>;
103 #size-cells = <0>;
109 reg = <0x0 0x40200000 0x0 0x1000>;
111 clocks = <&k3_clks 0 2>;
112 assigned-clocks = <&k3_clks 0 2>;
115 dmas = <&mcu_udmap 0x7100>,
116 <&mcu_udmap 0x7101 >;
128 reg = <0x0 0x40210000 0x0 0x1000>;
134 dmas = <&mcu_udmap 0x7102>,
135 <&mcu_udmap 0x7103>;
152 reg = <0x00 0x40400000 0x00 0x400>;
153 clocks = <&k3_clks 35 0>;
162 reg = <0x00 0x40410000 0x00 0x400>;
163 clocks = <&k3_clks 36 0>;
172 reg = <0x00 0x40420000 0x00 0x400>;
173 clocks = <&k3_clks 37 0>;
182 reg = <0x00 0x40430000 0x00 0x400>;
183 clocks = <&k3_clks 38 0>;
194 ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>;
202 reg = <0x0 0x2b800000 0x0 0x400000>,
203 <0x0 0x2b000000 0x0 0x400000>,
204 <0x0 0x28590000 0x0 0x100>,
205 <0x0 0x2a500000 0x0 0x40000>,
206 <0x0 0x28440000 0x0 0x40000>;
210 ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
218 reg = <0x0 0x285c0000 0x0 0x100>,
219 <0x0 0x2a800000 0x0 0x40000>,
220 <0x0 0x2aa00000 0x0 0x40000>,
221 <0x0 0x284a0000 0x0 0x4000>,
222 <0x0 0x284c0000 0x0 0x4000>,
223 <0x0 0x28400000 0x0 0x2000>;
233 ti,sci-rm-range-tchan = <0xf>, /* TX_HCHAN */
234 <0xd>; /* TX_CHAN */
235 ti,sci-rm-range-rchan = <0xb>, /* RX_HCHAN */
236 <0xa>; /* RX_CHAN */
237 ti,sci-rm-range-rflow = <0x0>; /* GP RFLOW */
245 reg = <0x0 0x2a480000 0x0 0x80000>,
246 <0x0 0x2a380000 0x0 0x80000>,
247 <0x0 0x2a400000 0x0 0x80000>;
258 reg = <0x0 0x40528000 0x0 0x400>,
259 <0x0 0x40500000 0x0 0x4400>;
262 clocks = <&k3_clks 102 5>, <&k3_clks 102 0>;
268 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
274 reg = <0x0 0x40568000 0x0 0x400>,
275 <0x0 0x40540000 0x0 0x4400>;
278 clocks = <&k3_clks 103 5>, <&k3_clks 103 0>;
284 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
292 ranges = <0x0 0x47000000 0x0 0x47000000 0x0 0x100>, /* FSS Control */
293 <0x0 0x47040000 0x0 0x47040000 0x0 0x100>, /* OSPI0 Control */
294 <0x0 0x47050000 0x0 0x47050000 0x0 0x100>, /* OSPI1 Control */
295 <0x0 0x50000000 0x0 0x50000000 0x0 0x10000000>, /* FSS data region 1 */
296 <0x4 0x00000000 0x4 0x00000000 0x4 0x00000000>; /* FSS data region 0/3 */
300 reg = <0x0 0x47040000 0x0 0x100>,
301 <0x5 0x00000000 0x1 0x00000000>;
305 cdns,trigger-address = <0x0>;
306 clocks = <&k3_clks 248 0>;
307 assigned-clocks = <&k3_clks 248 0>;
312 #size-cells = <0>;
318 reg = <0x0 0x47050000 0x0 0x100>,
319 <0x7 0x00000000 0x1 0x00000000>;
323 cdns,trigger-address = <0x0>;
327 #size-cells = <0>;
336 reg = <0x0 0x46000000 0x0 0x200000>;
338 ranges = <0x0 0x0 0x0 0x46000000 0x0 0x200000>;
344 dmas = <&mcu_udmap 0xf000>,
345 <&mcu_udmap 0xf001>,
346 <&mcu_udmap 0xf002>,
347 <&mcu_udmap 0xf003>,
348 <&mcu_udmap 0xf004>,
349 <&mcu_udmap 0xf005>,
350 <&mcu_udmap 0xf006>,
351 <&mcu_udmap 0xf007>,
352 <&mcu_udmap 0x7000>;
359 #size-cells = <0>;
365 ti,syscon-efuse = <&cpsw_mac_syscon 0x0>;
372 reg = <0x0 0xf00 0x0 0x100>;
374 #size-cells = <0>;
383 reg = <0x0 0x3d000 0x0 0x400>;
392 #clock-cells = <0>;
408 ranges = <0x41000000 0x00 0x41000000 0x20000>,
409 <0x41400000 0x00 0x41400000 0x20000>;
414 reg = <0x41000000 0x00008000>,
415 <0x41010000 0x00008000>;
419 ti,sci-proc-ids = <0x01 0xff>;
429 reg = <0x41400000 0x00008000>,
430 <0x41410000 0x00008000>;
434 ti,sci-proc-ids = <0x02 0xff>;
445 reg = <0x00 0x40800000 0x00 0x1000>;
453 reg = <0x0 0x40610000 0x0 0x100>;
454 clocks = <&k3_clks 135 0>;
456 assigned-clocks = <&k3_clks 135 0>;