17e614b53SNishanth Menon// SPDX-License-Identifier: GPL-2.0-only OR MIT 2f1d17330SVignesh Raghavendra/* 3f1d17330SVignesh Raghavendra * Device Tree Source for AM62 SoC Family 4f1d17330SVignesh Raghavendra * 57e614b53SNishanth Menon * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/ 6f1d17330SVignesh Raghavendra */ 7f1d17330SVignesh Raghavendra 8f1d17330SVignesh Raghavendra#include <dt-bindings/gpio/gpio.h> 9f1d17330SVignesh Raghavendra#include <dt-bindings/interrupt-controller/irq.h> 10f1d17330SVignesh Raghavendra#include <dt-bindings/interrupt-controller/arm-gic.h> 11f1d17330SVignesh Raghavendra#include <dt-bindings/soc/ti,sci_pm_domain.h> 12f1d17330SVignesh Raghavendra 13fe49f2d7SNishanth Menon#include "k3-pinctrl.h" 14fe49f2d7SNishanth Menon 15f1d17330SVignesh Raghavendra/ { 16f1d17330SVignesh Raghavendra model = "Texas Instruments K3 AM625 SoC"; 17f1d17330SVignesh Raghavendra compatible = "ti,am625"; 18f1d17330SVignesh Raghavendra interrupt-parent = <&gic500>; 19f1d17330SVignesh Raghavendra #address-cells = <2>; 20f1d17330SVignesh Raghavendra #size-cells = <2>; 21f1d17330SVignesh Raghavendra 22f1d17330SVignesh Raghavendra chosen { }; 23f1d17330SVignesh Raghavendra 24f1d17330SVignesh Raghavendra firmware { 25f1d17330SVignesh Raghavendra optee { 26f1d17330SVignesh Raghavendra compatible = "linaro,optee-tz"; 27f1d17330SVignesh Raghavendra method = "smc"; 28f1d17330SVignesh Raghavendra }; 29f1d17330SVignesh Raghavendra 30f1d17330SVignesh Raghavendra psci: psci { 31f1d17330SVignesh Raghavendra compatible = "arm,psci-1.0"; 32f1d17330SVignesh Raghavendra method = "smc"; 33f1d17330SVignesh Raghavendra }; 34f1d17330SVignesh Raghavendra }; 35f1d17330SVignesh Raghavendra 36f1d17330SVignesh Raghavendra a53_timer0: timer-cl0-cpu0 { 37f1d17330SVignesh Raghavendra compatible = "arm,armv8-timer"; 38f1d17330SVignesh Raghavendra interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */ 39f1d17330SVignesh Raghavendra <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */ 40f1d17330SVignesh Raghavendra <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */ 41f1d17330SVignesh Raghavendra <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */ 42f1d17330SVignesh Raghavendra }; 43f1d17330SVignesh Raghavendra 44f1d17330SVignesh Raghavendra pmu: pmu { 45f1d17330SVignesh Raghavendra compatible = "arm,cortex-a53-pmu"; 46f1d17330SVignesh Raghavendra interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 47f1d17330SVignesh Raghavendra }; 48f1d17330SVignesh Raghavendra 49f1d17330SVignesh Raghavendra cbass_main: bus@f0000 { 5087e437a0SNishanth Menon bootph-all; 51f1d17330SVignesh Raghavendra compatible = "simple-bus"; 52f1d17330SVignesh Raghavendra #address-cells = <2>; 53f1d17330SVignesh Raghavendra #size-cells = <2>; 54f1d17330SVignesh Raghavendra 55f1d17330SVignesh Raghavendra ranges = <0x00 0x000f0000 0x00 0x000f0000 0x00 0x00030000>, /* Main MMRs */ 56f1d17330SVignesh Raghavendra <0x00 0x00420000 0x00 0x00420000 0x00 0x00001000>, /* ESM0 */ 57f1d17330SVignesh Raghavendra <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */ 58f1d17330SVignesh Raghavendra <0x00 0x00703000 0x00 0x00703000 0x00 0x00000200>, /* USB0 debug trace */ 59f1d17330SVignesh Raghavendra <0x00 0x0070c000 0x00 0x0070c000 0x00 0x00000200>, /* USB1 debug trace */ 60f1d17330SVignesh Raghavendra <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* Timesync router */ 61f1d17330SVignesh Raghavendra <0x00 0x01000000 0x00 0x01000000 0x00 0x01b28400>, /* First peripheral window */ 62f1d17330SVignesh Raghavendra <0x00 0x08000000 0x00 0x08000000 0x00 0x00200000>, /* Main CPSW */ 63f1d17330SVignesh Raghavendra <0x00 0x0e000000 0x00 0x0e000000 0x00 0x01d20000>, /* Second peripheral window */ 64f1d17330SVignesh Raghavendra <0x00 0x0fd00000 0x00 0x0fd00000 0x00 0x00020000>, /* GPU */ 65f1d17330SVignesh Raghavendra <0x00 0x20000000 0x00 0x20000000 0x00 0x0a008000>, /* Third peripheral window */ 66f1d17330SVignesh Raghavendra <0x00 0x30040000 0x00 0x30040000 0x00 0x00080000>, /* PRUSS-M */ 67f1d17330SVignesh Raghavendra <0x00 0x30101000 0x00 0x30101000 0x00 0x00010100>, /* CSI window */ 68f1d17330SVignesh Raghavendra <0x00 0x30200000 0x00 0x30200000 0x00 0x00010000>, /* DSS */ 69f1d17330SVignesh Raghavendra <0x00 0x31000000 0x00 0x31000000 0x00 0x00050000>, /* USB0 DWC3 Core window */ 70f1d17330SVignesh Raghavendra <0x00 0x31100000 0x00 0x31100000 0x00 0x00050000>, /* USB1 DWC3 Core window */ 71*a0286c7bSNitin Yadav <0x00 0x3b000000 0x00 0x3b000000 0x00 0x00000400>, /* GPMC0_CFG */ 72c024c46fSJayesh Choudhary <0x00 0x40900000 0x00 0x40900000 0x00 0x00030000>, /* SA3UL */ 73f1d17330SVignesh Raghavendra <0x00 0x43600000 0x00 0x43600000 0x00 0x00010000>, /* SA3 sproxy data */ 74f1d17330SVignesh Raghavendra <0x00 0x44043000 0x00 0x44043000 0x00 0x00000fe0>, /* TI SCI DEBUG */ 75f1d17330SVignesh Raghavendra <0x00 0x44860000 0x00 0x44860000 0x00 0x00040000>, /* SA3 sproxy config */ 76f1d17330SVignesh Raghavendra <0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>, /* DMSS */ 77*a0286c7bSNitin Yadav <0x00 0x50000000 0x00 0x50000000 0x00 0x08000000>, /* GPMC0 DATA */ 78f1d17330SVignesh Raghavendra <0x00 0x60000000 0x00 0x60000000 0x00 0x08000000>, /* FSS0 DAT1 */ 79f1d17330SVignesh Raghavendra <0x00 0x70000000 0x00 0x70000000 0x00 0x00010000>, /* OCSRAM */ 80f1d17330SVignesh Raghavendra <0x01 0x00000000 0x01 0x00000000 0x00 0x00310000>, /* A53 PERIPHBASE */ 81f1d17330SVignesh Raghavendra <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS0 DAT3 */ 82f1d17330SVignesh Raghavendra 83f1d17330SVignesh Raghavendra /* MCU Domain Range */ 84f1d17330SVignesh Raghavendra <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>, 85f1d17330SVignesh Raghavendra 86f1d17330SVignesh Raghavendra /* Wakeup Domain Range */ 87bbb6dc62SBryan Brattlof <0x00 0x00b00000 0x00 0x00b00000 0x00 0x00002400>, /* VTM */ 88f1d17330SVignesh Raghavendra <0x00 0x2b000000 0x00 0x2b000000 0x00 0x00300400>, 89f1d17330SVignesh Raghavendra <0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>; 90f1d17330SVignesh Raghavendra 91f1d17330SVignesh Raghavendra cbass_mcu: bus@4000000 { 9287e437a0SNishanth Menon bootph-all; 93f1d17330SVignesh Raghavendra compatible = "simple-bus"; 94f1d17330SVignesh Raghavendra #address-cells = <2>; 95f1d17330SVignesh Raghavendra #size-cells = <2>; 96f1d17330SVignesh Raghavendra ranges = <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>; /* Peripheral window */ 97f1d17330SVignesh Raghavendra }; 98f1d17330SVignesh Raghavendra 99bbb6dc62SBryan Brattlof cbass_wakeup: bus@b00000 { 10087e437a0SNishanth Menon bootph-all; 101f1d17330SVignesh Raghavendra compatible = "simple-bus"; 102f1d17330SVignesh Raghavendra #address-cells = <2>; 103f1d17330SVignesh Raghavendra #size-cells = <2>; 104bbb6dc62SBryan Brattlof ranges = <0x00 0x00b00000 0x00 0x00b00000 0x00 0x00002400>, /* VTM */ 105bbb6dc62SBryan Brattlof <0x00 0x2b000000 0x00 0x2b000000 0x00 0x00300400>, /* Peripheral Window */ 106f1d17330SVignesh Raghavendra <0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>; 107f1d17330SVignesh Raghavendra }; 108f1d17330SVignesh Raghavendra }; 109bbb6dc62SBryan Brattlof 1108ccc1073SAradhya Bhatia dss_vp1_clk: clock-divider-oldi { 1118ccc1073SAradhya Bhatia compatible = "fixed-factor-clock"; 1128ccc1073SAradhya Bhatia clocks = <&k3_clks 186 0>; 1138ccc1073SAradhya Bhatia #clock-cells = <0>; 1148ccc1073SAradhya Bhatia clock-div = <7>; 1158ccc1073SAradhya Bhatia clock-mult = <1>; 1168ccc1073SAradhya Bhatia }; 1178ccc1073SAradhya Bhatia 118bbb6dc62SBryan Brattlof #include "k3-am62-thermal.dtsi" 119f1d17330SVignesh Raghavendra}; 120f1d17330SVignesh Raghavendra 121f1d17330SVignesh Raghavendra/* Now include the peripherals for each bus segments */ 122f1d17330SVignesh Raghavendra#include "k3-am62-main.dtsi" 123f1d17330SVignesh Raghavendra#include "k3-am62-mcu.dtsi" 124f1d17330SVignesh Raghavendra#include "k3-am62-wakeup.dtsi" 125