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/freebsd/sys/contrib/device-tree/Bindings/phy/
H A Dbrcm-sata-phy.txt14 - size-cells: should be 0
25 - phy-cells: generic PHY binding; must be 0
39 equalizer value that should be used. Allowed range is 0..63.
44 reg = <0xf0458100 0x1e00>, <0xf045804c 0x10>;
47 #size-cells = <0>;
49 sata-phy@0 {
50 reg = <0>;
51 #phy-cells = <0>;
56 #phy-cells = <0>;
H A Dbrcm,sata-phy.yaml46 const: 0
49 "^sata-phy@[0-9]+$":
60 const: 0
83 minimum: 0
130 reg = <0xf0458100 0x1e00>;
133 #size-cells = <0>;
135 sata-phy@0 {
136 reg = <0>;
137 #phy-cells = <0>;
142 #phy-cells = <0>;
/freebsd/sys/powerpc/powermac/
H A Dviareg.h32 #define vBufB 0x0000 /* register B */
33 #define vDirB 0x0400 /* data direction register */
34 #define vDirA 0x0600 /* data direction register */
35 #define vT1C 0x0800 /* Timer 1 counter Lo */
36 #define vT1CH 0x0a00 /* Timer 1 counter Hi */
37 #define vSR 0x1400 /* shift register */
38 #define vACR 0x1600 /* aux control register */
39 #define vPCR 0x1800 /* peripheral control register */
40 #define vIFR 0x1a00 /* interrupt flag register */
41 #define vIER 0x1c00 /* interrupt enable register */
[all …]
/freebsd/sys/dev/qlnx/qlnxe/
H A Decore_gtt_values.h32 0,
33 0,
34 0x1c02, /* win 2: addr=0x1c02000, size=4096 bytes */
35 0x1c80, /* win 3: addr=0x1c80000, size=4096 bytes */
36 0x1d00, /* win 4: addr=0x1d00000, size=4096 bytes */
37 0x1d01, /* win 5: addr=0x1d01000, size=4096 bytes */
38 0x1d80, /* win 6: addr=0x1d80000, size=4096 bytes */
39 0x1d81, /* win 7: addr=0x1d81000, size=4096 bytes */
40 0x1d82, /* win 8: addr=0x1d82000, size=4096 bytes */
41 0x1e00, /* win 9: addr=0x1e00000, size=4096 bytes */
[all …]
/freebsd/sys/dev/bhnd/bhndb/
H A Dbhndb_pcireg.h36 * - PCI (cid=0x804, revision <= 12)
40 * [0x0000+0x1000] dynamic mapped backplane address space (window 0).
41 * [0x1000+0x0800] fixed SPROM shadow
42 * [0x1800+0x0E00] fixed pci core device registers
43 * [0x1E00+0x0200] fixed pci core siba config registers
47 * - PCI (cid=0x804, revision >= 13)
48 * - PCIE (cid=0x820) with ChipCommon (revision <= 31)
52 * [0x0000+0x1000] dynamic mapped backplane address space (window 0).
53 * [0x1000+0x1000] fixed SPROM shadow
54 * [0x2000+0x1000] fixed pci/pcie core registers
[all …]
H A Dbhndb_pci_hwdata.c68 sizeof(_BHNDB_HW_REQ_ARRAY(__VA_ARGS__)[0])), \
82 * at the default enumeration address (0x18000000).
86 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE },
87 { -1, 0, 0 }
91 /* bar0+0x0000: configurable backplane window */
99 .res = { SYS_RES_MEMORY, PCIR_BAR(0) }
119 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE },
120 { -1, 0, 0 }
124 /* bar0+0x0000: configurable backplane window */
132 .res = { SYS_RES_MEMORY, PCIR_BAR(0) }
[all …]
H A Dbhndb_pci.c211 for (size_t i = 0; !BHNDB_PCI_IS_CORE_END(&bhndb_pci_cores[i]); i++) { in bhndb_pci_find_core()
231 quirks = 0; in bhndb_pci_get_core_quirks()
241 for (size_t i = 0; !BHNDB_PCI_IS_QUIRK_END(&qtable[i]); i++) { in bhndb_pci_get_core_quirks()
349 return (0); in bhndb_pci_alloc_msi()
368 sc->pci_quirks = 0; in bhndb_pci_attach()
408 if (bhndb_pci_alloc_msi(sc, &sc->msi_count) == 0) { in bhndb_pci_attach()
415 sc->msi_count = 0; in bhndb_pci_attach()
416 irq_rid = 0; in bhndb_pci_attach()
422 sc->isrc = bhndb_alloc_intr_isrc(sc->parent, irq_rid, 0, RM_MAX_END, 1, in bhndb_pci_attach()
465 return (0); in bhndb_pci_attach()
[all …]
/freebsd/sys/contrib/dev/iwlwifi/
H A Diwl-context-info.h11 #define CSR_CTXT_INFO_BA 0x40
38 IWL_CTXT_INFO_AUTO_FUNC_INIT = 0x0001,
39 IWL_CTXT_INFO_EARLY_DEBUG = 0x0002,
40 IWL_CTXT_INFO_ENABLE_CDMP = 0x0004,
41 IWL_CTXT_INFO_RB_CB_SIZE = 0x00f0,
42 IWL_CTXT_INFO_TFD_FORMAT_LONG = 0x0100,
43 IWL_CTXT_INFO_RB_SIZE = 0x1e00,
44 IWL_CTXT_INFO_RB_SIZE_1K = 0x1,
45 IWL_CTXT_INFO_RB_SIZE_2K = 0x2,
46 IWL_CTXT_INFO_RB_SIZE_4K = 0x4,
[all …]
/freebsd/sys/contrib/openzfs/tests/zfs-tests/tests/functional/vdev_disk/
H A Dpage_alignment.c65 * physical (order-0) page boundary, as the kernel expects to be able in vdev_disk_check_alignment_cb()
104 return (0); in vdev_disk_check_alignment_cb()
125 512, 0x1000, {
126 { 0x0, 0x1000 },
130 512, 0x400, {
131 { 0x0, 0x1000 },
135 512, 0x400, {
136 { 0x0c00, 0x0400 },
140 512, 0x400, {
141 { 0x0200, 0x0e00 },
[all …]
/freebsd/sys/libkern/
H A Dcrc16.c32 /* CRC table for the CRC-16. The poly is 0x8005 (x16 + x15 + x2 + 1). */
34 0x0000, 0xC0C1, 0xC181, 0x0140, 0xC301, 0x03C0, 0x0280, 0xC241,
35 0xC601, 0x06C0, 0x0780, 0xC741, 0x0500, 0xC5C1, 0xC481, 0x0440,
36 0xCC01, 0x0CC0, 0x0D80, 0xCD41, 0x0F00, 0xCFC1, 0xCE81, 0x0E40,
37 0x0A00, 0xCAC1, 0xCB81, 0x0B40, 0xC901, 0x09C0, 0x0880, 0xC841,
38 0xD801, 0x18C0, 0x1980, 0xD941, 0x1B00, 0xDBC1, 0xDA81, 0x1A40,
39 0x1E00, 0xDEC1, 0xDF81, 0x1F40, 0xDD01, 0x1DC0, 0x1C80, 0xDC41,
40 0x1400, 0xD4C1, 0xD581, 0x1540, 0xD701, 0x17C0, 0x1680, 0xD641,
41 0xD201, 0x12C0, 0x1380, 0xD341, 0x1100, 0xD1C1, 0xD081, 0x1040,
42 0xF001, 0x30C0, 0x3180, 0xF141, 0x3300, 0xF3C1, 0xF281, 0x3240,
[all …]
/freebsd/sys/contrib/device-tree/src/powerpc/
H A Dadder875-redboot.dts24 #size-cells = <0>;
26 PowerPC,875@0 {
28 reg = <0>;
33 timebase-frequency = <0>;
34 bus-frequency = <0>;
35 clock-frequency = <0>;
43 reg = <0 0x01000000>;
51 reg = <0xfa200100 0x40>;
54 0 0 0xfe000000 0x00800000
55 2 0 0xfa100000 0x00008000
[all …]
H A Dadder875-uboot.dts24 #size-cells = <0>;
26 PowerPC,875@0 {
28 reg = <0>;
33 timebase-frequency = <0>;
34 bus-frequency = <0>;
35 clock-frequency = <0>;
43 reg = <0 0x01000000>;
51 reg = <0xff000100 0x40>;
54 0 0 0xfe000000 0x01000000
57 flash@0,0 {
[all …]
H A Dep88xc.dts19 #size-cells = <0>;
21 PowerPC,885@0 {
23 reg = <0x0>;
28 timebase-frequency = <0>;
29 bus-frequency = <0>;
30 clock-frequency = <0>;
38 reg = <0x0 0x0>;
45 reg = <0xfa200100 0x40>;
48 0x0 0x0 0xfc000000 0x4000000
49 0x3 0x0 0xfa000000 0x1000000
[all …]
H A Dmpc885ads.dts19 #size-cells = <0>;
21 PowerPC,885@0 {
23 reg = <0x0>;
28 timebase-frequency = <0>;
29 bus-frequency = <0>;
30 clock-frequency = <0>;
38 reg = <0x0 0x0>;
45 reg = <0xff000100 0x40>;
48 0x0 0x0 0xfe000000 0x800000
49 0x1 0x0 0xff080000 0x8000
[all …]
/freebsd/sys/contrib/device-tree/src/arm/broadcom/
H A Dbcm63138.dtsi23 #size-cells = <0>;
25 cpu@0 {
29 reg = <0>;
46 #clock-cells = <0>;
54 #clock-cells = <0>;
63 #clock-cells = <0>;
72 #clock-cells = <0>;
80 ranges = <0 0x80000000 0x78400
[all...]
/freebsd/crypto/heimdal/lib/wind/
H A Dbidi_table.c9 {0x5be, 1},
10 {0x5c0, 1},
11 {0x5c3, 1},
12 {0x5d0, 0x1b},
13 {0x5f0, 0x5},
14 {0x61b, 1},
15 {0x61f, 1},
16 {0x621, 0x1a},
17 {0x640, 0xb},
18 {0x66d, 0x3},
[all …]
/freebsd/sys/riscv/riscv/
H A Daplic.c78 #define APLIC_DOMAIN_CFG_BE (1UL << 0) /* Endianess */
80 #define APLIC_MODE_DIRECT 0 /* Direct delivery mode */
84 #define APLIC_SRC_CFG_SM_SHIFT 0
85 #define APLIC_SRC_CFG_SM_MASK (0x7UL << APLIC_SRC_CFG_SM_SHIFT)
87 #define APLIC_SRC_CFG_SM_INACTIVE 0 /* APLIC inactive in domain */
95 #define APLIC_DOMAIN_CFG 0x0000
96 #define APLIC_SRC_CFG(_idx) (0x0004 + (((_idx) - 1) * 4))
97 #define APLIC_TARGET(_idx) (0x3004 + (((_idx) - 1) * 4))
98 #define APLIC_MMSIADDRCFG 0x1BC0
99 #define APLIC_MMSIADDRCFGH 0x1BC4
[all …]
/freebsd/sys/dev/bnxt/bnxt_re/
H A Dib_verbs.h41 #define BNXT_RE_ROCE_V2_UDP_SPORT 0x8CD1
42 #define BNXT_RE_QP_RANDOM_QKEY 0x81818181
97 #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_256MB 0x1cUL
488 return 0; in bnxt_re_init_pow2_flag()
508 return 0; in bnxt_re_init_rsvd_wqe_flag()
516 return _is_chip_gen_p5_p7(cctx) ? 0 : BNXT_QPLIB_RESERVED_QP_WRS; in bnxt_re_get_diff()
518 return 0; in bnxt_re_get_diff()
559 return (*(u16 *)a ^ *(u16 *)b) | (a32[0] ^ b32[0]) | in compare_ether_header()
572 /* CRC table for the CRC-16. The poly is 0x8005 (x16 + x15 + x2 + 1). */ in crc16()
574 0x0000, 0xC0C1, 0xC181, 0x0140, 0xC301, 0x03C0, 0x0280, 0xC241, in crc16()
[all …]
/freebsd/usr.sbin/ppp/
H A Dhdlc.c64 /* 00 */ 0x0000, 0x1189, 0x2312, 0x329b, 0x4624, 0x57ad, 0x6536, 0x74bf,
65 /* 08 */ 0x8c48, 0x9dc1, 0xaf5a, 0xbed3, 0xca6c, 0xdbe5, 0xe97e, 0xf8f7,
66 /* 10 */ 0x1081, 0x0108, 0x3393, 0x221a, 0x56a5, 0x472c, 0x75b7, 0x643e,
67 /* 18 */ 0x9cc9, 0x8d40, 0xbfdb, 0xae52, 0xdaed, 0xcb64, 0xf9ff, 0xe876,
68 /* 20 */ 0x2102, 0x308b, 0x0210, 0x1399, 0x6726, 0x76af, 0x4434, 0x55bd,
69 /* 28 */ 0xad4a, 0xbcc3, 0x8e58, 0x9fd1, 0xeb6e, 0xfae7, 0xc87c, 0xd9f5,
70 /* 30 */ 0x3183, 0x200a, 0x1291, 0x0318, 0x77a7, 0x662e, 0x54b5, 0x453c,
71 /* 38 */ 0xbdcb, 0xac42, 0x9ed9, 0x8f50, 0xfbef, 0xea66, 0xd8fd, 0xc974,
72 /* 40 */ 0x4204, 0x538d, 0x6116, 0x709f, 0x0420, 0x15a9, 0x2732, 0x36bb,
73 /* 48 */ 0xce4c, 0xdfc5, 0xed5e, 0xfcd7, 0x8868, 0x99e1, 0xab7a, 0xbaf3,
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Support/
H A DUnicodeCaseFold.cpp5 // http://www.unicode.org/Public/15.1.0/ucd/CaseFolding.txt
9 // "http://www.unicode.org/Public/15.1.0/ucd/CaseFolding.txt" \
17 if (C < 0x0041) in foldCharSimple()
20 if (C <= 0x005a) in foldCharSimple()
23 if (C == 0x00b5) in foldCharSimple()
24 return 0x03bc; in foldCharSimple()
25 if (C < 0x00c0) in foldCharSimple()
28 if (C <= 0x00d6) in foldCharSimple()
30 if (C < 0x00d8) in foldCharSimple()
33 if (C <= 0x00d in foldCharSimple()
[all...]
/freebsd/sys/contrib/device-tree/src/arm/qcom/
H A Dqcom-sdx65.dtsi20 qcom,msm-id = <458 0x10000>, <483 0x10000>, <509 0x10000>;
25 reg = <0 0>;
33 #clock-cells = <0>;
40 #clock-cells = <0>;
46 #clock-cells = <0>;
52 #size-cells = <0>;
54 cpu0: cpu@0 {
[all...]
/freebsd/sys/dev/bxe/
H A D57711_int_offsets.h31 { 0x40, 0x0, 0x0, 0x0, 0x0}, // COMMON_SB_SIZE
32 { 0x40, 0x0, 0x0, 0x0, 0x0}, // COMMON_SB_DATA_SIZE
33 { 0x28, 0x0, 0x0, 0x0, 0x0}, // COMMON_SP_SB_SIZE
34 { 0x10, 0x0, 0x0, 0x0, 0x0}, // COMMON_SP_SB_DATA_SIZE
35 { 0x40, 0x0, 0x0, 0x0, 0x0}, // COMMON_DYNAMIC_HC_CONFIG_SIZE
36 { 0x10, 0x0, 0x0, 0x0, 0x0}, // COMMON_ASM_ASSERT_MSG_SIZE
37 { 0x8, 0x0, 0x0, 0x0, 0x0}, // COMMON_ASM_ASSERT_INDEX_SIZE
38 { 0x0, 0x0, 0x0, 0x0, 0x0}, // COMMON_ASM_INVALID_ASSERT_OPCODE
39 { 0x0, 0x0, 0x0, 0x0, 0x0}, // COMMON_RAM1_TEST_EVENT_ID
40 …{ 0x0, 0x0, 0x0, 0x0, 0x0}, // COMMON_INBOUND_INTERRUPT_TEST_AGG_INT_EVEN…
[all …]
/freebsd/sys/contrib/dev/rtw88/
H A Ddebug.c84 return 0; in rtw_debugfs_close()
122 seq_printf(m, "reg 0x%03x: 0x%02x\n", addr, val); in rtw_debugfs_get_read_reg()
126 seq_printf(m, "reg 0x%03x: 0x%04x\n", addr, val); in rtw_debugfs_get_read_reg()
130 seq_printf(m, "reg 0x%03x: 0x%08x\n", addr, val); in rtw_debugfs_get_read_reg()
133 return 0; in rtw_debugfs_get_read_reg()
151 seq_printf(m, "rf_read path:%d addr:0x%08x mask:0 in rtw_debugfs_get_rf_read()
[all...]
/freebsd/sys/dev/qlxge/
H A Dqls_dump.c92 Q81_PAUSE_SRC_LO = 0x00000100,
93 Q81_PAUSE_SRC_HI = 0x00000104,
94 Q81_GLOBAL_CFG = 0x00000108,
95 Q81_GLOBAL_CFG_RESET = (1 << 0), /*Control*/
99 Q81_TX_CFG = 0x0000010c,
100 Q81_TX_CFG_RESET = (1 << 0), /*Control*/
103 Q81_RX_CFG = 0x00000110,
104 Q81_RX_CFG_RESET = (1 << 0), /*Control*/
107 Q81_FLOW_CTL = 0x0000011c,
108 Q81_PAUSE_OPCODE = 0x00000120,
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/qcom/
H A Dsc8180x.dtsi28 #clock-cells = <0>;
34 #clock-cells = <0>;
42 #size-cells = <0>;
44 CPU0: cpu@0 {
47 reg = <0x0 0x0>;
51 qcom,freq-domain = <&cpufreq_hw 0>;
58 clocks = <&cpufreq_hw 0>;
76 reg = <0x0 0x10
[all...]

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