Lines Matching +full:0 +full:x1e00
68 sizeof(_BHNDB_HW_REQ_ARRAY(__VA_ARGS__)[0])), \
82 * at the default enumeration address (0x18000000).
86 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE },
87 { -1, 0, 0 }
91 /* bar0+0x0000: configurable backplane window */
99 .res = { SYS_RES_MEMORY, PCIR_BAR(0) }
119 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE },
120 { -1, 0, 0 }
124 /* bar0+0x0000: configurable backplane window */
132 .res = { SYS_RES_MEMORY, PCIR_BAR(0) }
135 /* bar0+0x3000: chipc core registers */
142 .unit = 0,
143 .port = 0,
144 .region = 0,
147 .res = { SYS_RES_MEMORY, PCIR_BAR(0) }
170 BHND_MATCH_CORE_UNIT (0)
177 BHND_MATCH_CORE_UNIT (0)
190 BHND_MATCH_CORE_UNIT (0)
197 BHND_MATCH_CORE_UNIT (0)
208 BHND_MATCH_CORE_UNIT (0)
218 BHND_MATCH_CORE_UNIT (0)
225 BHND_MATCH_CORE_UNIT (0)
236 BHND_MATCH_CORE_UNIT (0)
246 BHND_MATCH_CORE_UNIT (0)
253 BHND_MATCH_CORE_UNIT (0)
264 BHND_MATCH_CORE_UNIT (0)
271 BHND_MATCH_CORE_UNIT (0)
274 { NULL, NULL, 0, NULL }
281 * - PCI (cid=0x804, revision <= 12)
285 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE },
286 { -1, 0, 0 }
290 /* bar0+0x0000: configurable backplane window */
298 .res = { SYS_RES_MEMORY, PCIR_BAR(0) }
301 /* bar0+0x1000: sprom shadow */
306 .res = { SYS_RES_MEMORY, PCIR_BAR(0) }
310 * bar0+0x1800: pci core registers.
322 .unit = 0,
323 .port = 0,
324 .region = 0,
327 .res = { SYS_RES_MEMORY, PCIR_BAR(0) }
330 /* bar0+0x1E00: pci core (SSB CFG registers) */
337 .unit = 0,
338 .port = 0,
339 .region = 0,
343 .res = { SYS_RES_MEMORY, PCIR_BAR(0) }
363 * - PCI (cid=0x804, revision >= 13)
367 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE },
368 { -1, 0, 0 }
372 /* bar0+0x0000: configurable backplane window */
380 .res = { SYS_RES_MEMORY, PCIR_BAR(0) }
383 /* bar0+0x1000: sprom shadow */
388 .res = { SYS_RES_MEMORY, PCIR_BAR(0) }
391 /* bar0+0x2000: pci core registers */
398 .unit = 0,
399 .port = 0,
400 .region = 0,
403 .res = { SYS_RES_MEMORY, PCIR_BAR(0) }
406 /* bar0+0x3000: chipc core registers */
413 .unit = 0,
414 .port = 0,
415 .region = 0,
418 .res = { SYS_RES_MEMORY, PCIR_BAR(0) }
438 * - PCIE (cid=0x820) with ChipCommon (revision <= 31)
442 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE },
443 { -1, 0, 0 }
447 /* bar0+0x0000: configurable backplane window */
455 .res = { SYS_RES_MEMORY, PCIR_BAR(0) }
458 /* bar0+0x1000: sprom shadow */
463 .res = { SYS_RES_MEMORY, PCIR_BAR(0) }
466 /* bar0+0x2000: pci core registers */
473 .unit = 0,
474 .port = 0,
475 .region = 0,
478 .res = { SYS_RES_MEMORY, PCIR_BAR(0) }
481 /* bar0+0x3000: chipc core registers */
488 .unit = 0,
489 .port = 0,
490 .region = 0,
493 .res = { SYS_RES_MEMORY, PCIR_BAR(0) }
518 * - PCIE (cid=0x820) with ChipCommon (revision >= 32)
522 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE },
523 { -1, 0, 0 }
527 /* bar0+0x0000: configurable backplane window */
535 .res = { SYS_RES_MEMORY, PCIR_BAR(0) }
538 /* bar0+0x1000: configurable backplane window */
546 .res = { SYS_RES_MEMORY, PCIR_BAR(0) }
549 /* bar0+0x2000: pcie core registers */
556 .unit = 0,
557 .port = 0,
558 .region = 0,
561 .res = { SYS_RES_MEMORY, PCIR_BAR(0) }
564 /* bar0+0x3000: chipc core registers */
571 .unit = 0,
572 .port = 0,
573 .region = 0,
576 .res = { SYS_RES_MEMORY, PCIR_BAR(0) }
601 * - PCIE2 (cid=0x83c)
605 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE },
606 { -1, 0, 0 }
610 /* bar0+0x0000: configurable backplane window */
618 .res = { SYS_RES_MEMORY, PCIR_BAR(0) }
621 /* bar0+0x1000: configurable backplane window */
629 .res = { SYS_RES_MEMORY, PCIR_BAR(0) }
632 /* bar0+0x2000: pcie core registers */
639 .unit = 0,
640 .port = 0,
641 .region = 0,
644 .res = { SYS_RES_MEMORY, PCIR_BAR(0) }
647 /* bar0+0x3000: chipc core registers */
654 .unit = 0,
655 .port = 0,
656 .region = 0,
659 .res = { SYS_RES_MEMORY, PCIR_BAR(0) }