Lines Matching +full:0 +full:x1e00
92 Q81_PAUSE_SRC_LO = 0x00000100,
93 Q81_PAUSE_SRC_HI = 0x00000104,
94 Q81_GLOBAL_CFG = 0x00000108,
95 Q81_GLOBAL_CFG_RESET = (1 << 0), /*Control*/
99 Q81_TX_CFG = 0x0000010c,
100 Q81_TX_CFG_RESET = (1 << 0), /*Control*/
103 Q81_RX_CFG = 0x00000110,
104 Q81_RX_CFG_RESET = (1 << 0), /*Control*/
107 Q81_FLOW_CTL = 0x0000011c,
108 Q81_PAUSE_OPCODE = 0x00000120,
109 Q81_PAUSE_TIMER = 0x00000124,
110 Q81_PAUSE_FRM_DEST_LO = 0x00000128,
111 Q81_PAUSE_FRM_DEST_HI = 0x0000012c,
112 Q81_MAC_TX_PARAMS = 0x00000134,
115 Q81_MAC_RX_PARAMS = 0x00000138,
116 Q81_MAC_SYS_INT = 0x00000144,
117 Q81_MAC_SYS_INT_MASK = 0x00000148,
118 Q81_MAC_MGMT_INT = 0x0000014c,
119 Q81_MAC_MGMT_IN_MASK = 0x00000150,
120 Q81_EXT_ARB_MODE = 0x000001fc,
121 Q81_TX_PKTS = 0x00000200,
122 Q81_TX_PKTS_LO = 0x00000204,
123 Q81_TX_BYTES = 0x00000208,
124 Q81_TX_BYTES_LO = 0x0000020C,
125 Q81_TX_MCAST_PKTS = 0x00000210,
126 Q81_TX_MCAST_PKTS_LO = 0x00000214,
127 Q81_TX_BCAST_PKTS = 0x00000218,
128 Q81_TX_BCAST_PKTS_LO = 0x0000021C,
129 Q81_TX_UCAST_PKTS = 0x00000220,
130 Q81_TX_UCAST_PKTS_LO = 0x00000224,
131 Q81_TX_CTL_PKTS = 0x00000228,
132 Q81_TX_CTL_PKTS_LO = 0x0000022c,
133 Q81_TX_PAUSE_PKTS = 0x00000230,
134 Q81_TX_PAUSE_PKTS_LO = 0x00000234,
135 Q81_TX_64_PKT = 0x00000238,
136 Q81_TX_64_PKT_LO = 0x0000023c,
137 Q81_TX_65_TO_127_PKT = 0x00000240,
138 Q81_TX_65_TO_127_PKT_LO = 0x00000244,
139 Q81_TX_128_TO_255_PKT = 0x00000248,
140 Q81_TX_128_TO_255_PKT_LO = 0x0000024c,
141 Q81_TX_256_511_PKT = 0x00000250,
142 Q81_TX_256_511_PKT_LO = 0x00000254,
143 Q81_TX_512_TO_1023_PKT = 0x00000258,
144 Q81_TX_512_TO_1023_PKT_LO = 0x0000025c,
145 Q81_TX_1024_TO_1518_PKT = 0x00000260,
146 Q81_TX_1024_TO_1518_PKT_LO = 0x00000264,
147 Q81_TX_1519_TO_MAX_PKT = 0x00000268,
148 Q81_TX_1519_TO_MAX_PKT_LO = 0x0000026c,
149 Q81_TX_UNDERSIZE_PKT = 0x00000270,
150 Q81_TX_UNDERSIZE_PKT_LO = 0x00000274,
151 Q81_TX_OVERSIZE_PKT = 0x00000278,
152 Q81_TX_OVERSIZE_PKT_LO = 0x0000027c,
153 Q81_RX_HALF_FULL_DET = 0x000002a0,
154 Q81_TX_HALF_FULL_DET_LO = 0x000002a4,
155 Q81_RX_OVERFLOW_DET = 0x000002a8,
156 Q81_TX_OVERFLOW_DET_LO = 0x000002ac,
157 Q81_RX_HALF_FULL_MASK = 0x000002b0,
158 Q81_TX_HALF_FULL_MASK_LO = 0x000002b4,
159 Q81_RX_OVERFLOW_MASK = 0x000002b8,
160 Q81_TX_OVERFLOW_MASK_LO = 0x000002bc,
161 Q81_STAT_CNT_CTL = 0x000002c0,
162 Q81_STAT_CNT_CTL_CLEAR_TX = (1 << 0), /*Control*/
164 Q81_AUX_RX_HALF_FULL_DET = 0x000002d0,
165 Q81_AUX_TX_HALF_FULL_DET = 0x000002d4,
166 Q81_AUX_RX_OVERFLOW_DET = 0x000002d8,
167 Q81_AUX_TX_OVERFLOW_DET = 0x000002dc,
168 Q81_AUX_RX_HALF_FULL_MASK = 0x000002f0,
169 Q81_AUX_TX_HALF_FULL_MASK = 0x000002f4,
170 Q81_AUX_RX_OVERFLOW_MASK = 0x000002f8,
171 Q81_AUX_TX_OVERFLOW_MASK = 0x000002fc,
172 Q81_RX_BYTES = 0x00000300,
173 Q81_RX_BYTES_LO = 0x00000304,
174 Q81_RX_BYTES_OK = 0x00000308,
175 Q81_RX_BYTES_OK_LO = 0x0000030c,
176 Q81_RX_PKTS = 0x00000310,
177 Q81_RX_PKTS_LO = 0x00000314,
178 Q81_RX_PKTS_OK = 0x00000318,
179 Q81_RX_PKTS_OK_LO = 0x0000031c,
180 Q81_RX_BCAST_PKTS = 0x00000320,
181 Q81_RX_BCAST_PKTS_LO = 0x00000324,
182 Q81_RX_MCAST_PKTS = 0x00000328,
183 Q81_RX_MCAST_PKTS_LO = 0x0000032c,
184 Q81_RX_UCAST_PKTS = 0x00000330,
185 Q81_RX_UCAST_PKTS_LO = 0x00000334,
186 Q81_RX_UNDERSIZE_PKTS = 0x00000338,
187 Q81_RX_UNDERSIZE_PKTS_LO = 0x0000033c,
188 Q81_RX_OVERSIZE_PKTS = 0x00000340,
189 Q81_RX_OVERSIZE_PKTS_LO = 0x00000344,
190 Q81_RX_JABBER_PKTS = 0x00000348,
191 Q81_RX_JABBER_PKTS_LO = 0x0000034c,
192 Q81_RX_UNDERSIZE_FCERR_PKTS = 0x00000350,
193 Q81_RX_UNDERSIZE_FCERR_PKTS_LO = 0x00000354,
194 Q81_RX_DROP_EVENTS = 0x00000358,
195 Q81_RX_DROP_EVENTS_LO = 0x0000035c,
196 Q81_RX_FCERR_PKTS = 0x00000360,
197 Q81_RX_FCERR_PKTS_LO = 0x00000364,
198 Q81_RX_ALIGN_ERR = 0x00000368,
199 Q81_RX_ALIGN_ERR_LO = 0x0000036c,
200 Q81_RX_SYMBOL_ERR = 0x00000370,
201 Q81_RX_SYMBOL_ERR_LO = 0x00000374,
202 Q81_RX_MAC_ERR = 0x00000378,
203 Q81_RX_MAC_ERR_LO = 0x0000037c,
204 Q81_RX_CTL_PKTS = 0x00000380,
205 Q81_RX_CTL_PKTS_LO = 0x00000384,
206 Q81_RX_PAUSE_PKTS = 0x00000388,
207 Q81_RX_PAUSE_PKTS_LO = 0x0000038c,
208 Q81_RX_64_PKTS = 0x00000390,
209 Q81_RX_64_PKTS_LO = 0x00000394,
210 Q81_RX_65_TO_127_PKTS = 0x00000398,
211 Q81_RX_65_TO_127_PKTS_LO = 0x0000039c,
212 Q81_RX_128_255_PKTS = 0x000003a0,
213 Q81_RX_128_255_PKTS_LO = 0x000003a4,
214 Q81_RX_256_511_PKTS = 0x000003a8,
215 Q81_RX_256_511_PKTS_LO = 0x000003ac,
216 Q81_RX_512_TO_1023_PKTS = 0x000003b0,
217 Q81_RX_512_TO_1023_PKTS_LO = 0x000003b4,
218 Q81_RX_1024_TO_1518_PKTS = 0x000003b8,
219 Q81_RX_1024_TO_1518_PKTS_LO = 0x000003bc,
220 Q81_RX_1519_TO_MAX_PKTS = 0x000003c0,
221 Q81_RX_1519_TO_MAX_PKTS_LO = 0x000003c4,
222 Q81_RX_LEN_ERR_PKTS = 0x000003c8,
223 Q81_RX_LEN_ERR_PKTS_LO = 0x000003cc,
224 Q81_MDIO_TX_DATA = 0x00000400,
225 Q81_MDIO_RX_DATA = 0x00000410,
226 Q81_MDIO_CMD = 0x00000420,
227 Q81_MDIO_PHY_ADDR = 0x00000430,
228 Q81_MDIO_PORT = 0x00000440,
229 Q81_MDIO_STATUS = 0x00000450,
230 Q81_TX_CBFC_PAUSE_FRAMES0 = 0x00000500,
231 Q81_TX_CBFC_PAUSE_FRAMES0_LO = 0x00000504,
232 Q81_TX_CBFC_PAUSE_FRAMES1 = 0x00000508,
233 Q81_TX_CBFC_PAUSE_FRAMES1_LO = 0x0000050C,
234 Q81_TX_CBFC_PAUSE_FRAMES2 = 0x00000510,
235 Q81_TX_CBFC_PAUSE_FRAMES2_LO = 0x00000514,
236 Q81_TX_CBFC_PAUSE_FRAMES3 = 0x00000518,
237 Q81_TX_CBFC_PAUSE_FRAMES3_LO = 0x0000051C,
238 Q81_TX_CBFC_PAUSE_FRAMES4 = 0x00000520,
239 Q81_TX_CBFC_PAUSE_FRAMES4_LO = 0x00000524,
240 Q81_TX_CBFC_PAUSE_FRAMES5 = 0x00000528,
241 Q81_TX_CBFC_PAUSE_FRAMES5_LO = 0x0000052C,
242 Q81_TX_CBFC_PAUSE_FRAMES6 = 0x00000530,
243 Q81_TX_CBFC_PAUSE_FRAMES6_LO = 0x00000534,
244 Q81_TX_CBFC_PAUSE_FRAMES7 = 0x00000538,
245 Q81_TX_CBFC_PAUSE_FRAMES7_LO = 0x0000053C,
246 Q81_TX_FCOE_PKTS = 0x00000540,
247 Q81_TX_FCOE_PKTS_LO = 0x00000544,
248 Q81_TX_MGMT_PKTS = 0x00000548,
249 Q81_TX_MGMT_PKTS_LO = 0x0000054C,
250 Q81_RX_CBFC_PAUSE_FRAMES0 = 0x00000568,
251 Q81_RX_CBFC_PAUSE_FRAMES0_LO = 0x0000056C,
252 Q81_RX_CBFC_PAUSE_FRAMES1 = 0x00000570,
253 Q81_RX_CBFC_PAUSE_FRAMES1_LO = 0x00000574,
254 Q81_RX_CBFC_PAUSE_FRAMES2 = 0x00000578,
255 Q81_RX_CBFC_PAUSE_FRAMES2_LO = 0x0000057C,
256 Q81_RX_CBFC_PAUSE_FRAMES3 = 0x00000580,
257 Q81_RX_CBFC_PAUSE_FRAMES3_LO = 0x00000584,
258 Q81_RX_CBFC_PAUSE_FRAMES4 = 0x00000588,
259 Q81_RX_CBFC_PAUSE_FRAMES4_LO = 0x0000058C,
260 Q81_RX_CBFC_PAUSE_FRAMES5 = 0x00000590,
261 Q81_RX_CBFC_PAUSE_FRAMES5_LO = 0x00000594,
262 Q81_RX_CBFC_PAUSE_FRAMES6 = 0x00000598,
263 Q81_RX_CBFC_PAUSE_FRAMES6_LO = 0x0000059C,
264 Q81_RX_CBFC_PAUSE_FRAMES7 = 0x000005A0,
265 Q81_RX_CBFC_PAUSE_FRAMES7_LO = 0x000005A4,
266 Q81_RX_FCOE_PKTS = 0x000005A8,
267 Q81_RX_FCOE_PKTS_LO = 0x000005AC,
268 Q81_RX_MGMT_PKTS = 0x000005B0,
269 Q81_RX_MGMT_PKTS_LO = 0x000005B4,
270 Q81_RX_NIC_FIFO_DROP = 0x000005B8,
271 Q81_RX_NIC_FIFO_DROP_LO = 0x000005BC,
272 Q81_RX_FCOE_FIFO_DROP = 0x000005C0,
273 Q81_RX_FCOE_FIFO_DROP_LO = 0x000005C4,
274 Q81_RX_MGMT_FIFO_DROP = 0x000005C8,
275 Q81_RX_MGMT_FIFO_DROP_LO = 0x000005CC,
276 Q81_RX_PKTS_PRIORITY0 = 0x00000600,
277 Q81_RX_PKTS_PRIORITY0_LO = 0x00000604,
278 Q81_RX_PKTS_PRIORITY1 = 0x00000608,
279 Q81_RX_PKTS_PRIORITY1_LO = 0x0000060C,
280 Q81_RX_PKTS_PRIORITY2 = 0x00000610,
281 Q81_RX_PKTS_PRIORITY2_LO = 0x00000614,
282 Q81_RX_PKTS_PRIORITY3 = 0x00000618,
283 Q81_RX_PKTS_PRIORITY3_LO = 0x0000061C,
284 Q81_RX_PKTS_PRIORITY4 = 0x00000620,
285 Q81_RX_PKTS_PRIORITY4_LO = 0x00000624,
286 Q81_RX_PKTS_PRIORITY5 = 0x00000628,
287 Q81_RX_PKTS_PRIORITY5_LO = 0x0000062C,
288 Q81_RX_PKTS_PRIORITY6 = 0x00000630,
289 Q81_RX_PKTS_PRIORITY6_LO = 0x00000634,
290 Q81_RX_PKTS_PRIORITY7 = 0x00000638,
291 Q81_RX_PKTS_PRIORITY7_LO = 0x0000063C,
292 Q81_RX_OCTETS_PRIORITY0 = 0x00000640,
293 Q81_RX_OCTETS_PRIORITY0_LO = 0x00000644,
294 Q81_RX_OCTETS_PRIORITY1 = 0x00000648,
295 Q81_RX_OCTETS_PRIORITY1_LO = 0x0000064C,
296 Q81_RX_OCTETS_PRIORITY2 = 0x00000650,
297 Q81_RX_OCTETS_PRIORITY2_LO = 0x00000654,
298 Q81_RX_OCTETS_PRIORITY3 = 0x00000658,
299 Q81_RX_OCTETS_PRIORITY3_LO = 0x0000065C,
300 Q81_RX_OCTETS_PRIORITY4 = 0x00000660,
301 Q81_RX_OCTETS_PRIORITY4_LO = 0x00000664,
302 Q81_RX_OCTETS_PRIORITY5 = 0x00000668,
303 Q81_RX_OCTETS_PRIORITY5_LO = 0x0000066C,
304 Q81_RX_OCTETS_PRIORITY6 = 0x00000670,
305 Q81_RX_OCTETS_PRIORITY6_LO = 0x00000674,
306 Q81_RX_OCTETS_PRIORITY7 = 0x00000678,
307 Q81_RX_OCTETS_PRIORITY7_LO = 0x0000067C,
308 Q81_TX_PKTS_PRIORITY0 = 0x00000680,
309 Q81_TX_PKTS_PRIORITY0_LO = 0x00000684,
310 Q81_TX_PKTS_PRIORITY1 = 0x00000688,
311 Q81_TX_PKTS_PRIORITY1_LO = 0x0000068C,
312 Q81_TX_PKTS_PRIORITY2 = 0x00000690,
313 Q81_TX_PKTS_PRIORITY2_LO = 0x00000694,
314 Q81_TX_PKTS_PRIORITY3 = 0x00000698,
315 Q81_TX_PKTS_PRIORITY3_LO = 0x0000069C,
316 Q81_TX_PKTS_PRIORITY4 = 0x000006A0,
317 Q81_TX_PKTS_PRIORITY4_LO = 0x000006A4,
318 Q81_TX_PKTS_PRIORITY5 = 0x000006A8,
319 Q81_TX_PKTS_PRIORITY5_LO = 0x000006AC,
320 Q81_TX_PKTS_PRIORITY6 = 0x000006B0,
321 Q81_TX_PKTS_PRIORITY6_LO = 0x000006B4,
322 Q81_TX_PKTS_PRIORITY7 = 0x000006B8,
323 Q81_TX_PKTS_PRIORITY7_LO = 0x000006BC,
324 Q81_TX_OCTETS_PRIORITY0 = 0x000006C0,
325 Q81_TX_OCTETS_PRIORITY0_LO = 0x000006C4,
326 Q81_TX_OCTETS_PRIORITY1 = 0x000006C8,
327 Q81_TX_OCTETS_PRIORITY1_LO = 0x000006CC,
328 Q81_TX_OCTETS_PRIORITY2 = 0x000006D0,
329 Q81_TX_OCTETS_PRIORITY2_LO = 0x000006D4,
330 Q81_TX_OCTETS_PRIORITY3 = 0x000006D8,
331 Q81_TX_OCTETS_PRIORITY3_LO = 0x000006DC,
332 Q81_TX_OCTETS_PRIORITY4 = 0x000006E0,
333 Q81_TX_OCTETS_PRIORITY4_LO = 0x000006E4,
334 Q81_TX_OCTETS_PRIORITY5 = 0x000006E8,
335 Q81_TX_OCTETS_PRIORITY5_LO = 0x000006EC,
336 Q81_TX_OCTETS_PRIORITY6 = 0x000006F0,
337 Q81_TX_OCTETS_PRIORITY6_LO = 0x000006F4,
338 Q81_TX_OCTETS_PRIORITY7 = 0x000006F8,
339 Q81_TX_OCTETS_PRIORITY7_LO = 0x000006FC,
340 Q81_RX_DISCARD_PRIORITY0 = 0x00000700,
341 Q81_RX_DISCARD_PRIORITY0_LO = 0x00000704,
342 Q81_RX_DISCARD_PRIORITY1 = 0x00000708,
343 Q81_RX_DISCARD_PRIORITY1_LO = 0x0000070C,
344 Q81_RX_DISCARD_PRIORITY2 = 0x00000710,
345 Q81_RX_DISCARD_PRIORITY2_LO = 0x00000714,
346 Q81_RX_DISCARD_PRIORITY3 = 0x00000718,
347 Q81_RX_DISCARD_PRIORITY3_LO = 0x0000071C,
348 Q81_RX_DISCARD_PRIORITY4 = 0x00000720,
349 Q81_RX_DISCARD_PRIORITY4_LO = 0x00000724,
350 Q81_RX_DISCARD_PRIORITY5 = 0x00000728,
351 Q81_RX_DISCARD_PRIORITY5_LO = 0x0000072C,
352 Q81_RX_DISCARD_PRIORITY6 = 0x00000730,
353 Q81_RX_DISCARD_PRIORITY6_LO = 0x00000734,
354 Q81_RX_DISCARD_PRIORITY7 = 0x00000738,
355 Q81_RX_DISCARD_PRIORITY7_LO = 0x0000073C
362 memset(seg_hdr, 0, sizeof(qls_mpid_seg_hdr_t)); in qls_mpid_seg_hdr()
385 return (0); in qls_wait_reg_rdy()
421 int ret = 0; in qls_wr_mpi_reg()
438 #define Q81_TEST_LOGIC_FUNC_PORT_CONFIG 0x1002
439 #define Q81_INVALID_NUM 0xFFFFFFFF
441 #define Q81_NIC1_FUNC_ENABLE 0x00000001
442 #define Q81_NIC1_FUNC_MASK 0x0000000e
444 #define Q81_NIC2_FUNC_ENABLE 0x00000010
445 #define Q81_NIC2_FUNC_MASK 0x000000e0
470 if (ha->pci_func == 0) in qls_get_other_fnum()
483 int ret = 0; in qls_rd_ofunc_reg()
494 if (ret != 0) in qls_rd_ofunc_reg()
530 return (0); in qls_wait_ofunc_reg_rdy()
548 Q81_XG_SERDES_ADDR_RDY, 0); in qls_rd_ofunc_serdes_reg()
558 Q81_XG_SERDES_ADDR_RDY, 0); in qls_rd_ofunc_serdes_reg()
576 int ret = 0; in qls_rd_ofunc_xgmac_reg()
604 Q81_XG_SERDES_ADDR_RDY, 0); in qls_rd_serdes_reg()
613 Q81_XG_SERDES_ADDR_RDY, 0); in qls_rd_serdes_reg()
646 #define Q81_XFI1_POWERED_UP 0x00000005
647 #define Q81_XFI2_POWERED_UP 0x0000000A
648 #define Q81_XAUI_POWERED_UP 0x00000001
658 xfi_d_valid = xfi_ind_valid = xaui_d_valid = xaui_ind_valid = 0; in qls_rd_serdes_regs()
660 xaui_reg = 0x800; in qls_rd_serdes_regs()
664 temp = 0; in qls_rd_serdes_regs()
671 temp = 0; in qls_rd_serdes_regs()
676 ret = qls_rd_serdes_reg(ha, 0x1E06, &temp); in qls_rd_serdes_regs()
678 temp = 0; in qls_rd_serdes_regs()
704 for (i = 0; i <= 0x000000034; i += 4, dptr ++, indptr ++) { in qls_rd_serdes_regs()
717 for (i = 0x800; i <= 0x880; i += 4, dptr ++, indptr ++) { in qls_rd_serdes_regs()
730 for (i = 0x1000; i <= 0x1034; i += 4, dptr ++, indptr ++) { in qls_rd_serdes_regs()
743 for (i = 0x1050; i <= 0x107c; i += 4, dptr ++, indptr ++) { in qls_rd_serdes_regs()
756 for (i = 0x1800; i <= 0x1838; i += 4, dptr++, indptr ++) { in qls_rd_serdes_regs()
769 for (i = 0x1c00; i <= 0x1c1f; i++, dptr ++, indptr ++) { in qls_rd_serdes_regs()
782 for (i = 0x1c40; i <= 0x1c5f; i++, dptr ++, indptr ++) { in qls_rd_serdes_regs()
795 for (i = 0x1e00; i <= 0x1e1f; i++, dptr ++, indptr ++) { in qls_rd_serdes_regs()
800 return(0); in qls_rd_serdes_regs()
816 return 0; in qls_unpause_mpi_risc()
840 return ((count == 0) ? -1 : 0); in qls_pause_mpi_risc()
848 for (i = 0; i < MAX_RX_RINGS; i++, buf++) { in qls_get_intr_states()
849 WRITE_REG32(ha, Q81_CTL_INTR_ENABLE, (0x037f0300 + i)); in qls_get_intr_states()
858 int ret = 0; in qls_rd_xgmac_reg()
881 int ret = 0; in qls_rd_xgmac_regs()
884 for (i = 0; i < Q81_XGMAC_REGISTER_END; i += 4, buf ++) { in qls_rd_xgmac_regs()
1152 return 0; in qls_rd_xgmac_regs()
1158 int i, ret = 0; in qls_get_mpi_regs()
1160 for (i = 0; i < count; i++, buf++) { in qls_get_mpi_regs()
1176 #define Q81_RISC_124 0x0000007c in qls_get_mpi_shadow_regs()
1177 #define Q81_RISC_127 0x0000007f in qls_get_mpi_shadow_regs()
1178 #define Q81_SHADOW_OFFSET 0xb0000000 in qls_get_mpi_shadow_regs()
1180 for (i = 0; i < Q81_MPI_CORE_SH_REGS_CNT; i++, buf++) { in qls_get_mpi_shadow_regs()
1198 #define SYS_CLOCK (0x00)
1199 #define PCI_CLOCK (0x80)
1200 #define FC_CLOCK (0x140)
1201 #define XGM_CLOCK (0x180)
1203 #define Q81_ADDRESS_REGISTER_ENABLE 0x00010000
1204 #define Q81_UP 0x00008000
1205 #define Q81_MAX_MUX 0x40
1206 #define Q81_MAX_MODULES 0x1F
1213 for (module = 0; module < Q81_MAX_MODULES; module ++) { in qls_get_probe()
1215 for (mux_sel = 0; mux_sel < Q81_MAX_MUX; mux_sel++) { in qls_get_probe()
1224 if (mux_sel == 0) { in qls_get_probe()
1251 uint8_t sys_clock_valid_modules[0x20] = { in qls_get_probe_dump()
1252 1, // 0x00 in qls_get_probe_dump()
1253 1, // 0x01 in qls_get_probe_dump()
1254 1, // 0x02 in qls_get_probe_dump()
1255 0, // 0x03 in qls_get_probe_dump()
1256 1, // 0x04 in qls_get_probe_dump()
1257 1, // 0x05 in qls_get_probe_dump()
1258 1, // 0x06 in qls_get_probe_dump()
1259 1, // 0x07 in qls_get_probe_dump()
1260 1, // 0x08 in qls_get_probe_dump()
1261 1, // 0x09 in qls_get_probe_dump()
1262 1, // 0x0A in qls_get_probe_dump()
1263 1, // 0x0B in qls_get_probe_dump()
1264 1, // 0x0C in qls_get_probe_dump()
1265 1, // 0x0D in qls_get_probe_dump()
1266 1, // 0x0E in qls_get_probe_dump()
1267 0, // 0x0F in qls_get_probe_dump()
1268 1, // 0x10 in qls_get_probe_dump()
1269 1, // 0x11 in qls_get_probe_dump()
1270 1, // 0x12 in qls_get_probe_dump()
1271 1, // 0x13 in qls_get_probe_dump()
1272 0, // 0x14 in qls_get_probe_dump()
1273 0, // 0x15 in qls_get_probe_dump()
1274 0, // 0x16 in qls_get_probe_dump()
1275 0, // 0x17 in qls_get_probe_dump()
1276 0, // 0x18 in qls_get_probe_dump()
1277 0, // 0x19 in qls_get_probe_dump()
1278 0, // 0x1A in qls_get_probe_dump()
1279 0, // 0x1B in qls_get_probe_dump()
1280 0, // 0x1C in qls_get_probe_dump()
1281 0, // 0x1D in qls_get_probe_dump()
1282 0, // 0x1E in qls_get_probe_dump()
1283 0 // 0x1F in qls_get_probe_dump()
1286 uint8_t pci_clock_valid_modules[0x20] = { in qls_get_probe_dump()
1287 1, // 0x00 in qls_get_probe_dump()
1288 0, // 0x01 in qls_get_probe_dump()
1289 0, // 0x02 in qls_get_probe_dump()
1290 0, // 0x03 in qls_get_probe_dump()
1291 0, // 0x04 in qls_get_probe_dump()
1292 0, // 0x05 in qls_get_probe_dump()
1293 1, // 0x06 in qls_get_probe_dump()
1294 1, // 0x07 in qls_get_probe_dump()
1295 0, // 0x08 in qls_get_probe_dump()
1296 0, // 0x09 in qls_get_probe_dump()
1297 0, // 0x0A in qls_get_probe_dump()
1298 0, // 0x0B in qls_get_probe_dump()
1299 0, // 0x0C in qls_get_probe_dump()
1300 0, // 0x0D in qls_get_probe_dump()
1301 1, // 0x0E in qls_get_probe_dump()
1302 0, // 0x0F in qls_get_probe_dump()
1303 0, // 0x10 in qls_get_probe_dump()
1304 0, // 0x11 in qls_get_probe_dump()
1305 0, // 0x12 in qls_get_probe_dump()
1306 0, // 0x13 in qls_get_probe_dump()
1307 0, // 0x14 in qls_get_probe_dump()
1308 0, // 0x15 in qls_get_probe_dump()
1309 0, // 0x16 in qls_get_probe_dump()
1310 0, // 0x17 in qls_get_probe_dump()
1311 0, // 0x18 in qls_get_probe_dump()
1312 0, // 0x19 in qls_get_probe_dump()
1313 0, // 0x1A in qls_get_probe_dump()
1314 0, // 0x1B in qls_get_probe_dump()
1315 0, // 0x1C in qls_get_probe_dump()
1316 0, // 0x1D in qls_get_probe_dump()
1317 0, // 0x1E in qls_get_probe_dump()
1318 0 // 0x1F in qls_get_probe_dump()
1321 uint8_t xgm_clock_valid_modules[0x20] = { in qls_get_probe_dump()
1322 1, // 0x00 in qls_get_probe_dump()
1323 0, // 0x01 in qls_get_probe_dump()
1324 0, // 0x02 in qls_get_probe_dump()
1325 1, // 0x03 in qls_get_probe_dump()
1326 0, // 0x04 in qls_get_probe_dump()
1327 0, // 0x05 in qls_get_probe_dump()
1328 0, // 0x06 in qls_get_probe_dump()
1329 0, // 0x07 in qls_get_probe_dump()
1330 1, // 0x08 in qls_get_probe_dump()
1331 1, // 0x09 in qls_get_probe_dump()
1332 0, // 0x0A in qls_get_probe_dump()
1333 0, // 0x0B in qls_get_probe_dump()
1334 1, // 0x0C in qls_get_probe_dump()
1335 1, // 0x0D in qls_get_probe_dump()
1336 1, // 0x0E in qls_get_probe_dump()
1337 0, // 0x0F in qls_get_probe_dump()
1338 1, // 0x10 in qls_get_probe_dump()
1339 1, // 0x11 in qls_get_probe_dump()
1340 0, // 0x12 in qls_get_probe_dump()
1341 0, // 0x13 in qls_get_probe_dump()
1342 0, // 0x14 in qls_get_probe_dump()
1343 0, // 0x15 in qls_get_probe_dump()
1344 0, // 0x16 in qls_get_probe_dump()
1345 0, // 0x17 in qls_get_probe_dump()
1346 0, // 0x18 in qls_get_probe_dump()
1347 0, // 0x19 in qls_get_probe_dump()
1348 0, // 0x1A in qls_get_probe_dump()
1349 0, // 0x1B in qls_get_probe_dump()
1350 0, // 0x1C in qls_get_probe_dump()
1351 0, // 0x1D in qls_get_probe_dump()
1352 0, // 0x1E in qls_get_probe_dump()
1353 0 // 0x1F in qls_get_probe_dump()
1356 uint8_t fc_clock_valid_modules[0x20] = { in qls_get_probe_dump()
1357 1, // 0x00 in qls_get_probe_dump()
1358 0, // 0x01 in qls_get_probe_dump()
1359 0, // 0x02 in qls_get_probe_dump()
1360 0, // 0x03 in qls_get_probe_dump()
1361 0, // 0x04 in qls_get_probe_dump()
1362 0, // 0x05 in qls_get_probe_dump()
1363 0, // 0x06 in qls_get_probe_dump()
1364 0, // 0x07 in qls_get_probe_dump()
1365 0, // 0x08 in qls_get_probe_dump()
1366 0, // 0x09 in qls_get_probe_dump()
1367 0, // 0x0A in qls_get_probe_dump()
1368 0, // 0x0B in qls_get_probe_dump()
1369 1, // 0x0C in qls_get_probe_dump()
1370 1, // 0x0D in qls_get_probe_dump()
1371 0, // 0x0E in qls_get_probe_dump()
1372 0, // 0x0F in qls_get_probe_dump()
1373 0, // 0x10 in qls_get_probe_dump()
1374 0, // 0x11 in qls_get_probe_dump()
1375 0, // 0x12 in qls_get_probe_dump()
1376 0, // 0x13 in qls_get_probe_dump()
1377 0, // 0x14 in qls_get_probe_dump()
1378 0, // 0x15 in qls_get_probe_dump()
1379 0, // 0x16 in qls_get_probe_dump()
1380 0, // 0x17 in qls_get_probe_dump()
1381 0, // 0x18 in qls_get_probe_dump()
1382 0, // 0x19 in qls_get_probe_dump()
1383 0, // 0x1A in qls_get_probe_dump()
1384 0, // 0x1B in qls_get_probe_dump()
1385 0, // 0x1C in qls_get_probe_dump()
1386 0, // 0x1D in qls_get_probe_dump()
1387 0, // 0x1E in qls_get_probe_dump()
1388 0 // 0x1F in qls_get_probe_dump()
1391 qls_wr_mpi_reg(ha, 0x100e, 0x18a20000); in qls_get_probe_dump()
1401 return(0); in qls_get_probe_dump()
1412 for (type = 0; type < 4; type ++) { in qls_get_ridx_registers()
1418 for (idx = 0; idx < idx_max; idx ++) { in qls_get_ridx_registers()
1419 val = 0x04000000 | (type << 16) | (idx << 8); in qls_get_ridx_registers()
1422 r_idx = 0; in qls_get_ridx_registers()
1423 while ((r_idx & 0x40000000) == 0) in qls_get_ridx_registers()
1444 #define Q81_RS_AND_ADR 0x06000000 in qls_get_mac_proto_regs()
1445 #define Q81_RS_ONLY 0x04000000 in qls_get_mac_proto_regs()
1457 for (type = 0; type < Q81_NUM_TYPES; type ++) { in qls_get_mac_proto_regs()
1459 case 0: // CAM in qls_get_mac_proto_regs()
1515 printf("Bad type!!! 0x%08x\n", type); in qls_get_mac_proto_regs()
1516 max_index = 0; in qls_get_mac_proto_regs()
1517 max_offset = 0; in qls_get_mac_proto_regs()
1521 for (index = 0; index < max_index; index ++) { in qls_get_mac_proto_regs()
1522 for (offset = 0; offset < max_offset; offset ++) { in qls_get_mac_proto_regs()
1529 result_index = 0; in qls_get_mac_proto_regs()
1531 while ((result_index & 0x40000000) == 0) in qls_get_mac_proto_regs()
1552 int ret = 0; in qls_get_ets_regs()
1555 for(i = 0; i < 8; i ++, buf ++) { in qls_get_ets_regs()
1557 ((i << 29) | 0x08000000)); in qls_get_ets_regs()
1561 for(i = 0; i < 2; i ++, buf ++) { in qls_get_ets_regs()
1563 ((i << 29) | 0x08000000)); in qls_get_ets_regs()
1581 printf("Failed RISC pause. Status = 0x%.08x\n",ret); in qls_mpi_core_dump()
1585 memset(&(mpi_dump->mpi_global_header), 0, in qls_mpi_core_dump()
1618 for (i = 0; i < 64; i++) in qls_mpi_core_dump()
1622 for (i = 0; i < 64; i++) in qls_mpi_core_dump()
1627 qls_rd_xgmac_regs(ha, &mpi_dump->xgmac2[0], 0); in qls_mpi_core_dump()
1628 qls_rd_xgmac_regs(ha, &mpi_dump->xgmac1[0], 1); in qls_mpi_core_dump()
1630 for (i = 0; i < 64; i++) in qls_mpi_core_dump()
1634 for (i = 0; i < 64; i++) in qls_mpi_core_dump()
1639 qls_rd_xgmac_regs(ha, &mpi_dump->xgmac1[0], 0); in qls_mpi_core_dump()
1640 qls_rd_xgmac_regs(ha, &mpi_dump->xgmac2[0], 1); in qls_mpi_core_dump()
1746 ret = qls_get_mpi_regs(ha, &mpi_dump->mpi_core_regs[0], in qls_mpi_core_dump()
1750 &mpi_dump->mpi_core_sh_regs[0]); in qls_mpi_core_dump()
1758 ret = qls_get_mpi_regs(ha, &mpi_dump->test_logic_regs[0], in qls_mpi_core_dump()
1766 ret = qls_get_mpi_regs(ha, &mpi_dump->rmii_regs[0], in qls_mpi_core_dump()
1774 ret = qls_get_mpi_regs(ha, &mpi_dump->fcmac1_regs[0], in qls_mpi_core_dump()
1782 ret = qls_get_mpi_regs(ha, &mpi_dump->fcmac2_regs[0], in qls_mpi_core_dump()
1790 ret = qls_get_mpi_regs(ha, &mpi_dump->fc1_mbx_regs[0], in qls_mpi_core_dump()
1798 ret = qls_get_mpi_regs(ha, &mpi_dump->ide_regs[0], in qls_mpi_core_dump()
1806 ret = qls_get_mpi_regs(ha, &mpi_dump->nic1_mbx_regs[0], in qls_mpi_core_dump()
1814 ret = qls_get_mpi_regs(ha, &mpi_dump->smbus_regs[0], in qls_mpi_core_dump()
1822 ret = qls_get_mpi_regs(ha, &mpi_dump->fc2_mbx_regs[0], in qls_mpi_core_dump()
1830 ret = qls_get_mpi_regs(ha, &mpi_dump->nic2_mbx_regs[0], in qls_mpi_core_dump()
1839 ret = qls_get_mpi_regs(ha, &mpi_dump->i2c_regs[0], in qls_mpi_core_dump()
1847 ret = qls_get_mpi_regs(ha, &mpi_dump->memc_regs[0], in qls_mpi_core_dump()
1855 ret = qls_get_mpi_regs(ha, &mpi_dump->pbus_regs[0], in qls_mpi_core_dump()
1863 ret = qls_get_mpi_regs(ha, &mpi_dump->mde_regs[0], in qls_mpi_core_dump()
1871 qls_get_intr_states(ha, &mpi_dump->intr_states[0]); in qls_mpi_core_dump()
1878 qls_get_probe_dump(ha, &mpi_dump->probe_dump[0]); in qls_mpi_core_dump()
1885 qls_get_ridx_registers(ha, &mpi_dump->routing_regs[0]); in qls_mpi_core_dump()
1892 qls_get_mac_proto_regs(ha, &mpi_dump->mac_prot_regs[0]); in qls_mpi_core_dump()
1899 ret = qls_get_ets_regs(ha, &mpi_dump->ets[0]); in qls_mpi_core_dump()
1906 for(i = 0; i < Q81_MAX_SEMAPHORE_FUNCTIONS ; i ++) { in qls_mpi_core_dump()
1913 if (ret != 0) in qls_mpi_core_dump()
1919 printf("Failed RISC unpause. Status = 0x%.08x\n",ret); in qls_mpi_core_dump()
1923 printf("Failed RISC reset. Status = 0x%.08x\n",ret); in qls_mpi_core_dump()
1925 WRITE_REG32(ha, Q81_CTL_FUNC_SPECIFIC, 0x80008000); in qls_mpi_core_dump()
1932 ret = qls_mbx_dump_risc_ram(ha, &mpi_dump->memc_ram[0], in qls_mpi_core_dump()
1935 printf("Failed Dump of MEMC RAM. Status = 0x%.08x\n",ret); in qls_mpi_core_dump()
1942 ret = qls_mbx_dump_risc_ram(ha, &mpi_dump->memc_ram[0], in qls_mpi_core_dump()
1945 printf("Failed Dump of CODE RAM. Status = 0x%.08x\n",ret); in qls_mpi_core_dump()
1967 return 0; in qls_mpi_core_dump()