Lines Matching +full:0 +full:x1e00
20 qcom,msm-id = <458 0x10000>, <483 0x10000>, <509 0x10000>;
25 reg = <0 0>;
33 #clock-cells = <0>;
40 #clock-cells = <0>;
46 #clock-cells = <0>;
52 #size-cells = <0>;
54 cpu0: cpu@0 {
57 reg = <0x0>;
115 reg = <0x8fcad000 0x40000>;
120 reg = <0x8fcfd000 0x1000>;
125 reg = <0x8fd00000 0x80000>;
130 reg = <0x8fd80000 0x80000>;
135 reg = <0x8fe00000 0x20000>;
140 reg = <0x8fe20000 0xc0000>;
147 reg = <0x8fee0000 0x20000>;
153 reg = <0x8ff00000 0x100000>;
158 reg = <0x90000000 0x500000>;
163 reg = <0x15800000 0x800000>;
172 qcom,local-pid = <0>;
206 reg = <0x00100000 0x001f7400>;
211 <0>;
224 reg = <0x00831000 0x200>;
234 reg = <0xff4000 0x120>;
235 #phy-cells = <0>;
244 reg = <0x00ff6000 0x2000>;
255 #clock-cells = <0>;
256 #phy-cells = <0>;
269 reg = <0x01620000 0x31200>;
276 reg = <0x01b04000 0x1c000>;
281 qcom,ee = <0>;
288 reg = <0x01b30000 0x10000>;
290 #size-cells = <0>;
295 dmas = <&qpic_bam 0>,
304 reg = <0x01c00000 0x3000>,
305 <0x40000000 0xf1d>,
306 <0x40000f20 0xa8>,
307 <0x40001000 0x1000>,
308 <0x40200000 0x100000>,
309 <0x01c03000 0x3000>;
317 qcom,perst-regs = <&tcsr 0xb258 0xb270>;
354 reg = <0x01c06000 0x2000>;
375 #clock-cells = <0>;
378 #phy-cells = <0>;
385 reg = <0x01f40000 0x40000>;
391 reg = <0x01fc0000 0x1000>;
397 reg = <0x03f40000 0x10000>,
398 <0x03f50000 0x5000>,
399 <0x03e04000 0xfc000>;
406 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
413 iommus = <&apps_smmu 0x5e0 0x0>,
414 <&apps_smmu 0x5e2 0x0>;
424 qcom,smem-states = <&ipa_smp2p_out 0>,
434 reg = <0x04080000 0x4040>;
437 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
452 qcom,smem-states = <&modem_smp2p_out 0>;
467 reg = <0x08804000 0x1000>;
480 reg = <0x09680000 0x27200>;
487 reg = <0x0a6f8800 0x400>;
521 reg = <0x0a600000 0xcd00>;
523 iommus = <&apps_smmu 0x1a0 0x0>;
533 reg = <0x0c264000 0x1000>;
538 reg = <0xc440000 0xd00>,
539 <0xc600000 0x2000000>,
540 <0xe600000 0x100000>,
541 <0xe700000 0xa0000>,
542 <0xc40a000 0x26000>;
549 #size-cells = <0>;
550 qcom,channel = <0>;
551 qcom,ee = <0>;
556 reg = <0xf100000 0x300000>;
560 gpio-ranges = <&tlmm 0 0 109>;
568 reg = <0xb210000 0x10000>;
569 qcom,pdc-ranges = <0 147 52>, <52 266 32>;
577 reg = <0x1468f000 0x1000>;
578 ranges = <0x0 0x1468f000 0x1000>;
584 reg = <0x94c 0xc8>;
590 reg = <0x15000000 0x40000>;
633 reg = <0x17800000 0x1000>,
634 <0x17802000 0x1000>;
639 reg = <0x17808000 0x1000>;
642 #clock-cells = <0>;
647 reg = <0x17810000 0x2000>;
651 #clock-cells = <0>;
656 reg = <0x17817000 0x1000>;
665 reg = <0x17820000 0x1000>;
669 frame-number = <0>;
670 interrupts = <GIC_SPI 7 0x4>,
671 <GIC_SPI 6 0x4>;
672 reg = <0x17821000 0x1000>,
673 <0x17822000 0x1000>;
678 interrupts = <GIC_SPI 8 0x4>;
679 reg = <0x17823000 0x1000>;
685 interrupts = <GIC_SPI 9 0x4>;
686 reg = <0x17824000 0x1000>;
692 interrupts = <GIC_SPI 10 0x4>;
693 reg = <0x17825000 0x1000>;
699 interrupts = <GIC_SPI 11 0x4>;
700 reg = <0x17826000 0x1000>;
706 interrupts = <GIC_SPI 12 0x4>;
707 reg = <0x17827000 0x1000>;
713 interrupts = <GIC_SPI 13 0x4>;
714 reg = <0x17828000 0x1000>;
720 interrupts = <GIC_SPI 14 0x4>;
721 reg = <0x17829000 0x1000>;
729 reg = <0x17830000 0x10000>,
730 <0x17840000 0x10000>;
731 reg-names = "drv-0", "drv-1";
734 qcom,tcs-offset = <0xd00>;
807 interrupts = <1 13 0xf08>,
808 <1 12 0xf08>,
809 <1 10 0xf08>,
810 <1 11 0xf08>;